TWI262966B - Electrochemical electroplating method - Google Patents
Electrochemical electroplating method Download PDFInfo
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- TWI262966B TWI262966B TW93109864A TW93109864A TWI262966B TW I262966 B TWI262966 B TW I262966B TW 93109864 A TW93109864 A TW 93109864A TW 93109864 A TW93109864 A TW 93109864A TW I262966 B TWI262966 B TW I262966B
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- copper
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- electrochemical plating
- plating method
- electrochemical
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000009713 electroplating Methods 0.000 title abstract description 15
- 229910052802 copper Inorganic materials 0.000 claims abstract description 58
- 239000010949 copper Substances 0.000 claims abstract description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 57
- 230000000737 periodic effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims description 29
- 239000013078 crystal Substances 0.000 claims 3
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000005868 electrolysis reaction Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000003792 electrolyte Substances 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000009662 stress testing Methods 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Electroplating Methods And Accessories (AREA)
Abstract
Description
1262966 五、發明說明u) [發明所屬之技術領域] 本發明係有關於一種電化學電鍍方法,特別是有關於 一種執行週期性電鍍及電解之電化學電鍍方法。 [先前技術] 在半導體元件的製程中,由於線寬的要求愈來愈狹 窄,因此,在0 . 1 8微米或更窄的導線製程中,銅金屬已經 取代鋁金屬而成為較佳之導線材料,以符合對於時間(RC) 延遲的要求。尤其是當線寬很小時,是使用化學氣相沉積 技術來形成銅導電層,以獲得較平坦的薄膜層◦通常,化 學氣相沉積形成銅層的技術是使用含有有機物的化學物質 作為來源氣體,所形成的銅層電阻率較高,尤其是當銅層 的厚度減少時,電阻率將更增加。再者,在化學氣相沉積 後所產生的殘留物,會造成銅層及後續沉積薄膜層間附著 性的問題,且化學氣相沉積成本較高。 因此,目前業界多採用電化學電鍍 (electrochemical plating,ECP)技術來形成銅導電 層,其成本較低且不會增加銅層電阻率,但預定被沉積基 底之區域上須具有一傳導層或先形成一導電晶種層。然 而,電解液中通常具有一些雜質,例如有機物等化學物 質,上述物質若附著於所形成之銅導電層中,此銅導電層 之電阻率較高,尤其是當銅層的厚度減少時,電阻率將更 增力口 。 傳統技術採用一種交錯執行電鍍及電解之電化學電鍍1262966 V. INSTRUCTION DESCRIPTION u) [Technical Field to Which the Invention Is Ascribed] The present invention relates to an electrochemical plating method, and more particularly to an electrochemical plating method for performing periodic plating and electrolysis. [Prior Art] In the manufacturing process of a semiconductor element, since the line width requirement becomes narrower and narrower, copper metal has replaced aluminum metal as a preferable wire material in a wire process of 0.18 μm or less. To meet the requirements for time (RC) delay. Especially when the line width is small, the chemical vapor deposition technique is used to form the copper conductive layer to obtain a relatively flat film layer. Generally, the technique of chemical vapor deposition to form a copper layer is to use a chemical containing organic substances as a source gas. The formed copper layer has a high resistivity, especially when the thickness of the copper layer is reduced, the resistivity is further increased. Furthermore, the residue generated after chemical vapor deposition causes problems in adhesion between the copper layer and the subsequently deposited thin film layer, and the chemical vapor deposition cost is high. Therefore, at present, electrochemical plating (ECP) technology is often used in the industry to form a copper conductive layer, which is low in cost and does not increase the resistivity of the copper layer, but a region to be deposited must have a conductive layer or A conductive seed layer is formed. However, the electrolyte usually has some impurities, such as organic substances, such as organic substances. If the above substances are attached to the formed copper conductive layer, the resistivity of the copper conductive layer is high, especially when the thickness of the copper layer is reduced. The rate will be even stronger. Conventional technology uses an electrochemical plating that alternates between electroplating and electrolysis
0503-716nW(Nl) ; TSMC2001 -1058 ; Robert.ptd 第4頁 1262966 ——-- 五、發明說明(2) :ΐ ΐ ; ΐ : ί屬導線。參閱第1圖,第1圖係顯示採用交 晶圓Η中购& 意圖。在此以待電鍍 鑛製程時,需;;曰種層12為例。於執行電化學電 極16供應雷寺電鍍晶圓1〇置於電解液14中,接著以電 第2圖所-^銅晶種層1 2以執行電化學電鍍,其波形如 。不。父錯執行電鍍及電解之電化學電铲f置,1 於電極16所供應之電 匕?鍍衣= APPLIED MATFpt at 〇 只电乂錯之組合,例如由 電時,此時豐々 售之ECP裝置。當供應之電壓為正 形成。而當種=執行電鑛之動作,因此銅層逐漸 行電解之動作:、位負電時’此時對銅晶種層12執 子,在此::,】=銅層表面之銅金屬將電離為銅離 尖端放電之效應,上述之 :^起或尖知,由於 加負電具要產生之突起或尖端。再者,施 液中帶負電之雜質,負:J:f電能夠排斥電解 銅表面,因此必須妥盖押制中 所廿者於電鍍所形成之 換頻率。傳統技術所負電切 波形頻率為〇·32Ηζ。 、 、 _為25V,而電壓 當將傳統技術所形成一 銅層此時所受之應力 _ ς =應力測試時,發現 dyne/cm2。此代声縮力其值為- 1.5 0 9E08 銅層執行ECP製程後=過f之雜質°其原因在於當 低時,若為Λ之銅?再加一道回火製程,當溫度降 W之ΙΠ ’其收縮程度理當大於其周圍之基 0503-7161TWF(Nl);TSMC2〇〇l-i〇58;Robert. ptd 第5頁 12629660503-716nW(Nl) ; TSMC2001 -1058 ; Robert.ptd Page 4 1262966 ——-- V. Description of invention (2) : ΐ ΐ ; ΐ : 属 is a wire. Referring to Fig. 1, Fig. 1 shows the intention to use the " Here, the electroplating process is required, and the seed layer 12 is taken as an example. The electroplating wafer 16 is supplied to the electrochemical electrode 16 to be placed in the electrolyte 14, and then the electroplating is performed by electroplating with a copper seed layer 12 as shown in Fig. 2. Do not. The father performs the electroplating and electrolysis of the electrochemical shovel f, 1 is the electricity supplied by the electrode 16? Plating = APPLIED MATFpt at 〇 Only a combination of electric and erroneous, for example, when the electricity is used, the ECP device sold at this time. When the voltage supplied is positive. And when the species = the action of the electric ore, the copper layer gradually undergoes the action of electrolysis: when the position is negative, 'the copper seed layer 12 is held at this time, here::,] = the copper metal on the surface of the copper layer will be ionized For the effect of copper from the tip discharge, the above: or the tip, due to the negative electric appliance to produce the protrusion or tip. Furthermore, the negatively charged impurities in the solution, negative: J: f electricity can repel the surface of the electrolytic copper, so it is necessary to properly switch the frequency formed by the plating. The negative frequency of the conventional technique is 〇·32Ηζ. , , _ is 25V, and the voltage is dyne/cm2 when the stress of the copper layer formed by the conventional technique is _ ς = stress test. The value of this generation of sound reduction is -1.5 0 9E08 After the copper layer performs the ECP process = the impurities of the f. The reason is that when it is low, if it is copper? Add a tempering process. When the temperature drops by ΙΠ, the degree of shrinkage is greater than the base around it. 0503-7161TWF(Nl); TSMC2〇〇l-i〇58; Robert. ptd Page 5 1262966
底,此為金屬材質 張力(為基底所拉 壓縮力,代表其收 基底所擠壓,可見 之程度,顯示必須 之特性,因此鋼層此 扯),然而,若銅層 縮程度小於其周圍之 其内部含雜質過多而 改進銅層内部之雜質 時所受之應力應為 此時所受之應力為 基底,而被收縮之 影響其降溫時收縮 含量。 [發明内容] 本發明主要目的在於 明所揭露之電化學電 衝電壓以及較高頻之 程,如此一來,即可 一種電化學電鍍方 驟。首先提供一基 溝槽形成一銅晶種 由一電錢電極提供具 晶種層,上述週期波 ’而上述負脈衝之震 上述銅層。 有鑑於此,為了解決上述問題, 提供一種電化學電鍍方法,根據本發 鐘方法,其利用較傳統技術小之負脈 之正負電切換頻率執行電化學電鑛製 有效提高所形成之銅的純度。 為獲致上述之目的,本發明提出 法,適用於形成一銅層,包括下列步 底,上述具有一溝槽。接著,於上述 層,接著,執行電化學電鍍步驟,藉 有正脈衝及負脈衝之週期波至上述鋼 之頻率係位於0·5Ηζ〜40Hz之範圍内 幅係位於1〜7伏特之範圍内,以形成 [實施方式] 實施例·· 第3圖係顯示根據本 程之操作流程圖。而第4 A圖〜第4 Γ FI总祐-上丨 巷級衣 弟4C圖係顯不對應於第3圖Bottom, this is the tensile force of the metal material (the compression force of the substrate, which represents the extrusion of the substrate, the degree of visibility, showing the necessary characteristics, so the steel layer is pulled), however, if the copper layer is less than the surrounding The stress contained in the interior of the copper layer is excessively controlled by impurities, and the stress applied to the inside of the copper layer should be the substrate at which the stress is applied, and the shrinkage affects the shrinkage content when it is cooled. SUMMARY OF THE INVENTION The main object of the present invention is to disclose the electrochemical voltage and the higher frequency process, and thus, an electrochemical plating process. First, a base trench is provided to form a copper seed. A seed layer is provided by a battery electrode, and the periodic wave ′ and the negative pulse shocks the copper layer. In view of the above, in order to solve the above problems, an electrochemical plating method is provided. According to the method of the present invention, the electrochemical power generation system is used to effectively improve the purity of the formed copper by using the positive and negative switching frequency of the negative pulse of the conventional pulse. . In order to achieve the above object, the present invention is directed to forming a copper layer comprising the following steps, the above having a trench. Next, in the above layer, and then performing an electrochemical plating step, the period of the positive pulse and the negative pulse to the steel is in the range of 0·5 Ηζ 40 40 Hz, and the frame is in the range of 1 to 7 volts. [Formulation] Embodiments·· Fig. 3 shows an operation flow chart according to the present process. And the 4th figure ~ the 4th Γ FI total blessing - Shangyu Lane class 4 brother figure does not correspond to the 3rd figure
12629661262966
1262966 —--- 五、發明說明(5) 為銅離子。根據本發 0二絕對值係小於7伏特,而電負脈衝所供應之電 〇.5h至4〇Hz之間,較佳實施例形頻率範圍係位於 伏特’而電壓波形頻率為4HZ、,H所供應之電壓為 所1歷之時間約為1-10分鐘。 執行電化學電鍍製 , 在此之時,若銅層表面具有里營― 1端放電之效應,上述之突起突起或尖端,由於 c銅時不必要產生之突起。ί行電離,因此有 册:有另外一項優點,此優點在於負雷二再者,施加負 Τ負電之雜質,避免負離子雜質附=^夠排斥電解液中 !,二此必須妥善控制電極2 電=斤:成之銅表 ί。在本發明實施例中,將電塵波;正負電切換頻 具有,著改善銅層純度之效果。員率提咼為4ΗΖ ’即 當將本發明實施例所揭露之 銅插塞執行應力測試時,發現鋼=鑛方法所形成之 力二其值為i.謂08 dyne/cm2。日此==之應力為併張、 相當的少。其原因在於當銅層執行ECP ^程分 一道回火製程,當溫度降低時 衣私後必須再加 度理當大於苴 _ 、右為較純之銅,其收縮程 層此時所受之應力應;二二^金屬材質之特性,因此銅 形成之銅層所受之應力為i縮力之情形,顯示= I月已有效減少銅層内部之雜質含量。 所征ΐ閱第7圖’第7圖係顯示負脈衝之電壓值對應於電極 所供應電壓頻率之曲線圖。如第7圖所示,斜線部分之區1262966 —--- V. Description of invention (5) is copper ion. According to the present invention, the absolute value is less than 7 volts, and the electrical pulse supplied by the electrical negative pulse is between 5 and 4 Hz. The preferred embodiment has a frequency range of volts and the voltage waveform frequency is 4 Hz, H. The voltage supplied is approximately 1-10 minutes for a period of one. Electrochemical plating is performed. At this time, if the surface of the copper layer has the effect of the discharge of the inner-to-one end, the above-mentioned protruding protrusions or tips are unnecessary protrusions due to c-copper. ί 行 ionization, therefore there is a book: there is another advantage, this advantage lies in the negative Ray two again, the application of negative and negative negative impurities, to avoid negative ion impurities attached = ^ enough to repel the electrolyte! Second, the electrode 2 must be properly controlled Electricity = Jin: Cheng copper table ί. In the embodiment of the present invention, the electric dust wave; the positive and negative electric switching frequency has the effect of improving the purity of the copper layer. When the copper plug is exposed to stress test, the force formed by the steel=mine method is found to be i., 08 dyne/cm2. On this day, the stress of == is less, and is relatively small. The reason is that when the copper layer performs the ECP process, a tempering process, when the temperature is lowered, it must be added after the clothing is more than 苴 _, the right is pure copper, and the stress of the shrinkage layer at this time should be The characteristics of the metal material, so the stress on the copper layer formed by copper is the case of i-shrinkage, showing that =I month has effectively reduced the impurity content inside the copper layer. Figure 7 is a diagram showing the voltage value of the negative pulse corresponding to the voltage frequency supplied by the electrode. As shown in Figure 7, the area of the diagonal line
1262966 五、發明說明(6) 域代表對形 另一部份代 統技術所使 域c C點), 明實施例所 應力測試結 施例所述之 技術之純度 再者, 以限定本發 根據本發明 不脫離本發 飾,因此本 定者為準。 成之銅層執行應力測試結果為張力之區域,而 表執行應力測試結果為壓縮力之區域。根據傳 用之參數,其位於應力測試結果為壓縮力之區 結果形成銅層之純度當然不良,而根據本發 述之電化學電鍍方法,其所使用之參數係位於 果為張力之區域(D點),顯示根據本發明實 電化學電鍍方法所形成之銅層具有遠優於傳統 〇 本發明雖以較佳實施例揭露如上,然其並非用 明的範圍,於第7圖中所標示之斜線區域皆為 可應用之實施範圍,任何熟習此項技藝者,在 明之精神和範圍内,當可做些許的更動與潤 發明之保護範圍當視後附之申請專利範圍所界1262966 V. Inventive Note (6) The domain represents the other part of the sub-system technology to make the domain c C), the purity of the technique described in the stress test test example of the embodiment is further limited to The present invention is not deviated from the hair accessories, and therefore the present invention prevails. The resulting copper layer performs stress testing as the area of tension, while the table performs stress testing as the area of compressive force. According to the parameters of the transfer, the purity of the copper layer formed by the stress test result is a poor result, and according to the electrochemical plating method of the present invention, the parameter used is located in the region of the tension (D). Point), showing that the copper layer formed by the electrochemical plating method according to the present invention has much better advantages than the conventional one. Although the invention is disclosed in the preferred embodiment as above, it is not intended to be used in the scope of the present invention. The slashed areas are applicable to the scope of application. Anyone who is familiar with the art, within the spirit and scope of the Ming Dynasty, can make a few changes and protect the scope of the invention.
0503-7161TWF(Nl) ; TSMC2001-1058 ; Robert.ptd 第9頁 1262966 圖式簡單說明 為使本發明之上述目的、特徵和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖示說明: 第1圖係顯示採用交錯執行電鍍及電解之電化學電鍍 的示意圖。 第2圖係顯示傳統技術於執行電鍍及電解之電化學電 鍍時,電極供應電壓至銅晶種層之電壓波形。 第3圖係顯示根據本發明實施例所述之半導體電鍍製 程之操作流程圖。 第4 A圖〜第4C圖係顯示對應於第3圖之半導體剖面 圖。 第5圖係顯示根據本發明實施例採用交錯執行電鍍及 電解之電化學電鍍的示意圖。 第6圖係顯示根據本發明實施例於執行電鍍及電解之 電化學電鍍時,電極供應電壓至銅晶種層之電壓波形。 第7圖係顯示負脈衝之電壓值對應於電極所供應電壓 頻率之曲線圖。 符號說明: 1 0 、2 0〜晶圓; 2 1〜溝槽; 1 2、2 2〜銅晶種層;0503-7161TWF(Nl); TSMC2001-1058; Robert.ptd Page 9 1262966 BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment is described below The drawings are described in detail as follows: Illustration: Fig. 1 is a schematic view showing electrochemical plating using staggered electroplating and electrolysis. Fig. 2 is a view showing the voltage waveform of the electrode supply voltage to the copper seed layer in the conventional technique for performing electroplating of electroplating and electrolysis. Figure 3 is a flow chart showing the operation of a semiconductor electroplating process in accordance with an embodiment of the present invention. 4A to 4C are sectional views showing the semiconductor corresponding to Fig. 3. Figure 5 is a schematic view showing electrochemical plating using staggered electroplating and electrolysis according to an embodiment of the present invention. Fig. 6 is a view showing a voltage waveform of an electrode supply voltage to a copper seed layer in performing electrochemical plating for electroplating and electrolysis according to an embodiment of the present invention. Figure 7 shows a graph of the voltage value of the negative pulse corresponding to the voltage supplied by the electrode. DESCRIPTION OF SYMBOLS: 1 0 , 2 0~ wafer; 2 1~ trench; 1 2, 2 2~ copper seed layer;
0503-716nW(Nl) ; TSMC2001-1058 ; Robert.ptd 第10頁 1262966 圖式簡早說明 1 4、2 4〜電解液; 1 6、2 6〜電極。 第11頁 0503-7161TWF(Nl) ; TSMC2001-1058 ; Robert.ptd __10503-716nW(Nl) ; TSMC2001-1058 ; Robert.ptd Page 10 1262966 Schematic description 1 4, 2 4 ~ electrolyte; 1 6, 2 6 ~ electrode. Page 11 0503-7161TWF(Nl) ; TSMC2001-1058 ; Robert.ptd __1
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