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TWI261862B - Semiconductor module with high manufacture precision, method for making such module, and semiconductor device - Google Patents

Semiconductor module with high manufacture precision, method for making such module, and semiconductor device Download PDF

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Publication number
TWI261862B
TWI261862B TW094115866A TW94115866A TWI261862B TW I261862 B TWI261862 B TW I261862B TW 094115866 A TW094115866 A TW 094115866A TW 94115866 A TW94115866 A TW 94115866A TW I261862 B TWI261862 B TW I261862B
Authority
TW
Taiwan
Prior art keywords
resin film
film
semiconductor module
insulating resin
semiconductor
Prior art date
Application number
TW094115866A
Other languages
English (en)
Other versions
TW200601405A (en
Inventor
Ryosuke Usui
Takeshi Nakamura
Atsuhiro Nishida
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200601405A publication Critical patent/TW200601405A/zh
Application granted granted Critical
Publication of TWI261862B publication Critical patent/TWI261862B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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1261862 ^ 九、發明說明： i【杳明所屬之技術領域】 本备明係有關包含電路元件之半導體模組以及半導體 裝置。 【先别技術】 心著行動電話、PDA :個人數位助理（pers〇nal心以― assistant)、DVC:數位攝影機（Digital vide〇。㈣⑽）、DSC · -數:相機（Dlgltal still camera)等可攜式電子機器之加速高 .性能化’為使市場能接受這類產品，產品之小型化、輕量 化成為必須，為實現前述目的，則需要高積體之系統LSI。 ^方面，對於這些電子機器，追求更易於使用的便利產 、口口 &而對於使用在這些機器之LSI，則追求高功能化，高 ••性此化。因此，伴隨LSI晶片之高積體化，其I/O數量增 力1 =同時，也強烈要求封裝本身之小型化。為使這兩者同 守貝見非#需要適合半導體元件之高密度基板安裝之半 籲導體封裝體之開發。為實現該要求，開發有各種稱為 CSP(Chlp Size Package :晶片尺寸封裝）之封裝技術。 、乍為這種封t例’ BGA(Ball Grid Array ··球柵陣列） 為小所周知。BGA係在封裝用基板上安裝半導體晶片，在 將其樹脂成型（m〇ldmg)後，在相反侧之面，作為外部端子 區域狀地形成焊錫球（s〇lder ball)者。，由於其安裝區 域係以面之形式達成，可較容易地實現封裝小型化。並且， 即使是電路基板側，也不需要作窄間距（pitch)之對應，且 不而要向精確度的安裝技術，因此若使用BGA，則即使在 317057 1261862 封裝成本略高之情況下，也可減少整體封裝成本。 第1圖係一般性BGA概略構成之示意圖。BGA1〇〇， 係具有在玻璃纖維加強環氧基板1〇6上，透過接著層ι〇8 搭載LSI晶片102之構造。LSI晶片1〇2,係藉由密封樹脂 IjO而成型。LSI晶片1〇2與玻璃纖維加強環氧基板ι〇6, 藉由金屬線104而電性連接。在玻璃纖維加強環氧基板 之背面，陣列狀配列有焊錫球112。經由該焊錫球ιΐ2，使 -BGA100安裝於印刷配線基板上。 -在該種封裝中，半導體晶片之密封，例如使用轉注塑 模（transfer m〇ld)、射出塑模（mjecti〇n m〇ld)、灌注（_㈣ 或浸潰（dipping)等（例如專利文獻^ .[專利文獻丨]日本特開平8-162486號公報 .[專利文獻2]日本特開2002-110717號公報 【發明内容】 [發明欲解決之課題] 〜但是，這些習知之CSP，對於可攜式電子機器等，難 於只現現在所希望水準之小型化、薄型化、輕量化。 本發明係基於上述課題而研發出者，本發明之目的， 在於提供-種使半導體㈣小魏、㈣ [解決課題之方法] 文丁 本發明之半導體模組，係包令 。又置於則述絕緣樹脂膜上之阻焊 層；前述多個電路元件，固著於前侧 曰、’料阻焊層，為含有卡魯特（card。)型聚合物（註1: 317057 6 I261862 *具有如fIu〇rene結構之環狀大體積骨幹之聚合物 :::固著方法，㈣較為理想，其中，尤以熱㈣為較：: 电路元件，包含半導體元件、被動元件。 依據j發明，藉由阻焊層包含有卡魯特“do)型 ，可提咼阻焊層之解像度以及吸濕特性等各種特性！ 且，可實現阻谭層之薄膜化。 口種〜ϋ。亚 本發明之半導體模組，亦 .件之-部分或全部之-個以上之構二==路元 同—平面2 絕緣m —面，係形成於 面纺個以上之構件中任意構件之下部之一 面平，元件間之絕緣膜下部之—面，係形二- * 所谓任意構件之上立β 之-面，形成於同-平面路元件間絕緣膜上部 元件間絕緣膜上邱之而μ構件上部之—面，與 所C 面，實質上形成於同-平坦面。 斤口月任思構件之下立Ρ — 面，形成於同-平面，：咅：，構：件間絕緣膜下部之- 間絕緣膜下部之 Μ構件下部之—面，與元件 太雜el .、·貫質上形成於同一平坦面。 受月之半導體模組之|y 電路元件之壯浐, 、^方法，係包含有··以固定 體，並將前、J、己置絕緣樹脂膜以及導電性膜之積声 透過*::電，，入於前述絕緣樹脂膜内之步称： 土考將刖述電路元件固 ^ ^ 驟、以及在較埋入有前^〜絕緣樹脂膜内之步 成阻焊層之 二 路7^件之絕緣樹脂膜的上層形 為，别述阻焊層，含有卡魯特型聚合物。 317057 7 1261862 仇伞赞明之構成 成而得者作為本發明之能’惟將任意組合這些構 變換為其他類型者，作^:屬有效。而將本發明之表現 【實施方式】 χ明之態樣，亦為有效。 第2圖（a)至第2圖（ 導體模组之製造步驟之剖=表不本發明之實施形態之半 體元件"L如: = 所示:在基材14°上固定多個半導 呈有接# 兀144等電路元件。在此，基板140 體元件142以及基板。而基板140可以是將半導 可Tr续抖 ?兀件I44埋入絕緣樹脂膜122後，而 可：：:Γ膜122剝離之材料所構成。且基材140，也 伸縮之材料。該種材料，可使用例如PET膜。 或被=3142,有例如電晶體、二極體、1C晶片等。 一 牛44 ,有例如晶片電容、晶片電阻等。 在作為基材140使用可伸縮材料 :將多個半導體元…及被動元件14:固2定= 接著上基材140往圖巾146所示之伸拉方向伸拉。 等附導^ 4〇處於伸拉狀態下，將附有銅箱之樹脂膜 122 版之絕緣樹脂膜(以下稱「第-絕緣樹脂膜 a」）配置於基材14〇上’經由真空沖壓，將半導體元件 ⑷以及被動元件144壓入第一絕緣樹脂膜⑵& ^。然 後如第2圖（b)所示，在148所示之應力緩和方向， k基材140伸張之力，從而使晶片間的間隙縮小。 317057 1261862 .— 這樣，半導體元件142以及被動元件〗44，被埋入第 / 一絕緣膜樹脂122a内，使半導體元件142以及被動元件 =4壓著於第一絕緣樹脂膜122a内而予以接著。本實施形 心中’使用可伸縮材料作為基材140時，由於在將固定有 •，導體兀件142以及被動元件144之基材140予以伸拉狀 ^下’將半導體元件142以及被動元件144壓入第一絕緣 十月曰胃膜122a内，因此在將半導體元件m2以及被動元件 ♦ 144壓入第一絕緣樹脂膜122a内時，元件間之間隔變大， 鲁·而使在元件間壓入第一絕緣樹脂膜122a變得容易。因此， 可改善半導體元件142以及被動元件144與第一絕緣樹脂 膜122a之密著性。 ， 導電性膜丨23例如有軋延銅箔等之軋延金屬，做為第 =絕緣樹脂膜122a者，可使用只要藉由加熱可以軟化之材 料，例如可以使用環氧樹脂、BT樹脂等之三聚氰胺衍生 物、液晶聚合物、PPE樹脂、聚醯亞胺樹脂、含含氟樹脂、 _酚樹脂、聚醯胺雙馬來酸酐縮亞胺（p〇lyamide bismaleimide) 等。藉由使用如此之材料，可以提高半導體模組之剛性， 可以提高半導體模組之安定性。做為第一絕緣樹脂膜122a 者，藉由使用環氧樹脂，或BT樹脂、ppE樹脂、聚醯亞 月女Μ知、含含氟樹脂、盼樹脂、聚酿胺雙馬來酸酐縮亞胺 等之熱硬化性樹脂，更可以提高半導體模組之剛性。 做為環氧樹脂者，可以列舉如雙I分Α型樹脂、雙g分ρ i知、丨月曰雙驗S型樹脂、g分搭清漆（phen〇i nov〇iac)樹脂、 曱酚醛清漆型環氧（cresol novolac type epoxy)樹脂、參酚 317057 9 1261862 甲t型環氧樹脂、脂環型環氧樹脂等。 一取做為三聚氰胺（即密胺）衍生物者，可以列舉如密胺、 :聚氰酸^胺脂、經甲基化錢、（異）三聚氰酸、密白胺、 山勒胺、被弄、琥王白醒鳥糞胺、硫酸密胺、硫酸乙酿鳥置 &、硫酸密白胺、硫酸脈基密胺、三聚氣胺樹脂、bt樹脂'、 ::亂酸、三聚異氰酸、三聚異氰酸衍生物、三聚異氰酸 錢脂、苯并鳥糞胺、乙㈣糞胺等三聚氰酸射 系化合物等。 胍 做為液晶者，可以列舉如芳香族系液晶 -〜 口 π tjW1又日日承g日、聚酿p 胺、聚酯醯、或含此耸之抖日^人^
4 3此寺之树脂組合物。其中，耐熱性、力I 工性及吸濕性互相平衡優異的液晶聚醋或含有液晶聚醋每 合物較佳。 做為液晶聚s旨者，可列舉如⑴芳香族二㈣與芳香游 二醇以及芳香族經基羧酸反應所得者，⑺異種之芳香族声 基羧酸之組合岐應所得者，（3)由芳㈣二羧酸與芳香^ 『：醇反應所得者，（4)在聚對笨二曱酸乙二醇醋等之聚❹ 芳香㈣基㈣岐應所得者等，料，取代此等之芳= 知-叛I、芳香族二醇以及芳香族絲叛酸，亦可使用 等：醋衍生物。再者此等之芳香族二羧酸、芳香族二醇以 及芳香族經基㈣，也可以使用在芳香族部分被幽原子、 烧基、芳基等所取代者。 液晶聚酷之重覆結構單位，可以列舉如芳香族二 之重覆結構單位（下述式⑴），芳香族二醇之重覆結構單位 (下述式（η))，芳香族羥基羧酸之重覆結構單位（下述式 317057 10 1261862 (m)) (但A1表示含有芳香 曰衣之2價結合基） (η) — 0-Α2—〇 — (i) 一 CO — A1 〇 一 A2 — 〇 (但A2表示含有芳夭 $方3 %之2價結合基） (m) - C0~A3—〇 — (但A3表示含有关夭 ^ 韦方香％之2價結合基） - 又，在弟一絕緣樹脂腺 4等充填材。做為埴充^/仏中，可以含有填充劑或縐 狀之叫或在第例如可以使用粒子狀或纖雄 ，古 在弟一絶緣樹脂膜122a中，萨由合古 填充劑或纖維，加埶第—έ 精由3有 元# β n 、、巴、，彖树脂膜122a，熱壓著半導體 兀件142及被動元件ι4 丁〒范 冷卻㈤例如將第一絕緣樹脂膜122: V 口丨i j至/皿（際，可以试+ 象，由此，可以提古丰^絕緣樹脂膜咖之反麵現 m ^ V體兀件M2及被動元件144以及 弟一絕緣樹脂膜122a之密 ^ 卞4以及 中含有纖維之場合，因可以脂膜咖 1動性，故可提古望^ 疋呵弟一絕緣樹脂膜122a之流 J如同弟—絕緣樹脂膜122a盥半 以及被動元件144之穷 /、丰蜍肢兀件142 '絕緣樹脂獏咖之：：：此硯點來看，做為構成第 不織布為宜，萨由此/ "^用方香族聚醯胺(aramide) 、 3由此可以使加工性良好。 做為香族聚醯胺纖維 或間芳香族聚醯胺纖維，做為針酿胺纖維 如可使用~ 一 方香族㈣胺纖維者’例 夭η (卜伸苯基對甲醯胺苯酸）(PPD — Τ)、做為門苦 香族聚醯胺者，办|上^ )做為間方 女者例如可以使用聚（m—伸苯基異甲酿胺苯 317057 11 1261862 酸）(MPD〜i)。 構成第一絕緣樹脂膜122a 有量，可依材料而作•定广中的填充材料之含 下。萨此，飞位4士 例如可設為50重量％以 二 保持第一絕緣樹脂膜咖與半導體元件142 以及被動元件144之良好接著性。兀件M2 作為具有導電性膜之絕崚樹 一絕绫;^ ^ 、、十月曰肤，可使用在膜狀的第 ，巴她曰勝心上附著導電性膜123者。 朕之絶緣樹脂膜，可透過在導電 ： 七镇一 Θ从从丨 坑1 W上查布、乾燥構 中，m:f Γ膜心之樹脂組成物而形成。本實施形態 、、且成物，在不違反本發明目的之範圍内，可含有 硬化劑、硬化促進劑以及其他成分 / 3有 ::版，二在第 '絕緣樹脂膜丨22a為B階段(b㈣化(係 二上一:人硬w硬化或假硬化狀態)狀態下，配置於基材 可提高第—絕緣樹脂膜122a與半導體元件142 :旨膜？122兀件广4之密著性。之後’對應構成第一絕緣樹 :、a之樹脂種類，加熱第一絕緣樹脂膜12以，在真 空下或減廢下，慶著具有導電性膜之絕緣樹脂膜與半導體 兀件142以及被動元件144。而在其他例中，將膜 一 絕緣樹脂膜在B階段（B siage)化狀態下，配置於基材】4〇 s二在Z、上配置$電性膜123，而將第一絕緣樹脂膜〗22a 熱1著於半導體元件142以及被動元件i44時，即使藉由 將導電性膜】23熱壓著於第一絕緣樹脂膜U2a，也可^成 具有導電性膜之絕緣樹脂膜。 3]7057 12 1261862 並且，對導電性膜〗9 2 、’透過雷射直描法（trepanning -ai】rent)或濕銅則，進行形成配線之配線圖案化步驟 如第2圖⑷所示，組合二氧化碳氣體雷射、YAG雷 射、乾式餘刻，進行在篦—έ ^ 7 在弟絶緣樹脂膜122a形成通孔（via ，即throughhole)之通孔形成步驟。 f著★第2圖⑷所不’透過對應高孔深/孔徑（aspect) 匕之_銅鑛覆電解銅錢覆形成導電性膜 :導電性材料埋入通孔内，以進行形成通孔12吻 二接!，藉由對導電性膜12()進行半加成（semi_addi— 半；，從而形成高密度配線，並進行在多個 …及被動元件144間軸 的第接圖⑷所示，再進行形成具有導電性膜123 巴緣树月曰膜咖之第二絕緣樹脂膜形成步驟。 脂膜utt絕緣樹脂膜122b之材料，可從在第—絕緣樹 ^ 說明的’例如環氧樹脂、BT樹脂等之密 樹：生物：t晶聚合物、PPE樹脂、聚酸亞胺樹脂、含！ 货曰、酚樹脂、以及聚醯胺雙馬來 並利用。 又’木酉夂軒&亞胺中適當選擇 如亦第二絕緣樹脂膜122b上部之導電性膜⑵，例 亦可疋軋延銅箔等之軋延金屬。 在此，第一絕緣樹脂膜122a，例如可 蝴膽軟化之材料來構：藉 〜狗由於弟-絕緣樹脂膜122a比第二絕緣樹脂膜 317057 1261862 mb更易於變形， ⑷，順㈣導體元# 142以及被動元件 絕緣樹脂膜1221}之=脂膜122&内之同時，保持第二 統稱[第-絕緣樹脂 [絕緣_脂叫)之整體之^[弟一、·、巴、、軸旨膜心]為 在其他例中===換溫度為較低之材料來構成。而 122b^^f "l1'2" 144之宓著性ρ 、半導體兀件142、被動元件 得^材料構成。即使以上述方式，也可# 侍如則所述之同樣效果。 、也U又 中，邑/緣樹脂膜咖以及第二絕緣樹脂膜⑽ 維等填充材料。此時，第—絕緣樹 ^12 3之填充物的含有量，可以由比第二絕緣樹脂膜 之毛、充材的含有量更少者構成。而亦可只在 ·::膜咖中含有充填材，在第-絕緣樹脂膜122:中不 二 真充材之構成。如此作法’則可提高第-絕緣樹脂膜 咖之柔軟性，使半導體元件142以及被動元件144之埋 入更易於進行之同時，藉由第二絕緣樹脂膜12孔，可 絕緣樹脂膜122之翹曲。 夕 如上所述，透過以對應各個目的之理想材料構成第— 絕緣樹脂膜122a以及第二絕緣樹脂膜122b，可良好地進 行向絕緣樹脂膜Π2之半導體元件142以及被動元件144 之埋入，同時可提高半導體模組之剛性以及成型性。 317057 f ^61862 路壯:圖⑴至第3圖（k) ’係表示本發明之實施形態之電 .衣置之製造步驟的後半部剖面圖。 首先，如第 3 ISUf、π - , 以 S⑴所不，對於第二絕緣樹脂膜122b 上部之導電性膜123，也與前述相同，反復配線圖 、隹^ ^通孔形成步驟、鍍覆步驟、以及配線形成步驟， 、行2層配線之形成步驟。 如後面所述，右繁—π .16〇 , . ^ 在弟—、、、巴、、彖祕脂膜122b上疊層之積層膜 鲁在〜，^已設置有配線⑵與導電性膜124時，不必 擊在弟一絕緣樹脂膜1 9 9 h主工 〇 胰122b表面，另外形成配線。 接著，如第3圖（2)所千，户μ 、隹—所不在弟二絕緣樹脂122b上部， 進仃知層構成凹部丨9〇的 -驟。奸居K 積層勝160之形成功能層第一步 -Ή 4槓層胺丨60，由於且供重A、上 ^ ^ ' 事先以雷射加工或沖壓力U工 、-寺所挖出之凹部吱穿補夕11如 ^ 貝I邛，因此當透過壓著等接著 部！9〇，具有底 曰 則構成凹部190。該凹 咖 一，也可只疋在積層膜160上方且有開口 逢狀之凹部，或是由在積層 ’、 嘗補邱溆穿_ π 兩面所開口之隧道狀 貝舁弟二、％緣樹脂膜122b ⑽，也可使用直m切厂面所構成之凹部。積層膜 ，、工貼者法或減壓貼著 也可在絕緣樹脂膜122上疊 貝每 案化、敍刻等，以形成凹部190層^60後，實施圖 該積層膜16〇,也可以是絕緣樹 所使用之絕緣樹脂膜，可從前述絕 f為和層版⑽ 說明的，例如環氧樹脂、BT樹脂等之蜜二馭122中所作之 合物、PPE樹脂、聚酿亞胺樹脂^女订生物、液晶聚 3亂树脂、酚樹脂、以 317057 15 1261862 .胺雙馬來酸酐縮亞胺中適當選擇並湘。透過使用 .二種材料，可使後述之配線125與導電性膜⑽ ==達到較好絕緣。而該種材料，也較容易藉 刀工或真空貼付法進行積層。 而積層膜160,亦可事先設置有配線125與導電性膜 4。作為這些配線125與導電性膣〗以 、 銅箔等之軋延金屬而使用。、 > 如可加工軋延 • h接著，如第3圖⑻所示，進行形成功能層第二牛驟 •邊步驟由下述步驟構成 /私， 16n ^ y 將知狀埋入材料埋入該積声膜 160之形成的凹部190内部之步驟 “貝層： 施乾燥等處理，以形成構成電阻 ^ I人材料貫 之高介電率構件⑺等之電路元件的電容175 •構件的步驟。 邛刀或王邛之埋入 在此，構成该電路元件之一部八 可成為構成被動元件等之構件。二:或古王/之埋入構件， ，是構成電阻18。或後述之電容175等二埋入構件’可以 全部之構件。該埋入構件為構成干、几件之一部分或 之構件時，作為該埋入構件之:：：180之-部分或全部 有高電阻的材料，則並沒有特別限定埋= 才料’只要是具 包含以(鎳鉻合金）為首 ^如，可使用碳與 又該埋入構件為構成後述之電==料等。 170時，該埋入構件之材料， 之向介電率構件 則並沒有特別限定，例如可使：:有高介電率之材料’ surface)之活性碳等碳系材料 二有大比面積（Specif]c G 3五氧化叙等 3Ϊ7057 16 1261862 严〜而電容之下部電極或上部電極，可由且有H八 屬形成。例如可佶爾山力 -、百V电性之金 這些埋入材料，可X!等構成之薄膜電極等。 之膠狀㈣，亦可是末㈣體物懸浮於溶媒中 埋入凹部19〇H 到板㈣職㈣等刮取裝置200 埋入。〇 可將該埋人材料利用網印⑽叫法 在此，所謂網印法，係孔版㈣法之 用人造絲叫特多龍、尼龍等化學纖維、;、= 缄維寺之網之印刷法。作為實施網印法 、， :張在框上’四角拉緊固定，在其上面以機械式或Li 式之片）方法’製作版膜（阻劑），堵塞必要晝線以外之網 眼’從而製作版。接著’在框内放入埋入材料，由被稱為 _到板之刮刀狀之橡膠板等構成之刮取裝置2〇〇，加塵、移 動網之内面。如此一來埋入材料穿透沒有版膜之部分的 、罔被壓出至置於版下之被印刷物面之積層膜！ 6〇之凹部 19〇内部’形成埋入凹部内部直至無縫隙狀態。並且，凹 邛190外所殘留之該埋入材料，可利用刮板等刮取裝置2〇〇 除去。 接著，如弟3圖⑴所示，在積層膜以及電路裝置之構 成構件之更上部’形成上層絕緣樹脂膜21 〇後，壓著形成 光阻焊層（photo solder resist layer)220。作為壓著條件，例 如，使用溫度110°C、時間1至2分鐘，2個大氣壓等。之 後，經由後硬化（after bake)步驟，使光阻焊層220部分硬 化。 在光阻焊層220上，如後所述，使用含有卡魯特（card〇) 317057 17 1261862 型聚合物之樹脂膜。 接著，如第3圖⑴所示，在將玻璃作為遮罩進行曝光 而形成圖案化後，將光阻焊層220作為遮罩，例如，以藥 液進：化予蝕刻加工，形成通孔，反復鍍覆步驟、配線形 成步驟二進行3層配線形成步驟。然後，在最上層上部所 形^之導電性膜126上，進行利用焊錫印刷法等，形成作 為月面电極之焊錫電極（焊錫球）23q之焊錫電極形成步驟。 以下’對本實施形態中，光阻焊層22〇中使用含有 魯特型聚合物樹脂膜之效果進行說明。 斤在此_所明卡魯特型聚合物（cardo type p〇lymer)，如 第（1)式所不，係指具有環狀基直接鍵結於聚合物主鏈之構 造之聚合物總稱。又於繁「 + 才舟又於弟⑴式中，R1、R2表示含有伸烴 基、方香％之2價的基等之2價基。 [化1]
球卞魯特型聚合物 的取代基，相脖Μ，四級碳素之太 仏 于於主％為具有幾乎直角存在構造之聚 物。 含不鮮鍵結，在 :产壯：4有乳原子、氧原子、硫原子、磷原子等原子 而满，可以是多環，也可以是縮合環。而環狀部， 317057 18 1261862 -以疋鍵結其他碳鏈，或者亦可是交俨 ，五員型的如第⑴“示，譬如可列舉：在 等严^美並具有縮合環之_基（仙价_ 鍵結之結構。 貞mu卜個碳原子與主鏈 所谓芴基，如第（II)式所示氣 化的基，在卡魯特型聚合二二=子::職 鼠[1 之原子位置，與主鏈之垸基之碳原子鍵結。、工脫風
(式II) 卡魯特型聚合物，由於具有前述構造 有以下效果： 口切U此男 (1)約束聚合物主鏈之旋轉 • (2)主鏈及側鏈之限制構型（c〇nf〇rmati⑽） (3) 阻祕为子間之$積（packing) (4) 由於側鏈導人芳香族取代基等導致之芳㈣性之增加 古耐=卡/Μ聚合物’其特徵為具有高機械性強度、 同耐熱性、溶劑溶解性、高透明性、古 率、以及更高氣體穿透性。 〃、。氐禝折射 在此’光阻焊層2 2 0所传用夕人士上 ㈣r “ 使用之3有卡魯特型聚合物之 二二 定之添力，，在抑制產生空洞(v°ld)或凹 寺之狀悲下’可形成薄臈。因此，可在光阻焊層220上， 317057 19 1261862 .1吏；;5::左右厚度之膜，這與光阻焊層狗常所使用 .之7子度為50“ 右之樹脂材料作比較，則只有約1/2之 厚度。因此，藉由在光阻焊層220上使用含有卡魯特 合物=樹脂膜，可小型化本實施形態之半導體模組。土 、含有卡魯特型聚合物之樹脂膜具有如後所述 =性與密著性。因此，在光阻焊層22()，藉由使用含有 魯特型聚合物之樹脂膜，可提高與半導體模組表面所搭 -载之元件及其他層之密著性。 含有卡魯特型聚合物之樹脂膜，如後所述， = 。而本實施形態所使用之膜的厚度，係光阻：層 通爷所使用厚度之約1/2，因此使用含有卡魯特 ^樹脂膜之光阻焊層細，具有更好的解像度。因此:可 ^尚形成通孔時之尺寸精度。故可提高半導體模組之信賴 含有卡魯特型聚合物之樹脂膜，如後所述，且 •I:二電=。？此，在光阻焊層22°，藉由使用；有：魯 I水口物之祕脂膜’可減少光阻焊層22()内所埋設之配 A間寄生電容。因此，可提高半導體模組之可靠性。 由於3有卡甘特型聚合物之樹脂膜具有高機械性强 度，故即使光阻焊層22〇之厚度為以往之約Μ厚度 :保持機械性強度。因此，可抑制半導體模組基板全體之 翹曲。故，可掉古、丄…首純 低王月且疋 T棱同+導體模組上所搭載之元件之接人 (bonding)精度。 於光阻焊層的形成通常所使用之旋塗法中，在光阻焊 317057 20 1261862 層之外周部易產生空洞（V0ld)，該點上具有改善之餘地。 而在灌注（pottmg)法，其接著前之狀態係液體，存在有汾 布後容易產生空洞（vend)之問題的改善餘地。相對於此土 本實施形態之光阻焊層220,在壓著膜時，因抑制空洞、 凹凸等之發生，故在壓著有膜之半導體模組之光阻焊層 :2〇 ί ’其空洞、凹凸也較少。因此，可提高半導體模組 之可罪性以及製造穩定性。 前述卡魯特型聚合物，可以是在同一分子鍵内具有尹 酸基與丙稀酸醋基之聚合物交聯所得之聚合物。作為習知 之一般性感光性清漆，係使用具有顯影性之叛酸基实 與多官能丙稀基之混合物，但在解像度方面有更加二改呈 之餘地。代替一般性之感光清漆，如使用在同-分子鏈内 具有叛酸基與丙稀酸醋基之聚合物交聯所得之卡魚特型〒 =物，則具有顯影性之叛酸與交聯基之丙烯酸心在同： =子=中，由於主鏈中具有大型的取代基不易游離基擴 C 提高含有卡魯特型聚合物之樹脂膜的解像度 H愛點。 含有卡魯特型聚合物之樹脂臈，以滿足以下所示之夂 r:::r 分之值’經由添加填充物等’可進行適當調 =，，前述含有卡魯特型聚合物之樹脂膜之玻璃轉換 上又二絲可：' 例如i8〇c以上，特別是較理想為i9〇t以 上。玻_換溫度如在該範圍，則提高含有卡魯特型聚合 317057 21 1261862 物之樹脂膜之耐熱性 a述合有卡魯特型聚合物之樹脂膜之玻璃轉換溫度 (Tg)，可在例如22(rc以下，特別是較理想為2i(rc以下。 如果是玻璃轉換溫度在該範圍之含有卡魯特型聚合物之樹 脂膜，則可透过通常之製法，進行穩定製造。而玻璃轉換 溫度，例如透過進行塊狀（bulk)試料之動態機械測試 (Dynaimc Mechamcal Analysis : DMA)，可進行測試。 • 刖述含有卡魯特型聚合物之樹脂膜之Tg以下之區域 鲁之線膨服係數（coefficient 〇fthermal expansi〇n: cte) ,可 在例如80Ppm/t：以下，特別是理想為75ppm/t：以下。線 膨脹係數如果在該範圍，則提高含有卡魯特型聚合物之樹 ~ _脂，與其他構件等之密著性。 前述含有卡魯特型聚合物之樹脂膜之Tg以下之區域 之線膨脹係數（CTE)，可在例如5〇ppm/t以上，特別是理 想為55ppm/ta上。透過在前述含有卡魯特型聚合物之掏 丨脂膜調配填充物，也可獲得CTE纟2QppmrCm之樹脂 組成物。如果線膨脹係數係在該範圍之含有卡f、特型聚合 物之樹脂膜’則可以利用通常之製法，進行穩定製造。而 熱膨服係數，可透過以例如熱機械分析裝置（Th_( Mechamcal Analysis : TMA)之熱膨脹測試進行測試。 丽述含有卡魯特型聚合物之樹脂膜之熱傳導率，可以 在例如0.50WW.sec以下，特别是理想為〇3顺, sec以下。如熱傳導率在該範圍，則提高含有卡魯特型聚 合物之樹脂膜之耐熱性。 317057 22 1261862 — d述含有卡魯特型聚合物之樹脂膜之熱傳導率，可以 -在例如〇.l〇W/cm2 · sec以上，特别是理想為〇 25W/cm2 · sec以上熱傳導率若在邊乾圍之含有卡魯特型聚合物之 樹脂膜，則利用通常之製法，可進行穩定製造。熱傳導率， 可透過例如圓板熱流計法（ASTM E1530)進行測試。 别述含有卡魯特型聚合物之樹脂膜之1〇至1〇〇“ m直 I之通孔的通孔孔深/孔徑比（aspect rati〇)，可以在例如 ，以上，特别是理想在丨以上。如果通孔孔深/孔徑比在該範 •圍，則提高含有卡魯特型聚合物之樹脂膜之解像度。 前述含有卡魯特型聚合物之樹脂膜之1〇至丨㈧“㈤直 徑：通孔的通孔孔深/孔徑比，可以在例如5以下，特别是 -理釔在2以下。如果通孔孔深/孔徑比在該範圍之含有卡魯 型聚合物之樹脂膜’則可透过通常之製法，進行穩定的 製造。 月J述3有卡魯特型聚合物之樹脂膜之施加有頻率 々MHz的交流電場時之介電率，可以是例如4以下，特」 以了。如果介電率在該範圍，則提高含有卡‘ 二口物之树脂膜之以高頻特性為首之介電特性。 前述含有卡‘I、特型聚合物之樹脂膜之 ==?之介電率，可以是例…上二: 型聚合物之樹㈣，之含有诗 前述含有卡㈣刑^進行穩定製造 WHz的交流電場時土：物之樹脂膜之施加有頻率
守之；丨質損耗角正切（dlelectric lQ 317057 23 1261862 〜tangent) ’可以是例如〇 如介質損耗角正士 a · 下，4寸别是理想在0.029以下。 ^角正切在該範圍，則提高含有卡 之樹脂膜之以高頻特性為首之介電特性。θ 來"物 月Ά 3有卡魯特型聚合物之樹脂膜之 1MHz的交流電場時、。有^員率為 以上，特别是理想在0.027=角正切，可以是例如〇侧 在該範圍之含有卡魯特型聚合物之:::介:損耗角正切 .之製法，進行穩定的製造。⑽…則可利用通常 前述含有卡魯特型聚合物之樹脂膜 型聚合物之之 有卡魯特 前述含有卡魯特型聚合物之樹脂膜 °-5wt%"" 之樹脂膜、，=::=圍魯特型聚合物 一 衣次進仃穩定的製造。 2卡魯特型聚合物之樹脂膜滿足這些前述 二ΤΓΓ佳地實現使用含有卡魯特型聚合物樹脂膜的 ，層220所被要求之薄膜化、機械性强度、耐敎性、 ^他構件之密著性、解像度、介電特性、耐濕性等各項 本實施形態之半導體模組，預先在樹脂層埋入半導體 :二;以及被動元件144，使與具導電性膜之絕緣樹脂 果的接者面平坦之後，並貼附具導電性膜之絕緣樹脂膜。 317057 5 1261862 並且’在積層膜1 60中將埋 即 材相入凹部190的話，則 在上層#巴緣樹脂腺2】。| 致之 、 胰210之表面，也由於没有各元件導 物+為表面平坦’故透过與使用含有卡魯特型聚合 之光阻焊層220之相乘效果，可實麻 膜12^如弟3圖⑴所示，進行將基材140從絕緣樹脂 用機^離之基材剝離步驟。該基材剝離步驟，雖也可使 ·::戒式方法來進行，但於基物為w光反應性膜時， 邦=由照射uv使在基材_内產生交聯反應，以降低 黏者力，而除去基材140。 -八I 即可獲彳于將半導體元件M2以及被動元件144 邊的面由絕緣樹脂膜122密封，同時使另一邊的 '面蕗出之構造體。 (適用於ISB封裝） 本實施形態之半導體模組之製造方法，可適用於 (Integrated System &註冊商標）封裝之製造。透 =適用4方法’可使ISB封裝之製造步驟簡略化。以下， 就ISB封裝進行說明。 、壯斤明ISB，係在以半導體裸晶片為中心之電子電路之 :=中具有以銅形成之配線圖案之同日夺，不使用用以支 棕電路元件之基材（core)之獨自的無基材系統封裝 (oreless system m package)。日本特開 2〇〇2_11〇717 號公 報中’記載了這種系統封裝（System in package)。 在此，習知之ISB封裝，係在也具有支撐基板功能之 317057 25 ^61862 安敦電路-:成\數層導電圖案，製成多層配線構造，再 封裂體。 以絕緣樹月旨成型，並除去導電羯而取得該 (1) 读封裝，具有以下優點： (11)
由於可用無基材安裳，因此可實現電 之小型、薄型化。 LSI 2於可將電晶體到系統LSI、以及晶片型電容與電阻 (iii) /成在電路並進行封裝，因此可實現高度SIP(system m package)。 組合現有之半導體晶片，因此可短期開發系 (vi) (v) 半V版裸晶片直接載置（m〇u叫於其正下方之銅 上’可取得良好散熱性。 由於電路配線是銅材之而沒有基材，因此成為低介
电率之电路配線’在高速資料傳送與高頻電 良好特性。 I (vi) 電極係埋入封裝辦M j 致 支了衣版内部之構造，因此可抑制電極 料之顆粒污染的發生。 ⑽封裝尺寸自由，平均们個之廢材料與60引腳㈣ 之SQFP封裝體相比，為大約1/1〇的量，因此可減 少環境負擔。 (v叫從裝載，件之印刷電路基板，到具有功能之電路基 板，可實現新概念的系統構成。 ⑻ISB之圖案設計，係與印刷電路基板之圖案設計一樣 317057 26 1261862 地方便，電子成品廠商（set 計。 maker)之工程師可自行設 本實施形態之半導體模組制、生古土 如t 步夕制、生+ 稞、、且衣造方法，在適用於ISB封 ^ 由於構成電路元件之—部分或全部之埋入構 面平坦’且於積層膜上部之—面與埋人構件之上部 二為形成平坦面的方式構成，因此更上部所層積之膜 :亦平坦。而且，藉由在形成上層絕緣層時，導入含有 :魯特型聚合物之光阻焊層22q，提高加卫精度，因此可 善ISB封裝之製造成本或製造穩定性，或實現高速信號 得送。 …«本實施形態，由於可使封裝電路元件之絕緣樹脂 -膜本身發揮作為支持基板之功能，因此可省去在形成多層 '配線構造後，除去基板之步驟。藉此，在可簡略化㈣^ 裝之製造步驟之同時，也可取得前述優點。 因此，根據本實施形態，可實現活用了晶圓步驟、Ι§Β 籲技術以及裝置之多晶片（multi chip)Sip。並且，可實現無凸 塊構造、高速信號傳送、薄型封裝。此外，藉由在上層絕 緣層之形成，導入含有卡魯特型聚合物之光阻焊層220, 而從外層進行高密度配線，可實現對應小型化、多引腳化 之封裝體。而電路裝置内，可内藏被動元件，提供薄型高 功能之SiP。 以上，根據實施形態以及實施例說明了本發明。本實 施形態以及實施例僅是示例，可有各種變形例，並且該種 變形例也在本發明之範圍内，應為本業業者所理解。 317057 27 1261862 例如 在配踝層干，層間的電性連接，並不限^ 通孔（thr0ugh hole)中埋入導電性材料之方法 々疋； ^過導線而進行連接。這種情况，可_封材料覆= :外：可對配線125、導電性膜124、 Μ以及電阻刚透過CVD法、濺射法等進行構 糟由圖案成形，姓刻等形成後，對積層膜16〇進行=膜亚 兄，含有卡魯特型聚合物之光阻焊層22成 可在積層膜16〇之成膜後進行 之开/成， 如前所述。 《後到形成配線之步驟， 電路元件’如第2圖⑷至第 至第3圖（k)所示，可以是包含在第一元件上配置第圖（〇 之電路元件之構成。作為在第—元件上租人第置弟:元件 這種情況，可在第1i a_M'SRAM與叹⑽。 取得。^弟一兀件上透過通孔電性連接第二元件而 積層膜16〇之材粗 成為電阻材料之 料。這種情況，積層膜16〇之凹;件之馬介電率材 可以是絕緣性樹脂材料。 里入之埋入材料， 亚且，作為形成構成 -部分或全部的埋入構件所二；^ 法，並不限於乾# , I里入材料之處理方 件之特性而使二 几成 K者、壓縮、固化、凝固、 317057 28 1261862 成型、交聯、硬化、變性等各種處理。 【圖式簡單說明】 第1圖係一般性BGA之概略構成示意圖 第2圖（a)係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 第2圖（b)係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 . 第2圖（c)係表示本發明之實施形態之半導體模組製造 鲁步驟之剖面圖。 第2圖（d)係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 • 第2圖（e)係表示本發明之實施形態之半導體模組製造 - 步驟之剖面圖。 第3圖（f)係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 第3圖（g)係表示本發明之實施形態之半導體模組製造 •步驟之剖面圖。 第3圖（h)係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 第3圖⑴係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 第3圖⑴係表示本發明之實施形態之半導體模組製造 步驟之剖面圖。 第3圖（k)係表示本發明之實施形態之半導體模組製造 29 317057 1261862 步驟 之剖面圖。 【主 要元件符號說明< 100 BGA 104 金屬線 108 接著層 112 焊錫球 120、 123 、 124 、 126 121 通孔 • 122a 第一絕緣樹脂膜 125 配線 142 半導體元件 146 表示伸拉方向 - 170 高介電率元件 190 凹部 210 上層絕緣樹脂膜 230 焊錫電極 lsi晶片 破璃纖维加強環氧基板 禮、封樹脂 絕緣樹脂膜 第一絕緣樹脂膜 基材 被動元件 積層膜 電阻器 刮取裝置 光阻焊層 317057 30

Claims (1)

  1. "1261862 第94115866號專利申請案 ， 申請專利範圍修正本 ! (95年3月9曰 •一種半導體模組，係包括有： 絕緣樹脂膜、 里入於别述絕緣樹脂膜之多個電路元件、以及 。又置於别述絕緣樹脂膜的上層之阻焊層； :述多個電路元件係固著於前述絕緣樹脂膜； 月’J述阻焊層包含卡魯特型聚合物。 申請專利範圍第丨項之半導體模組，係以下述方式携 :成前述電路元件之一部分或全部之一個以上之 的任意—構件之上部的—面，與前述電路元件間 、、、巴緣膜上部之一面，係形成同一平面； 前述一個以上之構件中的任意一構件之下部的— 一平：前述電路元件間之絕緣膜下部之一面，係 f面。 3’如申請士利範圍第1項之半導體模組，其中， 4. 如申2 =焊層設置有連接前述電路元件之配線。 申明f利乾圍第2項之半導體模組，其中， 5. 如申ί =阻焊層設置有連接前述電路元件之配線。 申二專利範圍第i項之半導體模組，其中， 下；珂述阻焊層之玻璃轉移溫度為18吖以上，靴以 (修正本）317057 1261862 甽逖阻焊層之施， ▼ 6 笔損耗角正切為0 001以上，〇 04以下 如申請專利範圍第5項之半導體模組，其中， 丽述阻焊層之玻璃轉移溫度以下之區域的線膨脹 係數為50ppm/t：以上，8〇ppm/^c以下。 如申請專利範圍第5項之半導體模組，其中， 前述阻焊層之熱傳導率為O.lOW/cm2 · sec以上， 〇.5〇W/cm2 · see 以下。 如申請專利範圍第5項之半導體模組，其中， 珂述阻焊層所設置之配線中，所包含之具有10 9 m之直徑之通孔的孔深/孔徑比（aspect ratio)， 為〇·5以上，5以下。 如申請專利範圍第5項之半導體模組，其中， 對前述阻焊層施加有頻率_ζ之交流電場時的介 包率為0.1以上，4·〇以下。 10·如申=專利範圍第5項之半導體模組，其中， 3則述阻*干層之24小時吸水率為〇.5wt%以上， 3.〇wt%以下。 u.—種半導體模組之製造方法，係包括： 導電2定了電路元件之狀態下，配置絕緣樹脂膜以及 體’並將前述電路元件埋入於前述絕緣 内之述電路元件固定於前述絕緣樹脂膜 (修正本）317057 丄261862 在較埋入右& 成阻焊層之牛取則处电路7l件之絕緣樹脂膜的上層形 曰 v驟； 月1J述阻焊I & I 12,如申請專利 …-合物。 復包括： 項之半導體模組製造方法，其中 表面具備凹部之膜之步驟、以及 形成構成前述2m 料’而在前述凹部内部 步驟。 牛 部分或全部的埋入構件之 13 ·如申請專利筋圖 中， 工、之半導體模組之製造方法，其 id u⑺述、巴緣樹脂膜係在材料中包含有埶硬化性m匕 14·如申請專利範圍第 化性树月曰。 中， 員之+導體模組之製造方法，其 前述絕緣樹脂膜在材料中包含乾延金屬。 •種Λ導f裝置，係包括··半導體模組及半導體元件， 違半導體模組為如中請專利第〗項之 且而該半導體元件係搭载於前述半導體模組。、 (修正本）3】7057 3
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677955B (zh) * 2015-01-28 2019-11-21 日商三美電機股份有限公司 模組及其製造方法

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7372126B2 (en) * 2005-03-31 2008-05-13 Intel Corporation Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same
US7288459B2 (en) * 2005-03-31 2007-10-30 Intel Corporation Organic substrates with integral thin-film capacitors, methods of making same, and systems containing same
US20070152311A1 (en) * 2005-12-30 2007-07-05 Saikumar Jayaraman Chip-packaging compositions including bis-maleimides, packages made therewith, and methods of assembling same
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
JP5409996B2 (ja) * 2006-12-25 2014-02-05 ピーエスフォー ルクスコ エスエイアールエル 多層プリント配線板
CN100501952C (zh) * 2007-05-09 2009-06-17 日月光半导体制造股份有限公司 具有埋入被动元件的晶粒承载用封装基板及其制造方法
US8003496B2 (en) 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
FR2963478B1 (fr) * 2010-07-27 2013-06-28 St Microelectronics Grenoble 2 Dispositif semi-conducteur comprenant un composant passif de condensateurs et procede pour sa fabrication.
CN102169840A (zh) * 2011-01-30 2011-08-31 南通富士通微电子股份有限公司 系统级扇出晶圆封装方法
WO2012100720A1 (zh) * 2011-01-30 2012-08-02 南通富士通微电子股份有限公司 封装方法
CN102157400B (zh) * 2011-01-30 2013-06-19 南通富士通微电子股份有限公司 高集成度晶圆扇出封装方法
CN102163603B (zh) * 2011-01-30 2013-11-06 南通富士通微电子股份有限公司 系统级扇出晶圆封装结构
WO2012100721A1 (zh) * 2011-01-30 2012-08-02 南通富士通微电子股份有限公司 封装结构
CN102176452B (zh) * 2011-01-30 2013-06-19 南通富士通微电子股份有限公司 高密度系统级芯片封装结构
CN102169879B (zh) * 2011-01-30 2013-10-02 南通富士通微电子股份有限公司 高集成度晶圆扇出封装结构
WO2012126377A1 (en) 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
US9595490B2 (en) 2011-03-22 2017-03-14 Nantong Fujitsu Microelectronics Co., Ltd. 3D system-level packaging methods and structures
WO2012126379A1 (en) 2011-03-23 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. Three-dimensional system-level packaging methods and structures
CN102157456B (zh) * 2011-03-23 2014-05-28 南通富士通微电子股份有限公司 三维系统级封装方法
CN103972218B (zh) * 2014-04-26 2016-08-24 华进半导体封装先导技术研发中心有限公司 集成无源器件扇出型晶圆级封装结构及制作方法
US20160218092A1 (en) * 2015-01-27 2016-07-28 Mediatek Inc. Chip package with embedded passive device
CN110473824A (zh) * 2019-09-05 2019-11-19 苏州芯慧联半导体科技有限公司 一种半导体用可再生静电卡盘及其制造方法
CN113853056B (zh) * 2021-08-25 2023-07-07 华为技术有限公司 封装模组、板对板连接结构及其制备方法和终端
CN114664771A (zh) * 2022-02-14 2022-06-24 致瞻科技(上海)有限公司 新型半导体电容封装结构及其封装方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814373A (en) * 1991-11-26 1998-09-29 Dow Chemical Company Heat-resistant hydroxy-functional polyethers as thermoplastic barrier resins
JPH08162486A (ja) 1994-12-05 1996-06-21 Shin Etsu Chem Co Ltd 半導体素子の樹脂封止方法
US6323435B1 (en) * 1998-07-31 2001-11-27 Kulicke & Soffa Holdings, Inc. Low-impedance high-density deposited-on-laminate structures having reduced stress
JP2000131242A (ja) * 1998-10-23 2000-05-12 Hitachi Ltd 不良解析装置
JP2000171973A (ja) * 1998-12-08 2000-06-23 Ngk Spark Plug Co Ltd 感光性樹脂組成物及びソルダーレジスト用感光性樹脂組成物
JP2000323645A (ja) 1999-05-11 2000-11-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2001168126A (ja) * 1999-12-06 2001-06-22 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2001254002A (ja) 2000-03-10 2001-09-18 Nippon Kayaku Co Ltd 樹脂組成物、そのフィルム及びその硬化物
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3442049B2 (ja) 2000-03-29 2003-09-02 住友ベークライト株式会社 耐熱性樹脂前駆体、耐熱性樹脂及び絶縁膜並びに半導体装置
JP5016768B2 (ja) * 2000-03-29 2012-09-05 学校法人神奈川大学 活性エネルギー線硬化性樹脂、その製造方法及び光硬化性・熱硬化性樹脂組成物
US6607937B1 (en) * 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
JP2002110717A (ja) 2000-10-02 2002-04-12 Sanyo Electric Co Ltd 回路装置の製造方法
JP4819304B2 (ja) 2000-10-18 2011-11-24 日本電気株式会社 半導体パッケージ
JP3959261B2 (ja) 2000-12-26 2007-08-15 日本特殊陶業株式会社 配線基板
JP4137389B2 (ja) 2001-02-16 2008-08-20 イビデン株式会社 半導体素子を内蔵する多層プリント配線板の製造方法
JP3888302B2 (ja) * 2002-12-24 2007-02-28 カシオ計算機株式会社 半導体装置
JP4303563B2 (ja) * 2003-11-12 2009-07-29 大日本印刷株式会社 電子装置および電子装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677955B (zh) * 2015-01-28 2019-11-21 日商三美電機股份有限公司 模組及其製造方法

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