TWI254508B - Thin gate oxide output driver - Google Patents

Abstract

An output driver circuit including first and second cascoded scaled P-channel devices coupled to first and second cascoded scaled N-channel devices. The P-channel devices are coupled together at a first node and between an output and a first source voltage having an elevated voltage level. The N-channel devices are coupled between the output and a reference source voltage. The first scaled P-channel device has a gate that receives a pull-up signal and the second scaled P-channel device has a gate coupled to a static voltage. The second P-channel device and the static voltage are configured to protect the first P-channel device from gate oxide breakdown when the first device is turned off. The first N-channel device has a gate receiving a voltage-limited pull-down signal and the second N-channel device has a gate receiving a lower voltage pull-down signal. The cascoded N-channel devices divide load and prevent hot carrier injection effects.

Description

1254508 V. INSTRUCTIONS INSTRUCTIONS (1) RELATED TO RELATED APPLICATIONS [0001] This application claims priority to the following U.S. Application Serial No. 10/317,240, filed on Dec. 11, 2002. [0 0 0 2 ] This application is related to the following U.S. patents in the same application, having the same filing date, applicant and inventor. Taiwan Application 曰DOCKETNUMBER Application No. 92 1 1 75 1 7 92/ 6/27 CNTR: 20 0 7 Digital potential converter capable of protecting the gate oxide layer of the reduced drive element [Technical Field of the Invention] [0 0 0 3 The present invention relates to a reduced driving element for coupling to an external cymbal operating at a high potential, and more particularly to a thin oxide output driver comprising a reduced p-channel element whose oxide layer is not easily collapsed at a high potential, and which is less prone to Hot carrier injection effect (reduced N-channel component of hot carrier injectiQn. [Prior Art] [0 0 0 4] With the development of integrated circuit design and process technology over the years, the operating voltage has been adjusted downward with component size. Trend. Super large product

Page 7 1254508 V. Description of invention (2)

UcalinoO h — 2 is ', in size and voltage reduction

Components must be ___ / lead. Therefore, the VLSI surface operating at a low voltage is switched to an external component such as an input/output (I/O) component and the like. However, the external component is not as large as the VLSI component. Therefore, many of the existing core voltages of VLSI components, β 7 small V L S I 7 components have quite a f, # α, plus I / O signal voltage amplitude, so that beans can = 2 electric 昼 conversion circuit ' to increase components. In the past few years, the VLSI components have dropped so that they are in the grass, and the operating voltage is going to & Du Xi into & AA In the case of February, the same high potential is used to generate the breakdown of the gate oxide layer as a coupling to the high voltage. As the soil shrinks, the gate oxide layer becomes very thin, so its gate is at the lowest voltage in the digital voltage range (such as 〇 乂, right: to high voltage (such as 3.3 volts)' Then the source to the gate, the source voltage to the gate voltage VCG and the drain to the gate voltage VDG ς ^ 'the breakdown voltage of the gate oxide layer, called Vbr (10). The neighbors are "more than [〇〇 -〇6 For example, today's VLSI components are manufactured in a 018 micron process. In a typical device, the thickness of the gate oxide layer is about A. It is known to those skilled in the art that the breakdown voltage of the dioxide (8) W is about == V/CM), and it is appropriate to limit the gate voltage to approximately 6 〇, which is the collapse threshold of the 〇. i 8 micron component. . 4 volts. 〇. 18 micron two - = appropriate VDDH. 8 volts (relative to the ground volts), the household jin with its logic ^ and shipped to the five core potential invention description (3) volt and logic "〇 " is 0 volts. Therefore, the problem of the collapse of the polar oxide layer. [〇m] The external portion of the VLSI device operates at a higher potential ( 70 仵 slaves (CMOS) components. The direct complement of the fruit (Guangzhou 3. volts) to 3. 3 volts, while the second 'will 〇. 18 micron P channel transmission: 70 channels of gate oxidation Layer. Known 浐屮: The operation system will be at the core potential logic; the power out I::: is sufficient to conduct the channel components, and is as high as:: [::』 is used, although the voltage reduction circuit provides I have encountered problems related to the application of high-tech in the three-state busbars, such as when it is low. So Lu, #,, 兀仵 关闭 且 且 且 叠 叠 叠 叠 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份 部份The oxide layer collapsed with the ?-type bungee domain is biased with an excess voltage, thus peaking at ^ 0,009] Another problem is that the hot carrier is injected into the Ifg small drive element occurs in the right 4-: t channel portion The question of the hot load voltage is :::; ΐ and the n-channel of the i1 closed-pole oxide layer. Some restricted carriers will change in the low-supply, electricity::: should be in the reduction of the heart element i To exclude, but this way can not be met, and there is no gate, need to be coupled to the oxygen semiconductor out of the component to pull up so it is possible to reduce the power f to the outside Element potential. This suspends the idle pole oxidation K; protection, when the pressure is applied, the busbar is still pulled by the diffusion region to cause the overlap zone effect and the hair is injected into the effector. In the high layer, this performance and time Can be used to reduce the drive, the invention description (4) the dynamic component needs to be coupled to the high voltage, because it can not be reduced at this time. I capture the voltage [0 0 1 0] Therefore, what is needed is to provide a The reduced drive element that can break the gate oxide when it is turned off. In addition, 4 needs to be = the drive element is protected from the high-voltage repeated switching caused by the hot carrier Note 2 should be such that its performance will not be reduced with time. < SUMMARY OF THE INVENTION [Summary] A small P channel element has a high power and a gate. When possible, the first phase has a drain and has a potential. The P channel is reduced in the output section [0012] And a second reduction point, and the coupling source has a 'one south member having a drain and a source coupled between the one-bit high voltage source. The first reduction is a pull-up signal 'When this pull-up signal is pulled high, a reduced P-channel component is turned off. The second reduced p-pass; the source, coupled to the first node and ;, connected to the -static voltage source. This meditation; 叮 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 缩小 缩小 缩小 缩小 缩小 缩小 缩小 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The invention provides a channel component of an output driving circuit, which is connected to the first package of the -i: voltage, and the component is lightly connected to the -th node potential. The = first voltage of the second channel 70 Coupling to the wheeled end and a [0011] the present invention provides a reduced output driver comprising first and second, channel elements and -n channel elements, first of which is reduced on page 10, 1254508. 5, invention description (5) Between. "In the configuration, the first-reduced p-channel component

One: to receive a pull-up signal, and the second to narrow-channel component I is connected to a static voltage. Each of the channel elements has an idle pole that receives the first and second pull down signals. Including a ^01, 3^^ invention provides an embodiment of an integrated circuit (ic) that includes a core driver and a reduced drive component. The source and a reference voltage source are defined - a lower voltage two::: electricity: the converter receives the first pull-up and pull-down signals, and the split signal system operates on a second pull-up and pull-down component, and the switch In the first - = : = between the first and the second narrow p channel. The reduced drive component is packaged between the first voltage source and an output and the reference voltage source. ^ Channel is connected to the input, connected to a static voltage, and the channel element has a - gate to avoid the first-reduced Ρ channel element state voltage has a potential, which can [〇m] the ^ ^ channel pole oxide layer collapse. The N-channel component is coupled to the input: the first and the second reduction of the series connection, and the reduction of the N-channel component has a gate and a reference voltage source. The second reduced N-channel component has a right chirp to receive a second pull-down signal, and the gate of the present invention receives the first pull-down signal. The rest of the description and the enthusiasm, benefits and advantages of the drawings will be more clearly seen in the reference to this article.

1254508

V. DESCRIPTION OF THE INVENTION (6) [Embodiment] [〇〇2 1 ] The following description is provided in the context of a specific embodiment and its necessary strips, so that those skilled in the art can utilize the present hair. However, various modifications to the preferred embodiment are apparent to those skilled in the art, and the principles discussed herein may be applied to other embodiments. Therefore, the invention is not limited to the specific embodiments shown and described herein. ,

[0 0 2 2 ] The inventor of the present invention has noticed that there is a need to use a reduced drive = piece 'which must have a high output voltage, such as driving a tri-state bus bar for such components, but not A high input potential is allowed, which is applied to the overlapping gate portions when the component is turned off. The inventor also thought that there is a need to avoid shrinking the hot carrier injection effect of the N-channel driving element under repeated switching of high voltage. Therefore, the inventors propose a reduction drive member that includes a pull-up portion that does not easily generate a gate oxide breakdown at high potential when closed; it also includes a pull-down portion The hot carrier injection effect is not easily generated at the repeated switching of high voltage, as described in the following figures 1 to 4. [0 0 2 3 ] FIG. 1 is a simplified block of a system 100 including a core circuit 丨〇1, a voltage conversion circuit IO3, a reduced drive element 丨〇5, and an 'external' component 丨〇7. Figure. The core circuit 101 receives power from the first voltage source. The first voltage source signal has a potential or voltage relative to the common or reference voltage source signal REF, and the reference voltage source signal REF is also sent.

Page 12 V. Description of the invention (7) to the core circuit 101. A power or voltage source (not shown) produces a source voltage between VDDL and REF. VDDL and REF together determine the first or lower voltage range (VDDL-REF) to provide power to 70 of the core circuit 1〇1. The core circuit 101 generates one or more logic signals or digital signals 'to provide respective inputs to one or more of the potential conversion circuits 丨03. Here, the digit π means that the component operates in a manner similar to a switch having a plurality of separate operating points, each operating point being associated with a different logic state and/or potential. [0 0 2 4 ] In the foregoing embodiment, the core circuit 丨〇 1 sets a pull-up signal PU and a pull-down signal PD to be supplied to respective input terminals of the voltage conversion circuit 1〇3. The PU and PD signals are used to drive an external tri-state bus to one of three modes, including a high logic state (when the ρυ signal is set), a low logic state (when the PD signal is set), and A third state (when neither PU nor PD signals are set). The PU and PD signals each have a first logic state at or near the REF potential and a first logic state at or near the VDDL potential. These logic states are commonly referred to as logic 壹 or , , , and logic zero or , 〇 ”. Here either positive or negative logic can be used, so any logic state 1 or 〇 may correspond to REF or VDDL. The conversion circuit 103 is coupled to VDDL and REF to provide power to the internal digital circuit to enable detection of the logic states of the PU and PD signals, as further described below. [0 0 2 5 ] Voltage Conversion Circuit 1 〇 3 Setting A pair of logic signals or digital signals PUPB and PDN are sent to the respective input terminals of the reduced drive elements 1 to 5. The PUPB signal reflects the logic state of the pu signal, while the pdn signal is inverted.

Page 13 V. Invention Description (8) The logical state of the PD ##. It should be noted that here "B„ is appended to the signal name or the input/output (I/O) pin' to indicate a logical negation, representing, inverting or complementary signal or I/〇 pin has The opposite logic is. For example, the PUPB signal is a logically complementary signal of the PUP signal (not shown), and the PUP signal has the same logic state as the PU signal. Since the (9) signal controls the P-channel component, it may be grouped. The state is a logic state with a signal such as pu.

The 4% small driving element 105 is switched to the second voltage source VDDH "a" and the two determine the second or high voltage range (VDDH_ 々 VDDH * RFfV p wide or voltage source (not shown) - The source voltage is between VDDH and REF. The size ratio of VDDH is higher than the range of the voltage range that is higher than the range of voltages associated with VDDL. Both ΐ^ΓΓ·TMΗ are positive, but this The invention uses a negative/1 source. The % small drive element 1〇5 generates a logic signal 0DS for the external components coupled to VDDH and REF} 宽5 〇〇 〇〇 27] 0DS signal operates at the second voltage with the first And the second logic is away from the 〇盥丨, i round this electric charge, the potential of the power. Because the positive logic "negative 1 logic can be from: electricity, bit 4: for /_ or sorrow 1 or 0 May correspond to REF or VDDH ^ solid logic core circuit 1 () 1 is a = 107 relative to the second form of sadness, when it is not set to logic 丨 or 丨 shape from t ^ ', eg, If PUPB is pulled high and ΡηΜ; κ 7 is less than 1%. The example is the third shape: Pila low: the rim of the drive element m is reduced to set the 0DS #5 tiger to the logic state〇

Page 14 J254508 V. Description of invention (9) (eg;: row 2 element i Μ may contain other drivers or similar components, such as bus line drive crying, when the mountain is out of the third position, Back to not shown), when the signal of the 0 of the reduced drive element 105 is set to logic two = the provided driver may additionally be a rhododendron, or a sorrow of 0 or 1. In this manner, the reduced drive element 70 may be exposed to a high potential in several situations, such as when the output of the member 105 is in the third state and the 0DS signal is pulled low by the π element. 1 ρπ b is in operation, it is desirable to transmit the logical tribute set by the core circuit 101 to the external component via the ODS signal; the PnM?tPD signal is converted into PUPB by the voltage conversion circuit 103, respectively. PDN# number. The reduced drive element 1〇5 transmits the logic of the pupB*pDN signal to the ODS signal. The external component 1〇7 is designed to operate with a logic signal within the potential definition = PMOS voltage range VDDH-REF, which is greater than the first or lower voltage range VDDL - ref. Therefore, the external element 107 must be driven to a potential higher than the pu and the assertion signal to facilitate logic switching. VDDH is supplied to the potential conversion circuit 1〇3 and the reduced drive element 105' to enable the two to operate within this high voltage range. The reduced drive element 105 cooperates with the switching of the PUPB and PDN signals to switch the ODS signal over the entire high voltage range to drive the input of the external component 丨〇7. [0029] The PUPB signal operates within a voltage conversion range based on the VDDH potential and is suitable for driving the input terminal of the reduced drive element 1〇5. This voltage conversion range does not cover the entire high voltage range, so the ρϋρΒ signal 3 - voltage converts the digital signal. In particular, the voltage conversion circuit 1〇3 will have a voltage conversion range between an intermediate potential (ΙΝΤ) and a VDDH potential, and

Sleep Page 15 1254508 V. Invention Description (10) PUPB signal. The magnitude of the INT potential is higher than REF, and its value is selected such that the voltage conversion range VDDH-I NT does not exceed the breakdown voltage of the reduced P-channel component in the reduced drive element 105. More specifically, when the PUPB signal is driven to the INT potential, the ODS signal can be driven to the potential of VDDH without causing the gate oxide layer to collapse when the P-channel component of the driving element 1 〇5 is turned on. Danger. [0 0 3 0 ] Several embodiments of the P D N signal are presented herein. In general, the PDN signal is sent to at least one N-channel component within the reduced drive component 1 , 5, wherein the reduced drive component 105 is used as a pull-down component. In one embodiment, the 〇DS signal is pulled low when the PDN signal is pulled high, and the ODS signal is pulled to the third state or pulled high when the PDN signal is pulled low, depending on the state of the PUPB signal. The PDN signal can operate over the high voltage range of VDDH-REF. As will be further explained below, the PDN signal can include multiple signals or be combined with another 5 Tiger to somehow reduce or eliminate hot carrier injection effects in one or more N-channel components. This is particularly advantageous for reduced N-channel components having short channels and thin gate oxide layers. [0 0 3 1 ] In one embodiment, the voltage conversion circuit 丨〇 3 is implemented in accordance with a related US patent application (Docket CNTR 207), entitled DIGITAL LEVEL SHIFTER FOR MAINTAINING GATE OXIDE INTEGRITY OF SCALED DRIVER DEVICES, which has the same Shen Qingyi, applicant and inventor, is included here. The digital potential converter described in the incorporated application incorporates the potential of a logic zero for the input of a high voltage output driver. The digital potential converter using the relevant application has several benefits. First, this

1254508

V. INSTRUCTIONS (11) The digital potential converter is fully described in the 'bits' as explained below. Intra-in: an integrated circuit (ic)

Several U-potential converters operating in the selected voltage range provide #uPDN^.. , ^ Ab 4 τ dry W in the W, to jointly perform the PUPB. The function of 旒 is described in the following paragraphs. L 〇 0 3 2 ] However, it should be noted that the applicable voltage conversion circuit is used to implement the conversion. The circuit 103 can be implemented in accordance with the analog voltage conversion circuit 103 using analog and digital circuits. Thunder ^ -r* generates a logical bias to the digital circuit. However, analog components are bulky and consume 31 components and therefore need to be separated and/or externally implemented. [00曰33] > The previously described 'integrated circuit design and process technology' make the transmission voltage down as the component size shrinks. For example, the core circuit 1〇1 may be a VLS I component integrated into a 1C's sequel to the frequency I L, and we would like to directly couple this 1C to the external component 丨〇7. In one, the voltage conversion circuit 103 is implemented as the digital conversion circuit incorporated in the above-mentioned U.S. application, and the digital conversion circuit 1〇3 and the reduced drive element 1〇5 are integrated into the same I c 1 0 9, The core circuit 丨〇i. Furthermore, the core circuit 101, the potential conversion circuit 103, and the reduced drive element 1〇5 are all implemented using the same circuit reduction technique, so that the \channel and p-channel elements constituting these circuits have a relatively thin gate oxide layer. . In this manner, IC 1 〇 g includes several external source pins or terminals for coupling to individual voltage sources as shown. [〇 〇 3 4 ] It is worth noting that the present invention is not limited to the foregoing implementation.

1254508 V. INSTRUCTION DESCRIPTION (12) For example, the voltage conversion circuit 丨〇3 and the reduced drive element 1〇5 are processed and/or on the same ic as the core circuit 101. Real = clothing: a circuit can be implemented separately without departing from the spirit of the invention;: range. For example, if the voltage conversion circuit 1〇3 is implemented on the IC 109 in a conventional manner, or at least included in the IC, i〇9, the ::= for analogy. However, with similar manufacturing techniques or manufacturing on the same K, there are significant advantages: Ϊ are well known to those skilled in the art. ^ 3 Heat [00 3 5 ] In a more specific embodiment, the lc meter process manufactures a coffee element that includes a thickness of about 4 〇 2? Oxygen: conductor (10)) component. For example, the core circuit; (Π Ϊ = processing =, the size and voltage need to be minimized. The idle oxide layer collapses electricity is about "volts irr, - u volt, qing - is 〇 Ϊ́ί"; both;: The maximum potential of the core circuit 101 is much lower than the breakdown voltage, there is no need to worry that the oxide layer will collapse. [0 0 3 6 ] In this embodiment, the outer % of the c: component, so The volts, the volts, the ^, 驱动, the drive element 105 include the 18.18 micron P channel and the N path 103 to operate the PUPB signal at approximately u. The voltage conversion power W is approximately U volts. Specific implementation:: and 3: between two special, and 2.3 volts, because the integration of the IC i 09 is reduced, the gate of the component is not reduced to m volts to H, f moving components 105 P channel since 2. 3 volts below crash

18th stomach 1254508 V. Invention description (13) "" ' ' ' · — Voltage VBRGX (about 2.4 volts), there is almost no risk of breakdown of the gate oxide layer when the p-channel component is turned on. As further described below, the reduced drive element 105 is configured to avoid conditions like a gate oxide collapse when the component is turned on and the 〇DS signal is pulled to 〇V.

[0 0 3 7] FIG. 2 is a detailed schematic diagram of a conventional reduced drive element 20 〇 according to the prior art implementation. This conventional reduction of the driving element 2 is used to illustrate the problem that if the gate electrode layer 5 is reduced as the driving element 图 5 of Fig. 1, the gate oxide layer collapses. The reduced drive element 2A includes a p-channel element 201, the drain of which is coupled to a corresponding N-channel element 203. The drain 205 will form an ODS signal. The p-channel element 2〇1 includes a p-type substrate 2〇7, an N-type well region (N-WELL) 20 9 and a pair of P-type diffusion regions (P+) 211 and 213. A gate insulating layer 215 is located over the N-well region 209 and overlaps the p-type regions 2 11 and 2 1 3 with the overlap regions 2 1 2 and 2 1 4, respectively, as shown. The drain 20 5 and the source 219 are connected to the P-type regions 2 11 and 213, respectively, and the gate 221 is connected to the gate insulating layer 2 15 . An N-type region (N + ) 2 2 3 is located on the N-well region 209, and an N-type well terminal 225 is connected to the N-well region 223 ° VDDH is coupled to the source 219 and the N-well terminal 22 5 °PUPB The signal is sent to the gate 221, and the PDN signal is sent to the N-channel component 2 0 3 〇PUPB and the PDN signal is used to control the conventional reduced drive component 2〇〇 to drive the 0DS signal into one of three states, as described above. Defined for three-state components. [0 0 38] As described above, the PUPB signal is supplied from the voltage conversion circuit 1 〇3 and maintained within the voltage conversion range of VDDH-I NT. This voltage conversion range prevents the turn-on voltage supplied to the gate 2 21 from being lowered to the potential of the oxide layer of the gate layer 2 15 , which is due to an excessive source to gate.

Page 19 1254508 ~ --------- - V. Invention Description (14) "" ------- Extreme or channel to gate voltage. However, the drain 2〇5 can be pulled down to the REF potential by any coupled component (e.g., external component 丨〇7 or any other busbar component not shown) or even N-channel component 2〇3. While the drain 2〇5 is pulled to the REF potential, if the PUPB signal is set to the high potential vddh and the P channel element 201 is turned off, the overlap region 212 is subjected to a high potential (JDDH-REF). This high potential causes the oxide layer in the overlap region 212 to collapse, even though most of the gate oxide layer of the gate insulating layer 215 only looks at the potential of the well 2, which is the same as the potential of the gate 221 is VDDfi. [. » [0 0 3 9] FIG. 3 is an exemplary circuit diagram of the reduced drive element 3A implemented in accordance with the present invention. The reduction of the driving element 3 can be used as the reduction driving element 105 of Fig. 1 to avoid the collapse of the gate oxide layer. The ρυρΒ signal is sent to the gate of a P-channel element P2. Is the source of P2 coupled to VDDH? The pole of 2 is coupled to a node 301, and the node 3〇1 is also coupled to a second? The source of channel element P1. The N-wells of P-channel components P1 and P2 are coupled to vddh. The gate is coupled to a static voltage (sv), and the drain of the ?1 and the N-channel component are coupled to the center, that is, the point 3 0 3 , and the intermediate node 3〇3 can form the 〇DS signal. This component 20 3 receives the PDN signal and is controlled by the PDN signal. Happen point ^1〇4〇] As shown in the figure, P1 is connected in series with P2, where the gate of P1 is connected. To a sv with a static potential. The potential is chosen to be the appropriate potential' so that the 汲 of the ρι is turned down to 〇V by the external element or possibly the N-channel element 2〇3, becoming a conduction r. When the source of P1 When the pole voltage drops to a protection potential (PVL), P1 is turned off. This protection potential is defined as the sum of the static potential (sv) and a critical potential ^ (TL), such as PVL = SV + TL. When the pupB signal is pulled Low time, 1254508 V. Invention description (15) The serial circuit configuration works as a pull-up component and pulls the output of both D1 and P2 to avoid excessively high gates and protects against VDDH. About 3. 3 volts and REF about 〇 volts. 18 micron layer _ voltage. The selected SV has a static potential of about 1 volt. Components and [ 0 04 1] When the PUPB signal is pulled high and ?2 is turned off, it is turned on. When the ODS signal is pulled low, it is like dropping to the REF potential (such as the conduction node 301 (P2's drain and pi source) discharge, and Hope, bit PVL. For 1 volt and the foot of the volts, the product potential is about 0.5 volts, so that the node 3〇1 is pulled down to about ι.

^ The gate of π is maintained at the potential of the sv signal, and the node 3()1 can only be discharged to the potential of PVL, so that when the source of P1 reaches pvL, ρ is closed to close. When P1 is turned off, the serial configuration of P1 and P2 protects p2曰. The gate is connected to the high voltage source VDDH, and when Ρ2 is turned off, the gate potential of Ρ2 is also V D D Η. However, when ρ 2 is turned off, the drain of ρ 2 will only drop to the protection potential... PVL. In this way, it can be seen that the selection of SV is used to prevent the collapse of the gate oxide layer when ρ2 is turned off. Ρ1 can also be protected from excessive oxide voltage, because pi will only withstand a gate to drain voltage Vgd (sv-REF); for 0. 18 micron process, when sv is about 1 volt and REF is about At volts, sV REF is about 1 volt. 〇 [ 0 0 4 2 ] FIG. 4 is a circuit diagram of a reduction of the moving 7L piece 40 0 according to another embodiment of the present invention, wherein the reduced driving element 4 is coupled to the electric=conversion circuit 1 〇3 An exemplary embodiment. Reducing the drive element 4 〇 〇 can additionally reduce the drive element 1 〇 5 for Figure 1 to prevent gate oxide breakdown and ... carrier injection effects. Figure 4 and the components used to reduce the drive component 3 〇〇

1254508 V. INSTRUCTIONS (16) -- Like components, having the same reference numerals. The voltage conversion circuit 101 includes a pair of digital potential conversion circuits 401 and 4, 3, both of which are implemented in accordance with the aforementioned U.S. Patent Application. Each of the digital potential conversion circuits 4〇1 and 401 references to VDDL, VDDH, and REF, and includes a first stage 4〇5 and a second stage 407. For each of the digital potential conversion circuits 4〇1 and 4〇3, the first stage 405 has a pair of complementary input terminals IN*INB for receiving a pair of corresponding complementary input signals, the logic state of which is between Between vdd i REF. The first stage 4〇5 cooperates with the switching of the input signal to switch a pair of corresponding digital output signals of the complementary output terminals 〇UT1 and 〇UT1B between ddl and an intermediate potential such as INT. The output signals of the output terminals 〇υτι and OUT1B of the first stage 4〇5 are sent to the input terminals (7) and Ι^Β of the second stage 4〇7, respectively. The complementary outputs 〇UT2 and 〇UT2B of the second stage 4〇7 cooperate with the switching of the input signals, and each switches between VDDH and the intermediate potential INT. [0 043] As shown, the first stage 405 of the digital potential conversion circuit 4 receives a complementary signal pair pu and provides a PUPB signal at the OUT2B round of the corresponding second stage 4〇7. It should be noted here that both positive and negative logic must be considered. For positive logic, the PU signal pair contains the PU signal sent to the input stage IN of the first stage 4〇5, and the complementary signal ρυβ sent to the input terminal ΙΝβ. 4 The first stage of the potential conversion circuit 4 〇 3 4 〇 5 receives the complementary signal pair p d , the second pair of PD is similar to the signal pair PU, as if it contains the pD signal and the port complementary signal PDB. Send to the input IN? The 11 signal is used as a pM signal that switches between the potentials of VDDL and REF. The first stage of the round-trip UT1 forms a PDNS signal, which is the voltage limit or voltage of the PDN signal.

Page 22 1254508 V. Description of invention (17) Formed by conversion. In particular, the PDNS signal is switched between V^DL and INT potential in conjunction with switching of the PDN signal. The second stage, 4〇7, is configured to switch the output of the voltage-limited output of the first stage 405. [0044] The reduced drive element 4〇〇 contains a p-channel element? 1 and? 2, the two are essentially equivalent to reducing the drive component 3? 1 and? The mode of 2 is coupled to node 301, which is also coupled between several (four) and node 3〇3, wherein node 303 can form an ODS signal. The n-channel component 203 is replaced by a series of configured N-channel components N1 and N2. The N-channel element N2 has a source coupled to the node 303, a source connected to the drain of the N-channel element n 1 , and a gate receiving the mns signal. N1 has a source coupled to the REF and a gate receiving the pM signal. The N-type wells of N1 and N2 are coupled to their respective sources, so the N-type well of N1 is consumed by REF, and the N-type well of N2 is coupled to the drain of N1. A [通道 〇 4 5 ] series connected N-channel elements N 1 and N 2 together form a pull-down phase of the reduced drive element 400. In one embodiment, N1 and ... have a relatively short channel and a thin gate oxide thinning element. The series element N2 can be used to eliminate the hot carrier injection effect generated by N1 due to the switching of the high potential. As described, the hot carrier effect typically occurs in N-channel components with very short channels and thin gate oxide layers. At repeated switching of high voltages, the carriers are accelerated so as to fall into the oxide layer. These restricted carriers change the critical value of the component and reduce component performance. In a tandem configuration, the logic of the N2 gate is a function of the N1 gate because the PDNS signal driving the n 2 gate is a function of the PDN signal driving the N1 gate. In the illustrated embodiment, the lower limit of the voltage limit signal PDNS for driving the N2 gate is about the mid-between potential INT, not the REF potential. N2 can be used to protect N1 because the 〇DS letter

Page 23 1254508 V. Invention Description (18) At the moment when the high voltage VDDH is switched to the REF potential, the overall operation of the N2 and N1 components is the same resistor divider (resist〇r divider) to avoid the hot carrier of N1. effect. The high voltage load is dispersed by κΝ1 and (10). [0 046] When the PDN signal is pulled to REF and N1 is turned off, the PDNS signal driving the N2 gate voltage is reduced to the intermediate potential INT to protect N2 from the transient change of the ODS signal on the bus. Due to the effects of the transmission line, the voltage of the 〇ds signal may drop below the REF potential. For example, when N1 is turned off and the N2 gate has a different VDDL potential, if there is a change in node 3〇3 to pull the gate of N2 below the REF potential, then N2 will withstand a gate that can be = ^ Channel voltage. Avoid the practice, tNi is turned off a inch, the gate voltage of N2 is reduced to INT potential to prevent excessive gate-to-channel voltage due to temporary changes in the economy. [〇〇47] It should be noted that although the reference to the 18 micron element and its associated potential is used herein to explain how the invention solves the related problems of the driving element, the same solution is fortunately - Η Λ, ^ /iL image It can be applied to larger and 鲂/丨, ...$ is because the gate oxide layer collapses = process related, and also with the application of the component 'that is, the component;; = the clothing is closely related to the overvoltage requirement. Therefore, this & , the non-invention of its components is not limited to Π 1 β 止 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The voltage source signal may be indeterminate to define any apricot potential and pole for a particular process.

Ref can be converted to a non-zero potential, while its second, electrical, and upper ranges. For example, 'change' to determine the ideal or appropriate voltage. The two responsibilities: the converter, the application situation and the relative potential, and the voltage is based on the system.

Page 24 1254508 V. INSTRUCTIONS (19) Polar oxide layer. [0 0 4 8 ] While the invention has been described in detail with reference to the particular preferred embodiments, For example, a particular potential and/or voltage range may vary depending on the component type or manufacturing process. The associated potential of the 〇18 micron element has been described in the exemplary embodiments, and it is also well known to those skilled in the art that the present invention can be applied to smaller and larger elements associated with the same or different potentials. Positive or negative logic is also considered. The Ρ channel and Ν channel elements can be implemented as pM 〇 s and 〇 8 elements, respectively, as is well known to those skilled in the art of PM 〇 s and ( iv ) ( VIII ) transistors.

[0 049] Furthermore, the breakdown of the gate oxide layer of the general M〇s type component is not only related to the component system, but also to the application of the component, including the components to be coupled. The voltage requirements of her components are closely related. It is to be understood that the scope of the patent application is only the scope of the invention. In the scope of the patents covered by this invention, dual mastering/modification should still belong to the present invention. "月贝番查委明鉴, and pray for the right,

Page 25 1254508 Brief Description of the Drawings [0016] In conjunction with the following [0017] A detailed diagram [0019] including a voltage conversion circuit [0018] is included; [0020] a voltage conversion circuit for driving the device And other objects, features and advantages will be better understood from the following description. FIG. 1 is a simplified block diagram of a system which is one of the embodiments of the present invention. The core circuit, and a reduced drive component, and an "external" component - the second diagram is based on the prior art implementation of the prior art; I move, Figure 3 is a reduced drive element and 1 thousand Figure 4 implemented in accordance with the present invention It is a circuit diagram of another embodiment according to the present invention, wherein an exemplary embodiment of the reduction of the drive element is reduced. The description of the figure to the figure is: 100 System 101 103 Potential converter 105 107 External component 109 200 Zoom out Drive element 201 203 N-channel element 205 207 p-type substrate 209 211 P-type region 212 213 P-type region 214 215 gate insulation layer 219 221 gate 223 core circuit hundred small drive Element 1C p channel element no pole N type well area overlap area overlap area source N type area 1254508 Brief description of the diagram 225 N type well terminal 300 reduction drive element 301 node 303 intermediate node 400 reduction drive 7L piece 401 digital potential conversion circuit 403 Digital potential conversion circuit 405 first stage 407 second stage

Page 27

Claims (1)

1254^08 r Six-package 敎 马 马 范 范 范 范 范 范 范 范 范 范 范 范 范 范 范 范 范 rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt rt With high parts, there is a yuan road and a ptt 1J 03^ section, the first one, P oiub, the letter is high, the first one is to receive the meeting, and the last bit gn^tir is high. The pull-up element is pulled up by the track number communication P. This is the case when the source is connected to the pole source and the pole is - there is a piece of elemental, and the 1 closed-closed piece of the elementary element is reduced to the second pass. The pole gate 1 1 has a parallel source, and the pressure between the pressure points is the static point. The source is pressed and the power is saved. The first state is stopped. , the closure of the collapsed layer of the elemental oxygen pass P leisure small shrinkage of the first element of the pass of the source of the test and the point section of the output of the contact element of the pass. N, 1 yuan, 1st, the first, the same, the standard P, when 9ΠΊ, L #da, condensed, please pass the application, if it is 2, the small squeezing and driving, the second, the second, the second, the second, the second, the second Time protection - near the point of the device to drive out the loss and shrink. Closed item 2 3 Dimensional encirclement. 々巳I piece JG spear 'special road, p medium and small as 3, the middle part of the two yuan pass the Hai-xHcr in the middle of the line, the electric system ^ /Λ - The. Drive and go out, d loses the pressure of the Ϊ 户 户 第 第 户 户 户 户 户 范 范 范 范 范 范 范 范 范 范 范 i i i i i i i i i i i i i i i i i i i i i i i i i To the first drop. Circumstances of the closed-door black--the beginning of the section, the opening of the section, the application of the yuan, the number of the passage, the passage of the passage, the passage of the small section, the movement of the section, and the Page 28 1254508 VI. Patent Application Range The pull-up signal operates at a voltage conversion range between the high potential and an intermediate potential, wherein the intermediate potential is between the high potential and the reference voltage source. 6. The reduced output driver of claim 1, wherein the first and second reduced p-channel components are each a 1.8 micron device having a gate oxide thickness of approximately 40 angstroms, wherein the height is The potential is about 3.3 volts, the reference voltage source is about 0 volts, and the quiescent voltage source potential is about 1 volt. 7. The reduced output driver of claim 1, wherein the N-channel component comprises: a first reduced N-channel component having a gate and having a gate and a source coupled to a Between the second node and the reference voltage source; and a second reduced N-channel component having a gate and having a pole and a source coupled between the output node and the second node; The gates of the first and second reduced N-channel components receive first and second pull-down signals, respectively. 8. The reduced output driver of claim 7, wherein the first and second reduced N-channel components cooperate as a resistor divider during transient switching of the output node to prevent hot carriers effect. 9. The reduced output driver of claim 7, wherein the first pull low signal is operated in a lower voltage range between a lower voltage source and the reference voltage source, and the second pull low The signal system operates at a limit voltage range between the lower voltage source and an intermediate potential, wherein the middle Page 29 1254508 6. Patent application range The potential system is between the lower voltage source and the reference voltage source. An output drive circuit, comprising: a first and a second reduced P-channel component connected in series, coupled to a first node, and coupled between a first electric dust source and a round output end, The voltage source has a high potential; and the first and second reduced N-channel components connected in series are coupled between the output terminal and a reference voltage source; wherein the first reduced P-channel component has a gate Receiving a pull-up signal, wherein the second reduced p-channel component has a gate that is consuming a static voltage, and the first and second reduced N-channel components each have a gate to receive the first and/or the Two pull low signal. 1 1 The output drive circuit of claim 10, further comprising: a voltage conversion circuit that receives a first pull-up signal operating in a lower voltage range and provides a corresponding second pull a high signal to the gate of the first reduced P-channel component, wherein the second pull-up signal is operated in a voltage conversion range between the high potential and an intermediate potential, wherein the intermediate potential is between the high potential and Between the reference voltage sources. 12. The output drive circuit of claim 1, wherein the static voltage is selected to control the first reduced p-channel component to maintain the first node at a sufficiently high voltage to prevent The gate oxide layer of the first reduced p-channel component collapses. 13. If the output drive circuit described in the first paragraph of the patent application is applied, Page 30 1254508 a potential conversion circuit for receiving the first pull-down signal and providing the second pull-down signal; and wherein the first pull-down signal is operated between the reference voltage source and a second voltage source lower than the south potential And the second pull-down signal is operated between the second voltage source and an intermediate potential, wherein the intermediate potential is higher than the reference voltage source and lower than the second voltage source. The output drive circuit of claim 13, wherein the intermediate potential is selected to prevent the second small N-channel component from being closed when the first pull-down signal is turned off. Second, the n-channel component has an excessive gate-to-channel voltage. 15. The output drive circuit of claim 1, wherein the series of first and second reduced N-channel components are used to spread the load and avoid hot load injection effects. 16· An integrated circuit (1C), comprising: a core circuit consuming between a reference voltage source and a first voltage source to generate a first pull-up signal and a first pull-down signal, each of which Operating in the lower voltage range defined by the reference voltage source and the first voltage source; a digital potential converter coupled to the reference voltage source, the first voltage source, and a second voltage source higher than the first voltage source for receiving the first pull-up signal to provide an associated a second pull-up signal 'and receiving the first pull-down signal to provide an associated first pull-down signal, wherein the second pull-up and pull-down signals are Page 31 1254508 々, the patent application range between the reference voltage source and the second voltage source; and a reduced driving component, comprising: the first and second reduced p-channel components connected in series, coupled to a first node And coupled between the first voltage source and an output terminal; and an N-channel component coupled between the output terminal and the reference voltage source; wherein the first reduced P-channel component has a gate Receiving the second pull-up signal, the second reduced P-channel component has a gate coupled to a static voltage, wherein the static voltage has a potential to prevent the gate oxide layer from collapsing in the first reduced P-channel component . The integrated circuit of claim 16, wherein the N-channel component comprises: a first and a second reduced N-channel component connected in series, coupled to the output terminal and the reference voltage source And wherein the first reduced N-channel component has a gate to receive the second pull-down signal, and the second reduced-N-channel component has a gate to receive the first pull-down signal. The integrated circuit of claim 17, wherein the digital potential converter comprises: a first digital potential converter coupled to the reference voltage source, the first and second voltage sources Receiving the first pull-up signal and providing an associated second pull-up signal, wherein the second pull-up signal is between the second voltage source and an intermediate voltage, the middle Page 32 1254508 6. The patent application range voltage is between the reference voltage source and the first voltage source; and a second digital potential converter coupled to the reference voltage source and the first voltage source for receiving The first pulls down the signal and provides a second pull low signal, wherein the second pull low signal is between the first voltage source and the intermediate voltage. 1. The integrated circuit of claim 18, wherein the core circuit, the first and second digital potential converters, and the reduced driving element are manufactured by 0.18 micron components, each The 0.8 micron element has a gate oxide layer having a thickness of about 40 angstroms. The first voltage source is about 1.8 volts, the reference voltage source is about 0 volts, and the second voltage source is about 3. 3 For volts, the intermediate voltage is about 1 volt and the quiescent voltage is about 1 volt. Page 33