1250555 16261twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種基板及其製作方法，且特 關於一種利用實心的導電塊以導通各線路層之基板及 作方法。 θ ^ 一製 【先前技術】 由於電子科技的進步及需求，各種電子相關產品 朝向小型化及多功能化的方向發展，並帶動相關二制 程技術朝向更高的積極度邁進。為了使封裝後之晶片^ 更小、複雜度更高，諸如覆晶（Flip Chip，FC) = 腳格狀陣列（BaiiGridArray，BGA)封裝以及晶片^二 裝（Chip Scale Package, CSP)等封裝技術更廣為產所 ，用。此外，電路板（PCB)方面，為了提高線路密厂 tfZ (Build-Up) (Lamination) 相成具有多層線路的電路板，而上述之覆晶封裝及Β〇Α 封^所使用之封裝基板亦在此應用範圍内。然而，無 =基板或是多層電路板，皆具有多個貫？多層基板的導BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate and a method of fabricating the same, and to a substrate and a method for conducting a circuit layer using a solid conductive block. θ ^ One system [Prior Art] Due to the advancement and demand of electronic technology, various electronic related products are developing toward miniaturization and multi-functionality, and the related two-process technology is moving toward higher enthusiasm. In order to make the packaged wafers smaller and more complex, such as Flip Chip (FC) = Baii Grid Array (BGA) package and Chip Scale Package (CSP) packaging technology More widely used in production. In addition, in terms of a circuit board (PCB), in order to improve the line-factory tfZ (Build-Up) (Lamination) to form a circuit board having a multi-layer circuit, the above-mentioned flip chip package and the package substrate used for the package are also Within the scope of this application. However, none of the substrates or multilayer boards have multiple passes? Multi-layer substrate guide
Th_gh HGle，PTH)，時f生連接不同的圖 案線路層，進而作為不同線路之_訊號連接路徑。 作法二It· ^ ~不分別為習知之基板上的導電通孔之製 f圖。以下將搭配圖示制基板上的導電通孔之 首先，如圖1Α所示，提供一基板1〇〇，此基板1〇〇 之上下表面分別具有一銅箔102，而此基板1〇〇例如係以 5 1250555 16261twf.doc/g 機械鑽孔（Mechanical Drilling)的方式依序形成一個一個 的貝孔104。接著’如圖1B所示，對基板100進行全面鍵 銅步驟’以分別在銅箔1〇2之表面及貫孔1〇4内壁形成一 銅金屬層no。最後，如圖1C所示，進行塞孔（Plugging) 的處理’此步驟係以印刷（printing)的方式，將塞孔用油 墨106填入貫孔104中，如此一來，即可完成導電通孔製 程。其中，塞孔的處理主要是用以防止水氣進入貫孔1〇4 中’因而造成爆米花效應（p〇pc〇rn]Effect)。 在完成上述導電通孔之製程後，便可對基板100表面 之銅金屬層110進行圖案化（Patterning)的步驟，以於基 板1〇〇之上下表面形成圖案化線路層110a與ll〇b，如此 一來，便完成雙層線路板15〇之製作。如圖m所示，位 於基板100上下表面之圖案化線路層110a與ll〇b，係分 ，藉由貫孔U)4内壁上的導電们服相互導通。而應用於 夕廣線路板％· ’―層以上不同的圖案化線路層更可藉由導 電通孔相互連接，以達到訊麟遞之目的。 上述導電通孔是屬於空心的孔洞結構，而基板上下表 壁的銅金制ij-t 魏方式軸於導電通孔内 丁—者之電性連接。然而，以電鍍方式形 成之銅金屬的品質當备阳帝 的改變等因夸而I 的配方、溫度及輸入電流 产 ’、有所改變，此即影響到導電通孔之可靠 度(1llty)，進而影響到整個基板的可靠度。 面之=線成時，需犧牲部分的基板表 乂形成貝孔以及著陸墊（LandArea)， 因此，如何提出一種新的基板結構及其製作方法，以 解決傳統導電通孔所面臨到可靠度的問題，並簡化整個基 板及其導電通孔之製程，且降低其製作成本，實為亟待解 決之一大難題。 【發明内容】Th_gh HGle, PTH), when connected to different pattern circuit layers, and then as the signal connection path of different lines. The second method of the method is not the same as the fabrication of the conductive vias on the substrate. Hereinafter, the conductive vias on the substrate are shown as follows. First, as shown in FIG. 1A, a substrate 1 is provided. The upper surface of the substrate 1 has a copper foil 102, and the substrate 1 is, for example, One bayhole 104 is sequentially formed in the manner of 5 1250555 16261 twf.doc/g Mechanical Drilling. Next, as shown in Fig. 1B, the substrate 100 is subjected to a full copper bonding step to form a copper metal layer no on the surface of the copper foil 1〇2 and the inner wall of the through hole 1〇4, respectively. Finally, as shown in FIG. 1C, the process of plugging is performed. This step is to fill the plug hole with the ink 106 into the through hole 104 in a printing manner, so that the conductive pass can be completed. Hole process. Among them, the treatment of the plug hole is mainly for preventing moisture from entering the through hole 1〇4 and thus causing a popcorn effect (p〇pc〇rn]Effect). After the process of the conductive vias is completed, a step of patterning the copper metal layer 110 on the surface of the substrate 100 may be performed to form patterned circuit layers 110a and 110b on the upper surface of the substrate 1? In this way, the production of the double-layer circuit board 15 is completed. As shown in FIG. m, the patterned circuit layers 110a and 110b located on the upper and lower surfaces of the substrate 100 are electrically connected to each other by the conductive bodies on the inner walls of the through holes U)4. The patterned circuit layers which are applied to the different layers of the HUAWEI circuit board can be connected to each other through the conductive vias to achieve the purpose of the communication. The conductive via is a hollow hole structure, and the copper-gold ij-t-mode of the lower surface of the substrate is electrically connected to the conductive via. However, the quality of the copper metal formed by electroplating is changed by the formulation, temperature and input current of the preparation of the Yang Emperor, which affects the reliability of the conductive via (1llty). This in turn affects the reliability of the entire substrate. When the surface is formed, it is necessary to sacrifice a part of the substrate surface to form a beacon hole and a landing pad (LandArea). Therefore, how to propose a new substrate structure and a manufacturing method thereof to solve the reliability of the conventional conductive via hole The problem, and simplifying the process of the entire substrate and its conductive vias, and reducing the manufacturing cost thereof, is a major problem to be solved. [Summary of the Invention]
1250555 i^eitwf.doc/g 孔徑亦有其最小尺寸上的限制，因此，整個 :、甬：?： a本必增加’以提供足夠的面積來配置所需的導 屯通孔。再者’由上述導電通孔之製程可知：整 =作财相當的魏，需先於純上軸電難子層 (銅 >白）’之後’再經過鑽孔、電鑛...等處理 ’如此-來，不僅會增加製作基板上之= k孔所而的日守間，也會提高整個基板的製作成本。 ♦本务明的目的就是在提供一種基板，係利用實心的導 電塊以導縣板之各料層，以提高基板之可靠度。 、胃本發明的再一目的是提供一種基板，係利用尺寸較小 之導電塊導通基板之各線路層，以降低基板之尺寸及其厚 度。 、 本發明的又一目的是提供一種具有較為簡化之製 程，並有助於提高生產效率之基板的製作方法。 本發明的另一目的是提供一種基板的製作方法，此基 板=僅可作為一般的核心板來使用，且亦可將多個疊合基 板壓合成一具有多層線路層之基板，以擴大其應用範圍。 為達上述或其他目的，本發明提出一種基板，此基板 包括一介電層及至少一導電塊。其中，此介電層具有相對 7 I250555itwfd〇c/g 應的第一表面及第二表面，而此導電塊係配置於介電層 内，其包括一第一凸塊、一第二凸塊及一金屬層，此金屬 層係配置於第一凸塊與第二凸塊之間。 在本發明之一較佳實施例中，此基板更包括一第一導 電層及一第二導電層。此第一導電層及第二導電層係分別 配置於介電層之第一表面及第二表面上，且第一凸塊係連 接第一導電層，而第二凸塊係連接第二導電層。 在本發明之一較佳實施例中，此第一導電層及第二導 電層例如係為一圖案化之線路層。 在本發明之一較佳實施例中，此基板更包括一第一銲 罩層，此第一銲罩層係配置於第一導電層上，並暴露出部 分的第一導電層。 在本發明之一較佳實施例中，此基板更包括一第一抗 氧化層，此第一抗氧化層係配置於第一銲罩層所暴露 第一導電層上，且第一抗氧化層例如包括一鎳/金層。、 在本發明之一較佳實施例中，此基板更包括一第二銲 _ 罩層，此第二銲罩層係配置於第二導電層上，並暴露出部 分的第二導電層。 在本發明之一較佳實施例中，此基板更包括一第二抗 f化層’此第二抗氧化層係配置於第二銲罩層所暴露出的 第二導電層上，且第二抗氧化層例如包括一鎳/金層。 在本發明之-較佳實施例中，此第一凸塊與第曰二凸塊 之材質例如包括銅，而金屬層之材質例如包 為達上述或其他目的，本發明再提出一種基板，此基 1250555 16261twf.doc/g 板^括一疊合層、一第一表層線路、一第二表層線路及多 個導電塊。纟中，此疊合層具有相對應的第一表面及第二 表面，且其包括多個介電層及至少一導電層，此導電層係 配置於相連的兩介電層之間。此第一表層線路與第二表層 線^係分別配置於疊合層的第一表面與第二表面之上。而 電塊係配置於各個介電層内，以導通第一表層線路、 ，電層與第二表層線路，且各導電塊係由一第一凸塊、一 第一凸塊及一金屬層所組成，此金屬層係配置於第一凸塊 與第二凸塊之間。 在本發明之 ^ 1 交佳實施例中，此基板更包括一第一銲 部艾^第―料層係配置於第—表層線路上，並暴露出 邛刀的弟一表層線路。 氧化Ϊ本佳實施例中，此基板更包括一第一抗 — a弟一抗氧化層係配置於第一銲罩層所暴露的第 t路上’且第—抗氧化層例如包括-鎳/金層。 罩層，此ί明t幸交佳實施例中，此基板更包括一第二銲 部分的第SC係配置於第二表層線路上，並暴露出 氧化ΐ本:i月較佳實施例中’此基板更包括-第二抗 二表層線路:Γ;化層係配置於第二銲罩層所暴露的第 在本發明之Η抗氧化相如包括—錄/金層。 之材質例如包括銅中，：第-凸塊與第二凸塊 為達上述或其侦主Μ Μ之材質例如包括鎳。 〜、目的，本發明另提出一種基板的製作 1250555 16261twf.doc/g Γ匕包含下列步驟：首先，提供—複合導電層， 口 層包括多個金屬層；之後， 層外側之至少一全^ 夕γ α木化此複口 ¥兒 孟屬層，以形成多個第一凸塊；接著， =弟:⑽之間形成一第一介電層，且第一介電層係 Ί 凸塊的頂面；然後，圖案化此複合導電層 ί ::卜側，以形成多個對應於上述第-凸塊的第二凸 二Τ ’於ί一介電層上且在第二凸塊之間形成-第二1250555 i^eitwf.doc/g The aperture also has its minimum size limit, so the entire :, 甬:?: a must be increased to provide enough area to configure the desired via. Furthermore, 'the process of the above-mentioned conductive vias can be known: the whole = the wealth of Wei, which needs to be preceded by the pure upper-axis electric hard sub-layer (copper > white), then drilled, electric mine, etc. The treatment of "this" will not only increase the day-to-day spacing of the k-holes on the substrate, but also increase the manufacturing cost of the entire substrate. ♦ The purpose of this task is to provide a substrate that utilizes a solid conductive block to guide the layers of the plate to improve the reliability of the substrate. Further, it is a further object of the present invention to provide a substrate in which each of the circuit layers of the substrate is turned on by a small-sized conductive block to reduce the size and thickness of the substrate. It is still another object of the present invention to provide a method of fabricating a substrate having a relatively simplified process and contributing to improved production efficiency. Another object of the present invention is to provide a method for fabricating a substrate, which can be used only as a general core board, and can also laminate a plurality of stacked substrates into a substrate having a plurality of wiring layers to expand the application thereof. range. To achieve the above or other objects, the present invention provides a substrate comprising a dielectric layer and at least one conductive block. The dielectric layer has a first surface and a second surface opposite to the surface of the I, and the conductive layer is disposed in the dielectric layer, and includes a first bump and a second bump. a metal layer disposed between the first bump and the second bump. In a preferred embodiment of the invention, the substrate further includes a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first surface and the second surface of the dielectric layer, and the first bump is connected to the first conductive layer, and the second bump is connected to the second conductive layer . In a preferred embodiment of the invention, the first conductive layer and the second conductive layer are, for example, a patterned circuit layer. In a preferred embodiment of the invention, the substrate further includes a first solder mask layer disposed on the first conductive layer and exposing a portion of the first conductive layer. In a preferred embodiment of the present invention, the substrate further includes a first anti-oxidation layer disposed on the first conductive layer exposed by the first solder mask layer, and the first anti-oxidation layer For example, a nickel/gold layer is included. In a preferred embodiment of the invention, the substrate further includes a second solder mask layer disposed on the second conductive layer and exposing a portion of the second conductive layer. In a preferred embodiment of the present invention, the substrate further includes a second anti-fusing layer, the second anti-oxidation layer is disposed on the second conductive layer exposed by the second solder mask layer, and the second The oxidation resistant layer includes, for example, a nickel/gold layer. In the preferred embodiment of the present invention, the material of the first bump and the second bump includes, for example, copper, and the material of the metal layer is, for example, for the above or other purposes, and the present invention further provides a substrate. The base 1250555 16261twf.doc/g board includes a laminated layer, a first surface layer line, a second surface layer line, and a plurality of conductive blocks. In the crucible, the laminated layer has a corresponding first surface and a second surface, and includes a plurality of dielectric layers and at least one conductive layer disposed between the two connected dielectric layers. The first surface layer and the second surface layer are respectively disposed on the first surface and the second surface of the laminated layer. The electrical block is disposed in each of the dielectric layers to turn on the first surface layer, the electrical layer and the second surface layer, and each of the conductive blocks is formed by a first bump, a first bump, and a metal layer. The metal layer is disposed between the first bump and the second bump. In the preferred embodiment of the present invention, the substrate further includes a first soldering portion disposed on the first surface layer and exposing the younger surface layer of the file. In the preferred embodiment of the cerium oxide, the substrate further comprises a first anti-a-anti-oxidation layer disposed on the t-th road exposed by the first solder mask layer and the first anti-oxidation layer comprises, for example, -nickel/gold Floor. In the preferred embodiment, the substrate further includes a second solder portion of the SC system disposed on the second surface line and exposing the ruthenium oxide: in the preferred embodiment of the month The substrate further includes a second anti-two-layer circuit: the germanium layer is disposed on the second solder mask layer and is exposed to the second anti-oxidation phase of the present invention, such as a recording/gold layer. The material includes, for example, copper, and the first bump and the second bump are materials such as nickel or the like. ~, the purpose, the present invention further proposes the fabrication of a substrate 1250555 16261twf.doc / g Γ匕 includes the following steps: First, provide a composite conductive layer, the mouth layer comprises a plurality of metal layers; afterwards, at least one of the outer layers of the layer γ α is ligated to form a plurality of first bumps; then, a first dielectric layer is formed between (10), and the first dielectric layer is a top of the bump And then patterning the composite conductive layer ί :: to form a plurality of second bumps corresponding to the first bumps on the first dielectric layer and forming between the second bumps -second
;| = a，=此第二介電層係暴露出第二凸塊之頂面，如此 一來’即完成基板之製作流程。此基板不僅可作為-般具 有又層線路層之基板來使用，且亦可作為線路基板中的核 心板來使用。 在本發明之一較佳實施例中，此複合導電層係由第一 外層金屬層、第二外層金屬層及中間金屬層所組成，而此 中間金屬層係配置於第一外層金屬層與第二外層金層之 間。 在本發明之一較佳實施例中，在圖案化上述複合導電 層外侧之至少一金屬層時，係圖案化此第一外層金屬層， 而在圖案化此複合導電層之另一外侧時，係圖案化此第二 外層金屬層與中間金屬層。 在本發明之一較佳實施例中，在圖案化上述複合導電 層外側之至少一金屬層，係圖案化此第一外層金屬層與中 間金屬層，而在圖案化此複合導電層之另一外側時，係圖 案化此第二外層金屬層。 在本發明之一較佳實施例中，在形成第一介電層之 1250555 16261twf.doc/g 後’更包括固化此第一介電層的步驟；同樣地，在妒 二介電層之後’更包括固化此第二介電層的步驟。/ ^ 在本發明之一較佳實施例中’在形成上述第二介+ 之後，更包括下列步驟：減，在第-介電層與第二= 層之外側表面上分別形成一第一表層線路鱼一第二表芦= 路；接著，在第一介電層與第二介電層上^別形二二二， 銲罩層與一第二銲罩層，其中，此第一 八^ 鲆罩層係暴露出部;| = a, = This second dielectric layer exposes the top surface of the second bump, thus completing the fabrication process of the substrate. This substrate can be used not only as a substrate having a further wiring layer but also as a core plate in a wiring substrate. In a preferred embodiment of the present invention, the composite conductive layer is composed of a first outer metal layer, a second outer metal layer and an intermediate metal layer, and the intermediate metal layer is disposed on the first outer metal layer and Between the outer layers of gold. In a preferred embodiment of the present invention, when at least one metal layer outside the composite conductive layer is patterned, the first outer metal layer is patterned, and when the other outer side of the composite conductive layer is patterned, The second outer metal layer and the intermediate metal layer are patterned. In a preferred embodiment of the present invention, at least one metal layer outside the patterned composite conductive layer is patterned to pattern the first outer metal layer and the intermediate metal layer, and the other of the composite conductive layers is patterned. On the outside, the second outer metal layer is patterned. In a preferred embodiment of the present invention, after the formation of the first dielectric layer 1250555 16261 twf.doc/g, the step of curing the first dielectric layer is further included; likewise, after the second dielectric layer Further comprising the step of curing the second dielectric layer. / ^ In a preferred embodiment of the present invention, after forming the second dielectric layer, the method further comprises the steps of: subtracting, respectively forming a first surface layer on the outer surface of the first dielectric layer and the second layer Line fish a second table a = road; then, on the first dielectric layer and the second dielectric layer, the shape of the second layer, the welding layer and a second welding layer, wherein the first eight鲆 系 暴露 exposed part
刀的弟一表層線路，而此第二銲罩層係暴露出部分的 表層線路；最後，在第一銲罩層所暴露出的部分第―: 線路上形成-第-抗氧化層，並且在第二轉層所暴= 的部分第二表層線路上形成一第二抗氧化層。。出 在本發明之一較佳實施例中 第二抗氧化層的方法包括分別在此第—銲罩層所暴敦^ 部分弟一表層線路以及第二銲罩層所暴露的部分第二 線路上電鍍一鎳/金層。 表層 在本發明之一較佳實施例中，在形成此第二介電 ^更包括下列步驟：錢，在第-介電層與第二介2 t別形ί—第—導電層與—第二導電層；之後，在第二 導電層與第二導制上分卿成圖案化的第—抗氧化 圖ί:匕：第二抗氧化層；接著，圖案化此第-導電層：第 i S二表層線路與—第二表層線路 ^ ;1兒層與第—介電層上分別形成一第一銲 t 罩層/其r，此第—銲罩層係覆蓋第一表層i 亚冰路出第一抗氧化層，而此第二銲罩層係覆蓋第二 1250555 16261twf.d〇c/g 表層線路，並暴露出第二抗氧化層。 第之一較佳實施例中，形成此第-抗氧化層盘 玆=1/*法,係分別在第―導電層與第二導電層ΐ 电錢鎳/金層’之後，再圖案 抗氧化層與第二抗氧化層。層㈣成弟- 為，上述或其他目的，本發明又提出—種基板的製作 此it方法包含下列步驟：首先，提供—複合導電層， 由多個金屬層所組成;之後，圖案化此複 ^層—外側之至少—金屬層，以形成多個第一凸塊； 人=於上述帛&塊之間开)成—第一介電層，而此第一 =層係暴露出第-凸塊之頂面；織，圖案化此複合導 ::之另-外侧’以形成多個對應於上述第一凸塊的第二 =塊’接下來’於第—介電層上形成—第二介電層，而此 苐了介電層係暴露上述第二凸塊之頂面，以形成—疊合基 +反，之後，重複上述步驟，以形成至少另一疊合基板；接 著丄於任意兩相鄰的疊合基板之間形成—圖案化線路，且 在最外側的兩疊合基板之外側表面上分別形成一第一導電 層與一第二導電層；最後，將各疊合基板壓合在一起，以 形成一具有多層線路層之基板。 在本發明之一較佳實施例中，基板的製作方法更包括 下列步驟：首先，圖案化此第一導電層與第二導電層，以 在最外侧之兩疊合基板的外侧表面上分別形成一第一表層 線路與一第二表層線路；接著，在最外側的兩疊合基板之 外側表面上分別形成一第一銲罩層與一第二銲罩層，其 12 1250555 16261twf.doc/g 二銲罩層縣露出部分的第—表層祕，而此第 罩層最後，胸 第二鲜罩居戶斤^表層，，泉路上形成—苐一抗氧化層，且在 層。 "暴路的第二表層線路上形成一第二抗氧化 在本韻^明> 第二抗氧切㈣關卜形錢第-抗氧化層與 第一表層線路及第i罩層所暴露的部分 電鑛一錄/金層。 層所恭露的部分第二表層線路上 下列’基板的製作方法更包括 圖案化的第-抗氧化;二導電層上分卿成 圖案化此第—導電層;第:;電層弟層;接著， 基板的外側表面上分八、γ 9 〃在取外側之兩疊合 表層線路；最後，在田^形、第一表層線路與一第二 -第-銲罩層與一第取兩2基板的表面分別形成 蓋第-表層線路，並;; 層係=心暴_= 第二抗氧化層的方法係抗氧化層與 電鑛-鎳/金層，之後 w層與弟二導電層上 -抗氧化層與第二抗氣化層纟錄/金層，即可形成第 由於本發明係利用山 導電塊取代傳統中空的導:1貫心金屬層所叠合而成的 ^通孔’以作林同線路層之間 13 1250555 16261twf.doc/g 電性連接的管道，以解決習知技術中因基板内中" 通孔所造成之可靠度降低的問題。再者，相較於傳統基二 上的導電通孔而言，本發明之導電塊具有較小的尺寸，因 此’將有助於縮小基板的面積及其厚度；且相較於 板上的導電通孔之製作流程而言，本發明之基板的製作^ 純為精間’如此-來，將有助於降低基板之製作成本， 並可提高其生產效率。此外，本發明之基板不僅可作為一 般的核心板來使用，且亦可將多個疊合基板麈合成一具 多層線路層之基板，以擴大其應用範圍。 “為讓本發明之上述和其他目的、特徵和優點能更明顯 易k，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖2½不為本發明之基板的結構剖面圖。請參考圖二， 此基板200係屬於具有雙層線路層之基板，其主要包括介 電層210及位於此介電層21〇中之至少一導電塊22〇。豆 _ 中，介電層210具有相對應的第一表面212及第二表面 214 ;而導電塊220則是配置於介電層21〇内，使介電層 210之第表面212及第二表面214上所形成的線路圖案 可藉由此導電塊220電性連接，其中，導電塊22〇包括第 -凸塊222、第二凸塊224及金屬層挪，金屬層2%係 置於第一凸塊222與第二凸塊224之間。 、 此導電塊22〇之第一凸塊222、金屬層226及第二凸 塊224例如疋由二層金屬層互相疊合而成，其中，第一凸 14 1250555 16261twf.doc/e 塊222及第二凸塊224例如係由銅金屬層所構成，而失置 於二者間之金屬層226可例如係由鎳金屬層所構成。由於 導電塊220係由三層實心的金屬材料所構成，因此，將有 助於提高整個基板200之可靠度。而使用者可依據不同的 使用需求，於基板上之適當位置配置所需的導電塊22〇， 本發明對於導電塊220之數目、形狀及其材質不作任何 限制。 、 請參考圖3A所示，此基板200之第一表面212及第 二表面214上可進一步地配置有第一導電層23〇與第二導 ，層240，此第一導電層230與第二導電層24〇例如是銅 箔(copper foil)層，且第一導電層23〇與第二導電層24〇係 分別連接於第一凸塊222與第二凸塊224，如此一來，苐 一導電層230即可透過導電塊22〇而與第二導電層24〇電 ，連接。值得注意的是，基板2〇〇上之第一導電層23〇與 第二導電層240更可透過微影蝕刻製程將其圖案化，以开; 成圖案化的第—線路層23G，與第二線路層240,，此第-綠 ，層230,與第二線路層24〇,即可作為基板之訊號 此外’請參考圖3B所示，本發明可進一步地於第、 =層230及第二導電層24〇上分別配置一第一焊罩爲 =:址)25()及-第二焊罩層，此第—焊罩層‘ 僅暴鉻出部份的第-導電層23()，同理，此第二焊罩層 2暴露出部份的第二導電層262，以作為基板綱與复 他甩子凡件如晶片、被動元件之間電性連接的媒介。、 15 1250555 1626ltWf.d〇c/g 第3B所示’此基板200上亦可選擇性地配置有- 層25^，層252及一第二抗氧化層262，此第—抗氧化 之麵置於第一详罩層250所暴露的第—導電層23〇 第-^Ϊ 以防止第一導電層23〇及 思 因接觸到空氣而產生氧化的情形。此第一 im52及第二抗氧化層262例如是由—錄/金層所組 ϋ者可依據不同的使用需求，僅於基板細其中-调之表面上依序形成焊罩層及抗氧化層亦可。 使用上反200不僅可作為—般雙層線路層的基板來 作200外侧不製作任何的線路層時，其亦可 於ίΐίίΓ的核心板’因此’上述基板結構將可應用 二有夕層線路層的基板中’以增加基板之可靠度。以下 將；1紹具有多層線路層的基板結構。 幻ΛΓ會ΐ為本發明之基板的結構剖面圖。請參考圖4， 日t 構係與上述雙層線蘭之基板爾請參 二® ^同其不同之處在於：基板300是由多層的 二層$合而成’以形成-具有多層線路層的基 m板300主要包括疊合層3lG、第—表層線路32〇、 弟一表層線路330及多數個導電塊34〇。 ^ 具有相對應的第一表面312及第二表面 314，且係由多個介電層316及導電層3 導電層318係夾置於-知抑认人〜 ^ μ a 、—相郇的介電層316之間。通常在線 路§又计上’導電層318係作為基板之電源平面（P_ 16 1250555 16261twf.doc/g =ane)或接地平面（gr〇undplane)，以作為訊號傳遞時所 需之電源輸入端或接地端；而此第一表層線路32〇及第二 表層線路33〇係分別配置於第一表面312及第二表面314 之上，以作為基板3〇〇之訊號導線。 多個導電塊340係配置於各介電層316内，以導通 一表層線路320、各導電層318及第二表層線路33〇。此 屯^4()包括第一凸塊342、第二凸塊344及金屬層346， ☆至=層346係夾置於第一凸塊342與第二凸塊3料之 估田本所在此不再多作贅述。同樣地， 者可依據不_使用需求，於基板· 形狀及八材貝不作任何的限制。 所以Hi四層線路層之基板是屬於較為常見之基板， 線路声的其把^應用於具有五層或五層以上之 電於疊合層中所包括之介電層及導 兩側的第- i層本:〜::步地於基板細 -第-焊罩層350及表曰線路330上分別配置 僅暴露出部份的第—表層’此第—料層350 與其他電子轉如 ，以料基板300 破動兀件之間電性連接的媒介。 1250555 】6261twfdoc/g 如圖5所示，此基〇 一抗氧化層352 >9 - 擇性地配置有—第 352係配置於第f化層祕，此第-抗氧化層 之上，Μ 罩層350所暴露出的第—表騎心η 之上，而此第二抗氧化層36 表^路320 所暴露出的第二表層線路33〇之上，^弟j罩層柳 320及第二表層線路330因接觸到空氣而層線路 形。此第一抗氧化層352及第二抗展生乳化的情 鎳/金層所組成。使用者可層362例如是由一 立由，《用者了依據不同的使用需求，僅於Α柘 :二之絲上依序形成_及抗氧=^^^ 下將搭配θ〜~不為本發狀基板的製作流程剖面圖，以 方法。。-圖不既明本發明之具有雙層線路層之基板的製作 、—首先，請參照圖6A所示，提供一複合導電層41 複合導電層410是由多個金屬声最人 AA道千仏^ 7 W至/蜀層®合而成，以形成基板中 的h塊。在此實施例中，複合導電層41〇例如是 — 外層金屬層412a、第二外層金屬層412c與中間金屬層似 所組成’其中，中間金屬層仙係夹置於第一外層金屬芦 4Ua與第二外層金屬層412e之間，且第一外層金屬層^ 與第二外層金屬層412c及夾置於二者間的中間金屬層 412b係由不同的金屬材料所組成，如此一來，在後續蝕^ 製程中，此中間金屬層412b即可作為蝕刻阻障層。在本實 施例中，第一外層金屬層412a與第二外層金屬層412c^ 如係由銅金屬層所構成，而失置於二者間的中間金屬層 412b例如係由錄金屬層所構成。 18 1250555 16261twf.doc/g 接著，請參照圖6B所示，利用微影蝕刻技術圖案化 此複合導電層410外侧的第一外層金屬層412a，以形成多 數個弟一凸塊414。之後，如圖6C所示，於各個第一凸塊 414之間形成一第一介電層420,此第一介電層42〇係暴露 出第一凸塊414之頂面。於形成第一介電層42〇的步驟之 後，可進一步地固化(curing)此第一介電層42〇，以增加第 一介電層420之硬度。 然後，請參照圖6D所示，利用微影蝕刻技術圖案化 此複合導電層410另一侧的第二外層金屬層412〇及中間金 屬層412b，以形成多個第二凸塊416。每個第二凸塊416 係分別對應於第一凸塊414其中之一，而中間金屬層41% 係配置於第一凸塊414與第二凸塊416之間，以形成導電 塊418。最後，請參照圖6E所示，於第一介電層42〇上^ 在各第二凸塊416之間形成一第二介電層43〇，此第二介 電層430係暴露出各第二凸塊416之頂面，如此一來，^ 完成基板400之製作流程。同樣地，於形成第二介電層43〇 • 的步驟之後，可進一步地固化此第二介電層430，以增加 第二介電層430之硬度。 曰 本發明之基板可利用多種不同的方式製作而成，以下 將搭配圖示說明本發明之具有雙層線路層之基板的另一種 製作方法。圖7A〜7E繪示為另—種製作基板的製作流 面圖。此製作方法大致上是與圖6A〜6E中戶斤示之基板_ 作方法雷同，而其不同之處在於：此製作方法在形成第^ 凸塊414日夺，係_掉複合導電層410中的第—外層金屬 19 1250555 16261twf.doc/g 層412a與中間金屬層412b，以形成第一凸塊414。 首先，請參照圖7A所示，提供一複合導電層410，此 複合導電層410例如是由第一外層金屬層412a、第二外層 金屬層412c與中間金屬層412b所組成。接著，請參照圖 7B所示，利用微影蝕刻技術圖案化此複合導電層41〇外侧 的第一外層金屬層412a與中間金屬層412b，以形成多數 個第一凸塊414。之後，如圖7C所示，於各個第一凸塊 414之間形成第一介電層42〇,此第一介電層42〇係暴露出 各第一凸塊414之頂面。同樣地，於形成第一介電層42〇 之後，可進一步地固化(curing)此第一介電層42〇，以增加 第一介電層420之硬度。 ^後，請參照圖7D所示，利用微影侧技術圖案化 此複合導電層410另-側的第二外層金屬層412e，以形成 多數個第二凸塊416，每個第-凸塊414、第二凸塊416 =置=者_中間金屬層即形成—導電塊418。 取後關7E所示’於第一介電層42。上且在 ϋ 416 Ϊ間形成第二介電層430，此第二介電層430 係暴路出各第二凸塊416之頂面，如此—也 曰 勸的製作流程。同樣地，於形成第奸板 之後’可進-步地固化此第二介電層Π 電層430之硬度。 以^加弟—介 而在70成上述基板之製作流程後，更 方式於基板兩_表面形成表層線路下列兩種 層’以使基板成為具有雙騎路層之基板Θ ^抗氧化 20 1250555 16261twf.doc/g ,\ 乃几甘丞版4υϋ的外圍保留所兩夕+辦 線’之後，再利用電鑛的方式於表層 二c 圖8A〜8C緣示為在基板上預先保留下電錄線=几乳化層。 表面上依序形成表層線路、痒罩層及抗氧化制 剖面圖。首先，請參照圖S 日之衣作/,丨L耘 於第一介電層420斑第-入丨用微影银刻技術， 成圖案化的第-表層表面上分別形 為基板彻之訊號導沒，^與主弟一表層線路450，以作 塊與第二表層:路 介電Γ43，Λ=Γ成Γ:价 470,其中，此第_鋒 =，460與第二銲罩層 路_，而第二鲜罩H 出部分的第一表層線 ㈣，以作為基板4〇〇曰縫=部分的第二表層線路 間電性連接的科。二/好元件如^、被動元件之 _所暴露之第4^跋如圖％所示，於第一薛罩層 462,並且在第二路物上形成一第一抗氧化層 上形成一第二尸^干¥ 70所暴露出的第二表層線路450 第二表層線：:二匕:=二猶止第-表層線路44〇 ^ 實施例中，此第—^接^工氣而產生氧化的情形。在本 成方式，可例如在462與第二抗氧化層472之形 440以及第二*曰1 ’干罩層460所暴露之第一表層線路 鑛一錄/金層—，、:开^4!0所暴露之第二表層線路450上電 472。使用者可片始成弟一抗氧化層462與第二抗氧化層 了依據不同的使用需求，僅於基板400其中— 21 1250555 16261twf.doc/g 側之=依序形成焊罩層及抗氧化層亦可。 焊罩層及抗氧 =9,層及抗氧化 “、、圖9A所示，在第一介電層伽 ，印 分卿成第一導電層與第二導電層伽f上 9B所示，於第—導電層48〇與第曰90 如圖 圖案化的第-抗氧化層462，與时別形成 Μ思中’形成此第—抗氧化層啦，鱼第才 :=二方; 刻f程目金層，之後，再彻微祕 y衣扭圖案化此鎳/金層，即可 與第二抗氧化層472,。 成此弟一抗氧化層偏， 麵之t請參照圖9C所示’圖案化此第-導電層480 第::==〇’二於基板400兩側的表面上分別形成 可利14弟—表層線路45G。在本實施例中， 層HtfL術圖案化此第—導電層480與第二導電 •I人帝二明奸、圖9C所不’於第—介電層420與第 ,工/心出弟抗乳化層462,，同樣地，此第二 、干a 70係覆盍第二表層線路45〇，並暴露出第二抗氧 22 1250555 16261twf.doc/g 化層472’，如此一來，即可完成基板400兩側之表層線路、 焊罩層及抗氧化層之製作。 在完成具有雙層線路層之基板的製作流程後，本發明 尚可藉由壓合多個疊合基板，以形成圖5中所示之具有多 層線路層的基板300。圖i〇A〜10G繪示為本發明之基板的 製作流程剖面圖，以下將搭配圖示說明本發明之具有多層 線路層的基板之製作方法。 首先，如圖10A所示，提供一複合導電層41〇，此複 合導電層410是由多個金屬層疊合而成。其中，中間金屬 層412e與配置於其兩侧之外層金屬層412(1與41^係由不 同之材質所組成，如此一來，在後續蝕刻製程中，此中間 金屬層412e即可作為蝕刻阻障層。在本實施例中，外層金 屬層412d與412f例如係由銅金屬層所構成，而夾置於二 者間的中間金屬層412e例如係由鎳金屬層所構成。 接著，凊苓照圖10B所示，圖案化此複合導電層41〇 外側之至少一金屬層412,以形成多數個第一凸塊414。在 • 1施例1，本發明僅先圖案化此外層金屬層412d，以形 ^夕數個第一凸塊414 ;然而，在此步驟中，本發明亦可 ，由圖，化此外層金屬層412d與中間金屬層412e，形成 夕^個第-凸塊414，這兩種方式同樣皆可製作出導電塊 的結構:之後，如圖10C所示，於各個第一凸塊414之間 形成第一介電層420，此第一介電層42〇係暴露出第一 凸塊414之頂面。 然後，凊苓照圖10D所示，圖案化此複合導電層41〇 23 1250555 16261twf.doc/g 另一側的外層金屬層412f及中間金屬層4l2e，以形成多 個第二凸塊416，每個第二凸塊416係分別對應於一第一 凸塊414，且每一個第一凸塊414與第二凸塊416係構成 $黾塊418。之後，請參照圖log所示，於第一介電居 420上且在各苐一凸塊416之間形成一第二介電層430,此 第二介電層430係暴露出各第二凸塊416之頂面，如此一 來’即完成單一疊合基板400,之製作流程。 接下來，如圖10F所示，重覆圖1〇A到圖1〇E之步驟， 齡以形成至少另一疊合基板400,。在本實施例中，係以三個 疊合基板400’組合成一基板為例以作說明，當然，使用者 亦可依據不同的使用需求，而將二個、四個或是四個以上 的疊合基板400’進行疊合，以組合成所需的基板。之後， 請參照圖10G所示，於任意兩相鄰的疊合基板4〇〇，之間形 成一圖案化線路500，並且在最外側之兩疊合基板4〇〇，的 外側表面上分別形成一第一導電層48〇與一第二導電層 490。在此實施例中，此圖案化線路5〇〇是分別形成於最外 , 側的兩疊合基板400’之内側表面上。最後，請參考圖1〇(} 所示，將這些疊合基板400,彼此對準且疊合好之後將其壓 合，以形成具有多層線路層之基板3〇〇,。此基板3〇〇,中各 個不同的線路層之間係透過各個導電塊418而電性連接。 在70成上述基板的製作流程後，本發明更可利用下列 兩種方式於基板兩側的表面形成表層線路、焊罩層及抗氧 化層，使外界訊號可藉由基板之表層線路而輸入此基板内。 第-種方式是預先在基板300,的外圍保留所需之電鍛 24 1250555 16261twf.doc/g 線’之後’再利用電鑛的方式於表層線路 圖11A〜11C繪示為在基板上預| 7成抗氧化層。 之表面上依序職層^以於基板 程剖面圖。 9抗乳化層之製作流 首先，請參照圖ΠΑ所示，利用 第一導電層_與第二導電層_，技術圖案化 基板働，之外側表面上分卿成—第一表K側的兩疊合 第二表層線路45〇，此第—表層線路物===與-450係作為基板3〇〇，之訊號導線，且、一表層線路 透過導電塊418與第二表層線路450電性遠^線路440係 ，請參照圖^所示，於最外側的兩.__， 二外：：面上分別形成第一銲罩層46 '基二： _ ’其中’此第-銲罩層46〇係暴露出部分^ , 路440,而第二鲜罩層47〇係暴露出部 弟，線 450，以作為基板4〇〇與其他 5弟一表層線路 間電性連接的婵介。曰$ & m 牛σ日日片、被動元件之 疋侵日1琛；丨。取後，如圖uc所示， 460所暴露之第一表層線路物上形成—=Γί"罩層 462 ’並且在第二輝罩層柳所暴露出的第 ^乳化層 上形成-第二抗氧化層仍，以防止第—表層，、泉路45〇 第二表層線路45〇因接、5、、表路440及 實施例中，此第工*產生氧化的情形。在本 作方式’可例如在第i罩層460所暴露之第製 鑛一錄/金層，以1/層線路450上電 乂成弟一抗乳化層462與第二抗氧化層 25 1250555 16261twf.doc/g 二。使用者可依據不同的使用需求，僅於基板，其中 一則之表面上依序形成焊罩層及抗氧化層亦可。 ” 谭罩種於基板雇’兩側之表面上形成表層線路、 電鍍^ =匕層的方式’則是不需在基板300,周圍保留 12Α〜12ΓΑ樣可以在表層線路上形成抗氧化層。圖 上护杰矣Ϊ不為另一種在圖1〇G中所示之基板300,的表面 首先，^、、泉路、焊罩層及抗氧化層之製作流程剖面圖。 圖12A所示，在第—導電層與第二導電 第二抗氧成圖案化的第一抗氧化層462,與圖案化的 462,血第二於\72。在本實施例中，形成此第一抗氧化層 與第丄導層472,的方式’可例如於第一導電層_ 後，再利用^上以電鍵的方式分別形成一鎳/金層，之 -抗氧化層二】製$圖案化此鎳/金層’即可形成此第 / θ奶2與弟二抗氧化層472,。 與第電^圖、12B:斤示’圖案化此第-導電層480 表面上分別^ 一 ^於取外側的兩疊合基板_，之外側 450。在本實表層線路物與第二表層線路 電層480 ^第心可利賴職刻技術_化此第-導 在最外側^了^層柳。最後’請參照圖政所示， 銲罩層卿基板W的外側表面上分卿成一第一 係覆蓋第-銲罩層47G，，其中，此第—銲罩層, 同樣地，此，亚暴露出第—抗氧化層462,， 暴露出第-^ 層470’係覆蓋第二表層線路450，並 抗乳化層❿，如此一來，即可完成基板實 26 1250555 16261twf.doc/g 兩侧之表層線路、焊罩層及抗氧化層之製作。 紅上所述，在本發明之基板中，係利用由多個實心金 屬層所疊合而成的導電塊取代傳統中空的導電通孔，以作 為不同線路層之間電性連接的管道，此舉將可有效提升整 個基板的可靠度。再者，相較於傳統的導電通孔而言，: ，明在基板上並不需配置有著陸墊，且其導電塊並^像導 電通孔—樣有最小尺相_，因此，將有助於縮小基板 =面積及其厚度；且相較於傳絲板上的導電通孔之製作 流程而言，本發明之基板的製作流程較為精簡，如此一來， 將有助於降低基板之製作成本，並可提高其生產效率。此 外，本發明之基板不僅可作為一般的核心板來使用， 可將多個疊合基板壓合成-具有多層線路層之基板 大其應用範圍。 $ 雖然本發明已以較佳實施例揭露如秋 限定本發明，任何熟習此技藝者，在不脫離;發== 和範圍内，當可作些許之更動與潤飾，因此本發明之保謹 範圍當視後附之申請專利範圍所界定者為準。 、& 【圖式簡單說明】 ~ 圖ία〜m繪示分麟習知之基板上 作流程剖面圖。 ％、札之衣 圖2繪示為本發明之基板的結構剖面圖。 圖3A繪示為在基板兩侧之表面上分別配置一導電声 之剖面圖。 曰 圖3B繪示為在基板兩側之表面上分別配置一導電 27The knives of the knife are a surface layer, and the second solder mask layer exposes part of the surface line; finally, a --anti-oxidation layer is formed on a portion of the first:-line exposed by the first solder mask layer, and A second anti-oxidation layer is formed on a portion of the second surface layer of the second layer. . A method of forming a second anti-oxidation layer in a preferred embodiment of the present invention includes separately on a portion of the second line on which the first layer of the solder mask layer is exposed and the second solder mask layer is exposed Electroplating a nickel/gold layer. In a preferred embodiment of the present invention, the forming of the second dielectric includes the following steps: money, in the first dielectric layer and the second dielectric layer - the first conductive layer and the first a second conductive layer; thereafter, a patterned first anti-oxidation layer on the second conductive layer and the second conductive layer: a second anti-oxidation layer; then, the first conductive layer is patterned: i S second surface line and - second surface line ^; 1 layer and the first dielectric layer respectively form a first solder mask layer / r, the first - solder mask layer covers the first surface layer i A first oxidation resistant layer is formed, and the second solder mask layer covers the second 1250555 16261 twf.d〇c/g surface line and exposes the second oxidation resistant layer. In a first preferred embodiment, the first anti-oxidation layer is formed, and the pattern is anti-oxidation after the first conductive layer and the second conductive layer ΐelectric nickel/gold layer respectively. a layer and a second antioxidant layer. Layer (4) Chengdi - For the above or other purposes, the present invention further proposes the fabrication of a substrate. The method comprises the steps of: firstly, providing a composite conductive layer composed of a plurality of metal layers; thereafter, patterning the complex ^ layer - at least the outer side - a metal layer to form a plurality of first bumps; a person = between the above 帛 & blocks) into a first dielectric layer, and the first = layer system exposes the first - a top surface of the bump; weaving, patterning the composite conductor: the other-outer side to form a plurality of second = blocks corresponding to the first bumps, and then forming on the first dielectric layer - a dielectric layer, wherein the dielectric layer exposes a top surface of the second bump to form a stacking layer + a reverse layer, and then repeating the above steps to form at least one other stacked substrate; Forming a patterned line between any two adjacent stacked substrates, and forming a first conductive layer and a second conductive layer on the outer side surfaces of the outermost two stacked substrates; finally, each stacked substrate Pressed together to form a substrate having a plurality of wiring layers. In a preferred embodiment of the present invention, the method for fabricating the substrate further comprises the steps of: first, patterning the first conductive layer and the second conductive layer to form on the outer surfaces of the outermost two stacked substrates, respectively. a first surface layer and a second surface layer; then, a first solder mask layer and a second solder mask layer are respectively formed on the outer side surfaces of the outermost two stacked substrates, 12 1250555 16261 twf.doc/g The second weld cap layer exposes part of the surface-layer secret, and at the end of the second cover layer, the second fresh cover of the chest is the surface layer of the household, and the anti-oxidation layer is formed on the spring road, and is in the layer. "The second surface line of the typhoon road forms a second anti-oxidation in this rhyme ^ Ming > second anti-oxidation cut (four) Guan Bu-mo-the first anti-oxidation layer and the first surface layer and the i-th cover layer exposed Part of the electricity mine recorded / gold layer. The following method for fabricating the second surface line of the layer is further including a patterned first-anti-oxidation; the second conductive layer is patterned to form the first conductive layer; the first layer; the electrical layer; Then, the outer surface of the substrate is divided into eight, γ 9 〃 is taken on the outer two superposed surface lines; finally, in the field shape, the first surface layer and a second-first welding layer and a second two The surface of the substrate is respectively formed with a cap-surface layer, and; layer system = heart storm _= the second anti-oxidation layer is an anti-oxidation layer and an electro-mineral-nickel/gold layer, and then the w layer and the second layer are on the conductive layer - an anti-oxidation layer and a second anti-gasification layer, a gold layer, can be formed. The present invention utilizes a mountain conductive block to replace a conventional hollow guide: a through-hole of a cross-section of a metal layer. The pipeline is electrically connected to the 13 1250555 16261 twf.doc/g between the forest and the circuit layer to solve the problem of the reliability reduction caused by the through hole in the substrate in the prior art. Furthermore, the conductive block of the present invention has a smaller size than the conductive via on the conventional base 2, so 'will help to reduce the area of the substrate and its thickness; and compared to the conductive on the board. In terms of the manufacturing process of the through hole, the fabrication of the substrate of the present invention is purely the same, which will help to reduce the manufacturing cost of the substrate and improve the production efficiency. In addition, the substrate of the present invention can be used not only as a general core board but also as a substrate of a plurality of wiring layers by a plurality of laminated substrates to expand the range of applications. The above and other objects, features and advantages of the present invention will become more apparent and appreciated. Referring to FIG. 2, the substrate 200 is a substrate having a double-layer circuit layer, and mainly includes a dielectric layer 210 and at least one conductive block 22〇 located in the dielectric layer 21〇. The dielectric layer 210 has a corresponding first surface 212 and a second surface 214. The conductive block 220 is disposed in the dielectric layer 21, and the first surface 212 and the second surface 214 of the dielectric layer 210. The circuit pattern formed thereon can be electrically connected by the conductive block 220, wherein the conductive block 22 includes the first bump 222, the second bump 224 and the metal layer, and the metal layer 2% is placed on the first bump Between the block 222 and the second bump 224, the first bump 222, the metal layer 226, and the second bump 224 of the conductive block 22 are formed by laminating two metal layers, for example, The bump 14 1250555 16261twf.doc/e block 222 and the second bump 224 are, for example, composed of a copper metal layer. The metal layer 226 that is lost between them may be composed, for example, of a nickel metal layer. Since the conductive block 220 is composed of three layers of solid metal material, it will contribute to improving the reliability of the entire substrate 200. The user can configure the required conductive blocks 22 适当 at appropriate positions on the substrate according to different usage requirements. The present invention does not impose any limitation on the number, shape and material of the conductive blocks 220. Please refer to FIG. 3A. The first surface 212 and the second surface 214 of the substrate 200 may be further disposed with a first conductive layer 23 and a second conductive layer 240. The first conductive layer 230 and the second conductive layer 24 are, for example, copper foil. (copper foil) layer, and the first conductive layer 23 and the second conductive layer 24 are respectively connected to the first bump 222 and the second bump 224, so that the conductive layer 230 can pass through the conductive block 22〇 is electrically connected to the second conductive layer 24. It is noted that the first conductive layer 23〇 and the second conductive layer 240 on the substrate 2 are further patterned by a photolithography process to Open; patterned first-line layer 23G, and second The road layer 240, the first green layer, the second layer, and the second circuit layer 24, can be used as the signal of the substrate. Further, please refer to FIG. 3B, the present invention can further be applied to the first layer, the second layer 230 and the second layer. A first solder mask is disposed on the conductive layer 24, and the second solder mask layer is a second solder mask layer. The first solder mask layer is only etched out of the first conductive layer 23 (). Similarly, the second solder mask layer 2 exposes a portion of the second conductive layer 262 as a medium for electrical connection between the substrate and the other components such as the wafer and the passive component. 15 1250555 1626ltWf. D〇c/g shown in FIG. 3B 'This substrate 200 may also be selectively provided with a layer 25, a layer 252 and a second oxidation resistant layer 262, the first anti-oxidation surface being placed in the first detailed mask The first conductive layer 23 exposed by the layer 250 prevents the first conductive layer 23 from being oxidized by contact with air. The first im52 and the second anti-oxidation layer 262 can be formed, for example, by a combination of a recording/gold layer, and the solder mask layer and the anti-oxidation layer are sequentially formed only on the surface of the substrate which is finely adjusted according to different usage requirements. Also. The use of the upper reverse 200 can be used not only as a substrate of a double-layer circuit layer but also as a circuit layer on the outside of the 200. It can also be used in an ίΐίί core core board. Therefore, the above substrate structure can be applied to the second eve layer. 'In the substrate' to increase the reliability of the substrate. Hereinafter, a substrate structure having a multilayer wiring layer will be described. The illusion will be a structural sectional view of the substrate of the present invention. Referring to FIG. 4, the Japanese t-structure is different from the above-mentioned double-layered blue-based substrate. The substrate 300 is formed by a plurality of layers of two layers to form a multi-layer circuit layer. The base m board 300 mainly includes a laminated layer 31G, a first-surface line 32A, a front-surface line 330, and a plurality of conductive blocks 34A. Having a corresponding first surface 312 and a second surface 314, and the plurality of dielectric layers 316 and the conductive layer 3 conductive layer 318 are sandwiched between the 知 认 〜 ^ ^ ^ μ a Between the electrical layers 316. Usually, the wiring layer § is used as the power plane (P_ 16 1250555 16261twf.doc/g = ane) or ground plane (gr〇undplane) of the substrate as the power input required for signal transmission or The first surface line 32 and the second surface line 33 are respectively disposed on the first surface 312 and the second surface 314 to serve as the signal wires of the substrate 3 . A plurality of conductive blocks 340 are disposed in each of the dielectric layers 316 to turn on a surface line 320, conductive layers 318, and second surface lines 33A. The 屯^4() includes a first bump 342, a second bump 344, and a metal layer 346, and the layer 346 is sandwiched between the first bump 342 and the second bump 3 No more details are given. Similarly, the substrate, the shape, and the eight-shell are not subject to any restrictions depending on the requirements of use. Therefore, the substrate of the Hi four-layer circuit layer is a relatively common substrate, and the sound of the circuit is applied to the dielectric layer and the two sides of the conductive layer included in the laminated layer having five or more layers. The i-layer: ~:: step on the substrate fine-first-welding layer 350 and the surface line 330 respectively, respectively, the exposed portion of the first surface layer - the first layer - 350 and other electrons The substrate 300 breaks the medium electrically connected between the components. 1250555 】6261twfdoc/g As shown in FIG. 5, the primary anti-oxidation layer 352 > 9 - is selectively disposed - the 352th system is disposed on the f-layer, above the first anti-oxidation layer, The cover layer 350 is exposed on the first table riding center η, and the second oxidation resistant layer 36 is formed on the second surface line 33〇 exposed by the surface 320, and the second layer of the cover layer 320 and the first layer The second surface line 330 is layered in shape due to exposure to air. The first anti-oxidation layer 352 and the second anti-extrusion emulsified nickel/gold layer are composed. The user-posable layer 362 is, for example, a stand-up. "The user has to form _ and the anti-oxygen = ^^^ will be matched according to different usage requirements, only on the silk of the second wire. A cross-sectional view of the production process of the hair-form substrate, by method. . - The figure does not clarify the fabrication of the substrate having the double-layer circuit layer of the present invention. First, as shown in FIG. 6A, a composite conductive layer 41 is provided. The composite conductive layer 410 is composed of a plurality of metal sound most AA roads. ^ 7 W to / 蜀 layer® are combined to form the h block in the substrate. In this embodiment, the composite conductive layer 41 is, for example, an outer metal layer 412a, a second outer metal layer 412c and an intermediate metal layer formed therein, wherein the intermediate metal layer is sandwiched between the first outer metal 4Ua and Between the second outer metal layers 412e, and the first outer metal layer and the second outer metal layer 412c and the intermediate metal layer 412b interposed therebetween are composed of different metal materials, so that In the etching process, the intermediate metal layer 412b can serve as an etch barrier layer. In the present embodiment, the first outer metal layer 412a and the second outer metal layer 412c are formed of a copper metal layer, and the intermediate metal layer 412b between the two is formed, for example, by a metal layer. 18 1250555 16261twf.doc/g Next, referring to FIG. 6B, the first outer metal layer 412a outside the composite conductive layer 410 is patterned by photolithography to form a plurality of bumps 414. Then, as shown in FIG. 6C, a first dielectric layer 420 is formed between each of the first bumps 414, and the first dielectric layer 42 is exposed to expose the top surface of the first bumps 414. After the step of forming the first dielectric layer 42A, the first dielectric layer 42A may be further cured to increase the hardness of the first dielectric layer 420. Then, referring to FIG. 6D, the second outer metal layer 412 and the intermediate metal layer 412b on the other side of the composite conductive layer 410 are patterned by a photolithography technique to form a plurality of second bumps 416. Each of the second bumps 416 corresponds to one of the first bumps 414, and the intermediate metal layer 41% is disposed between the first bumps 414 and the second bumps 416 to form the conductive bumps 418. Finally, as shown in FIG. 6E, a second dielectric layer 43 is formed between the second bumps 416 on the first dielectric layer 42, and the second dielectric layer 430 is exposed. The top surface of the two bumps 416, in this way, completes the fabrication process of the substrate 400. Similarly, after the step of forming the second dielectric layer 43, the second dielectric layer 430 may be further cured to increase the hardness of the second dielectric layer 430. The substrate of the present invention can be fabricated in a variety of different manners, and another method of fabricating the substrate having the double-layer wiring layer of the present invention will be described below. 7A to 7E are views showing a fabrication flow of another substrate. The manufacturing method is substantially the same as the substrate method shown in FIG. 6A to FIG. 6E, and the difference is that the manufacturing method is formed in the forming of the second bump 414, and is removed from the composite conductive layer 410. The first outer layer metal 19 1250555 16261twf.doc/g layer 412a and the intermediate metal layer 412b form a first bump 414. First, referring to FIG. 7A, a composite conductive layer 410 is provided. The composite conductive layer 410 is composed of, for example, a first outer metal layer 412a, a second outer metal layer 412c, and an intermediate metal layer 412b. Next, referring to FIG. 7B, the first outer metal layer 412a and the intermediate metal layer 412b outside the composite conductive layer 41 are patterned by a photolithography technique to form a plurality of first bumps 414. Thereafter, as shown in FIG. 7C, a first dielectric layer 42 is formed between each of the first bumps 414, and the first dielectric layer 42 is exposed to expose the top surface of each of the first bumps 414. Similarly, after the first dielectric layer 42 is formed, the first dielectric layer 42 is further cured to increase the hardness of the first dielectric layer 420. After that, referring to FIG. 7D, the second outer metal layer 412e on the other side of the composite conductive layer 410 is patterned by the lithography side technique to form a plurality of second bumps 416, each of the first bumps 414. The second bump 416 = set = the intermediate metal layer is formed - the conductive block 418. The first dielectric layer 42 is shown as being turned off 7E. A second dielectric layer 430 is formed over the ϋ 416 ,, and the second dielectric layer 430 is blasted out of the top surface of each of the second bumps 416. Thus, the manufacturing process is also encouraged. Similarly, the hardness of the second dielectric layer 430 can be cured stepwise after the formation of the first board. After the fabrication process of the substrate is 70%, the following two layers of the surface layer are formed on the surface of the substrate to make the substrate into a substrate having a double riding layer. 抗 Antioxidation 20 1250555 16261twf .doc/g , \ is the peripheral retention of the 4 υϋ 丞 丞 两 两 + + 办 办 办 , , , , , , , ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' = several emulsifying layers. The surface line, the itch cover layer and the anti-oxidation profile are sequentially formed on the surface. First, please refer to the clothing of Fig. S, / 丨L耘 in the first dielectric layer 420, the first-in-one lithography technique, and the surface of the patterned first-surface layer is respectively shaped as the signal of the substrate. Guided, ^ and the younger brother a surface line 450, to make the block and the second surface: road dielectric Γ43, Λ = Γ成Γ: price 470, where the first _ front =, 460 and the second welding hood layer road _, and the second fresh cover H out of the portion of the first surface line (four), as the substrate 4 quilting = part of the second surface line electrical connection between the sections. The second/good element such as ^, the passive element is exposed as shown in Figure 4, on the first Xue cover layer 462, and forms a first anti-oxidation layer on the second path to form a first Second corpse ^ dry ¥ 70 exposed second surface line 450 second surface line:: two 匕: = two urgency - surface line 44 〇 ^ In the embodiment, this first ^ ^ ^ ^ ^ ^ ^ The situation. In the present invention, for example, the shape of the first surface layer of the 420 and the second anti-oxidation layer 472 and the second surface layer 460 exposed by the second layer can be recorded/gold layer-, The second surface line 450 exposed by !0 is powered 472. The user can form an anti-oxidation layer 462 and a second anti-oxidation layer according to different use requirements, and only form the solder mask layer and the anti-oxidation layer on the substrate 400 - 21 1250555 16261 twf.doc / g side Layers are also available. The solder mask layer and the anti-oxidation layer, the layer and the anti-oxidation ", as shown in FIG. 9A, are shown in the first dielectric layer, and the first conductive layer and the second conductive layer are shown as 9B on the gamma f. The first conductive layer 48〇 and the 曰90 are patterned as the first anti-oxidation layer 462, and the second layer is formed in the same way to form the first anti-oxidation layer, the fish first:=two squares; After the gold layer, then the nickel/gold layer can be patterned by twisting the yoke, and the second anti-oxidation layer 472 can be formed. The anti-oxidation layer is biased, and the surface t is shown in Fig. 9C. 'patterning the first-conducting layer 480::==〇'2 on the two sides of the substrate 400 respectively form a Kelly 14-surface line 45G. In this embodiment, the layer HtfL is patterned to the first - The conductive layer 480 and the second conductive material are erected, and the second dielectric layer 462 is the same as the first dielectric layer 420, and the second, dry a The 70 series covers the second surface line 45〇, and exposes the second anti-oxidation 22 1250555 16261twf.doc/g layer 472', so that the surface lines, the solder mask layer and the anti-layer on both sides of the substrate 400 can be completed. Oxide layer production After completing the fabrication process of the substrate having the double-layer wiring layer, the present invention can form a substrate 300 having a multilayer wiring layer as shown in FIG. 5 by pressing a plurality of laminated substrates. Fig. i 〇 A 10G A cross-sectional view showing the manufacturing process of the substrate of the present invention, and a method for fabricating the substrate having the multilayer wiring layer of the present invention will be described below with reference to the drawings. First, as shown in FIG. 10A, a composite conductive layer 41 is provided, which is composited. The conductive layer 410 is formed by laminating a plurality of metals, wherein the intermediate metal layer 412e and the outer metal layer 412 disposed on both sides thereof (1 and 41^ are composed of different materials, and thus, are subsequently etched. In the process, the intermediate metal layer 412e can serve as an etch barrier layer. In the present embodiment, the outer metal layers 412d and 412f are formed, for example, of a copper metal layer, and the intermediate metal layer 412e sandwiched therebetween, for example. The nickel metal layer is formed. Next, as shown in FIG. 10B, at least one metal layer 412 outside the composite conductive layer 41 is patterned to form a plurality of first bumps 414. In the embodiment 1 The invention is only patterned first The outer metal layer 412d is shaped into a plurality of first bumps 414; however, in this step, the present invention may also form an outer metal layer 412d and an intermediate metal layer 412e to form a The bumps 414 can also form the structure of the conductive bumps. After that, as shown in FIG. 10C, a first dielectric layer 420 is formed between the first bumps 414. The first dielectric layer 42 is formed. The lanthanide exposes the top surface of the first bump 414. Then, as shown in Fig. 10D, the outer conductive metal layer 412f and the intermediate metal layer on the other side of the composite conductive layer 41〇23 1250555 16261 twf.doc/g are patterned. 4l2e, to form a plurality of second bumps 416, each of the second bumps 416 corresponding to a first bump 414, and each of the first bumps 414 and the second bumps 416 constitute a block 418 . Then, as shown in the figure log, a second dielectric layer 430 is formed on the first dielectric layer 420 and between each of the bumps 416. The second dielectric layer 430 exposes the second bumps. The top surface of block 416, in this way, completes the fabrication process of a single stacked substrate 400. Next, as shown in FIG. 10F, the steps of FIG. 1A to FIG. 1E are repeated to form at least one other superposed substrate 400. In this embodiment, the three stacked substrates 400' are combined into one substrate for illustration. Of course, the user can also combine two, four or more according to different usage requirements. The combined substrate 400' is laminated to form a desired substrate. Thereafter, referring to FIG. 10G, a patterned line 500 is formed between any two adjacent stacked substrates 4A, and is formed on the outer side surfaces of the outermost two stacked substrates 4A, respectively. A first conductive layer 48 is coupled to a second conductive layer 490. In this embodiment, the patterning lines 5 are formed on the inner side surfaces of the outermost and side two stacked substrates 400', respectively. Finally, referring to FIG. 1A, the stacked substrates 400 are aligned and laminated to each other and then pressed to form a substrate 3 having a plurality of wiring layers. The different circuit layers are electrically connected through the respective conductive blocks 418. After 70% of the manufacturing process of the substrate, the present invention can form surface lines and solder on the surfaces on both sides of the substrate by the following two methods. The cover layer and the anti-oxidation layer enable the external signal to be input into the substrate through the surface line of the substrate. The first way is to reserve the required electric forging 24 1250555 16261 twf.doc/g line in advance on the periphery of the substrate 300. After that, the method of reusing the electric ore is shown in FIG. 11A to FIG. 11C as a surface layer of the anti-oxidation layer on the substrate. The surface layer is sequentially formed on the surface of the substrate. First, please refer to FIG. ,, using the first conductive layer _ and the second conductive layer _, the technical patterning substrate 働, the outer surface of the substrate is divided into two superposed second surface lines on the first table K side 45〇, this first-surface line material === and -450 series as the base 3〇〇, the signal wire, and a surface line through the conductive block 418 and the second surface line 450 electrical far ^ line 440 system, please refer to Figure ^, on the outermost two.__, two outside:: The first solder mask layer 46' is formed on the surface respectively. The base 2: _ 'where the first solder mask layer 46 exposes a portion ^, the road 440, and the second fresh cover layer 47 exposes the younger brother, the line 450, as a substrate 4 〇〇 and other 5 brothers and a surface line electrical connection between the 曰 $ & m cattle σ day film, passive components of the invasion of the day 1 琛; 丨. After taking, as shown As shown by uc, the first surface layer exposed on 460 forms a layer of -=Γί" the cover layer 462' and forms a second anti-oxidation layer on the first emulsion layer exposed by the second cladding layer. Preventing the first surface layer, the spring surface 45, the second surface line 45, the connection 5, the surface road 440, and the embodiment, the first work * produces oxidation. In this mode, for example, the i-th cover The first ore-recorded/gold layer exposed by layer 460 is electrically charged on the 1/layer line 450 to form an anti-emulsification layer 462 and a second anti-oxidation layer 25 1250555 16261twf.do c/g 2. The user can only form the solder mask layer and the anti-oxidation layer on the surface of one of the substrates according to different use requirements. The tan cover is formed on the surface of the substrate hired on both sides. The surface layer, the plating method of the ^ 匕 layer is not required to be on the substrate 300, and 12 Α 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 The surface of the substrate 300 shown in the first, the first, the spring, the solder mask layer and the oxidation resistant layer are produced in a cross-sectional view. In Fig. 12A, the first conductive layer and the second conductive second antioxidant are patterned. The first antioxidant layer 462 is patterned with 462 and the blood is second to \72. In this embodiment, the first anti-oxidation layer and the second anti-conductive layer 472 are formed, for example, after the first conductive layer _, and then a nickel/gold layer is formed by using an electric key. - Anti-oxidation layer 2] The pattern of the nickel/gold layer can be formed to form the first / θ milk 2 and the second antioxidant layer 472. The surface of the first conductive layer 480 is patterned on the surface of the first conductive layer 480, and the outer surface 450 is taken out from the surface of the first conductive layer 480. In the real surface layer and the second surface line, the electrical layer 480 ^ The first heart can be used for the technique - this is the first guide - the outermost ^ ^ layer willow. Finally, please refer to the figure, the outer surface of the solder mask layer substrate W is divided into a first layer covering the first solder mask layer 47G, wherein the first solder mask layer, likewise, this, sub-exposure The first anti-oxidation layer 462 is exposed, and the exposed first layer 470' covers the second surface layer 450 and is resistant to the emulsion layer, so that the substrate can be completed on both sides of the substrate 12 1250555 16261 twf.doc/g Fabrication of surface lines, solder mask layers and anti-oxidation layers. In the substrate of the present invention, a conventional conductive via is replaced by a conductive block formed by stacking a plurality of solid metal layers to serve as a conduit for electrical connection between different circuit layers. This will effectively improve the reliability of the entire substrate. Furthermore, compared with the conventional conductive via, :, there is no need to have a land pad on the substrate, and the conductive block and the conductive via hole have the smallest scale phase _, therefore, there will be Helping to reduce the substrate=area and its thickness; and compared with the manufacturing process of the conductive vias on the wire plate, the manufacturing process of the substrate of the invention is relatively simple, which will help reduce the fabrication of the substrate. Cost and increase its production efficiency. Further, the substrate of the present invention can be used not only as a general core plate, but also a plurality of laminated substrates can be laminated - a substrate having a multilayer wiring layer can be used in a wide range of applications. Although the present invention has been disclosed in the preferred embodiments as defined by the following paragraphs, the skilled person skilled in the art will be able to make some modifications and refinements without departing from the scope of the invention. This is subject to the definition of the scope of the patent application. , & [Simple description of the diagram] ~ Fig. ία~m shows the flow profile on the substrate of the branch. %, 衣衣衣 Figure 2 is a cross-sectional view showing the structure of the substrate of the present invention. Fig. 3A is a cross-sectional view showing a conductive sound respectively disposed on the surfaces of both sides of the substrate.曰 FIG. 3B illustrates that a conductive layer is disposed on each surface of both sides of the substrate.
1250555 16261twf.doc/g 圖4繪示為本發明之 圖5终示氣^ 板的結構剖面圖。 焊罩層之剖面圖。1日月之基板的兩側表面上分別配置- 製作目㈣林發明之财雙觀路層之基板的 8A〜種製作基板的製作流程剖面圖。 依序形成表層線路、焊罩層娜^ 上形_7E巾所社基板的表面 之製作流程剖面圖。’、、、x之具有多層線路層的基板 於基二=c依;=2預先保留下繼，以 製作流程邮圖。 層极、料歧抗氧化層之 表面示為另—種在圖1GG中所示之基板的 圖。 、H、焊罩層及抗氧化層之製作流程剖面 【主要元件符號說明】 100 ·基板 102 ·銅箱 104 :貫孔 28 1250555 16261twf.doc/g 1 10 :銅金屬層 110a :圖案化線路層 110b ··圖案化線路層 110c :導電層 120 :雙層線路板 200 :基板 210 :介電層 212 :第一表面 • 214 :第二表面 220 :導電塊 222 :第一凸塊 224 :第二凸塊 226 :金屬層 230 :第一導電層 230’ ：第一線路層 240 :第二導電層 φ 240’ ：第二線路層 250 :第一焊罩層 252 :第一抗氧化層 260 :第二焊罩層 262 :第二抗氧化層 300 :基板 300’ ··基板 310 :疊合層 29 1250555 16261twf.doc/g 312 :第一表面 314 :第二表面 316 :介電層 318 :導電層 320 :第一表層線路 330 :第二表層線路 340 :導電塊 342 ··第一凸塊 • 344 :第二凸塊 346 :金屬層 350 :第一焊罩層 352 :第一抗氧化層 360 :第二焊罩層 362 :第二抗氧化層 400 :基板 400’ ：疊合基板 φ 410 :複合導電層 412a :第一外層金屬層 412b :中間金屬層 412c:第二外層金屬層 412d :外層金屬層 412e :中間金屬層 412f:外層金屬層 414 :第一凸塊 30 I25〇555wf,oc/g 416 ··第二凸塊 418 :導電塊 420 :第一介電層 430 :第二介電層 440 :第一表層線路 450 :第二表層線路 460 :第一焊罩層 460’ ：第一焊罩層 • 462 :第一抗氧化層 462’ ：第一抗氧化層 470 ··第二焊罩層 470’ ：第二焊罩層 472 :第二抗氧化層 472’ ：第二抗氧化層 480 :第一導電層 490 :第二導電層 ▲ 500 :圖案化線路 311250555 16261twf.doc/g Figure 4 is a cross-sectional view showing the structure of the final gas plate of Figure 5 of the present invention. A cross-sectional view of the weld cap layer. On the both sides of the substrate of the first day of the month, a cross-sectional view of the production process of the substrate of the 8A to the substrate for the production of the substrate of the invention. A process flow cross-sectional view of the surface of the substrate of the surface layer and the surface layer of the welding layer is formed in sequence. The substrate having the multi-layer wiring layer of ',, and x is subordinated to the base 2 = c; and = 2 is reserved in advance to make a flow map. The surface of the layer and the anti-oxidation layer is shown as another diagram of the substrate shown in Figure 1GG. , H, welding cap layer and anti-oxidation layer production process profile [main component symbol description] 100 · substrate 102 · copper box 104 : through hole 28 1250555 16261twf.doc / g 1 10 : copper metal layer 110a : patterned circuit layer 110b · patterned circuit layer 110c: conductive layer 120: double-layer circuit board 200: substrate 210: dielectric layer 212: first surface • 214: second surface 220: conductive block 222: first bump 224: second Bump 226: metal layer 230: first conductive layer 230': first wiring layer 240: second conductive layer φ 240': second wiring layer 250: first solder mask layer 252: first anti-oxidation layer 260: Second solder mask layer 262: second anti-oxidation layer 300: substrate 300' · substrate 310: laminated layer 29 1250555 16261twf.doc / g 312: first surface 314: second surface 316: dielectric layer 318: conductive layer 320: first surface layer line 330: second surface layer line 340: conductive block 342 · first bump 344: second bump 346: metal layer 350: first solder mask layer 352: first oxidation resistant layer 360: Second solder mask layer 362: second anti-oxidation layer 400: substrate 400': laminated substrate φ 410: composite conductive layer 412a: first outer Metal layer 412b: intermediate metal layer 412c: second outer metal layer 412d: outer metal layer 412e: intermediate metal layer 412f: outer metal layer 414: first bump 30 I25〇555wf, oc/g 416 ··second bump 418: conductive block 420: first dielectric layer 430: second dielectric layer 440: first surface layer 450: second surface layer 460: first solder mask layer 460': first solder mask layer • 462: first Antioxidant layer 462': first oxidation resistant layer 470 · second solder mask layer 470': second solder mask layer 472: second oxidation resistant layer 472': second anti-oxidation layer 480: first conductive layer 490: Second conductive layer ▲ 500 : patterned line 31