TWI244744B - Flat package for circuit components having soldered metallic contact terminal blocks with lateral surface and process of fabricating the same - Google Patents

Abstract

A leadless flat package for a circuit component for applications including high power rating is disclosed. The power-rating flat-type package comprises a flat-type package body and at least two contact terminals. The flat-type package body comprises a seal hermetically sealing at least a circuit die of the circuit component. The at least two contact terminals are each electrically connected to a corresponding circuit node of the at least one circuit die, among which at least one terminal is to the corresponding circuit node of the circuit die by a metallic conductor via soldering. Each of said contact terminals comprises a horizontal soldering surface exposed out of the soldering side of the package body and a lateral surface exposed out of the package body that is vertical to said soldering surface. The horizontal surface and the lateral surface of each contact terminal are suitable for soldering to a corresponding circuit pad on a printed circuit board to which the leadless flat package circuit component is being assembled. Each of the contact terminals is formed by shaping a single piece of electrically conductive material.

Description

1244744 V. Description of the invention (1) [Technical Field] The present invention relates generally to a package of circuit components, and more particularly to a method suitable for low-cost and high-efficiency automated mass production with good conductive properties. Contact terminals have good heat dissipation properties and are suitable for flat package of high power circuit components. [Previous technology] Active and passive circuit components such as diodes, transistors, resistors, and capacitors are widely used in electronic circuits. Circuit components. Regardless of the small signal (si gna!) Or high power (p 〇we r) use, linear (1 丨 near) or digital (digita 1) nature of the circuit, need to be applied to these discrete circuit of different properties element. In addition to diodes, resistors and electric valleys integrated in integrated circuits, diodes in the form of discrete components, electricity and capacitors, are electronic components that are used in large quantities. There are many types of packaging for discrete circuit components. Based on the demand for miniaturization, surface-mount technology (SMT) type discrete components have gradually become circuit components required for miniaturized electronic devices. Mass production at a high rate at a low cost is necessary to make such discrete circuit components.

1244744 V. Description of the invention (2) The electrical contact terminals of SMT discrete circuit components use the actual area of the contact terminals to eat tin, and the components themselves are soldered to the printed circuit board. SMT components do not have electrical contact terminals that are convexly inserted into the holes of the printed circuit board. Therefore, it is necessary to rely on a large enough soldering area to be able to firmly solder the components to the position of the printed circuit board and have a good Electrical contact quality, especially for high power applications. However, although the soldering surface of the electrical contact terminal of the SM T type discrete circuit element of the conventional technology has a sufficiently large area, the electrical connection path of the electrical contact terminal corresponding to the internal crystal grains does not have the best Conductive properties. For example, this internal electrical connection path of some conventional components is curved and elongated. Although the impedance characteristics of its conductive path are adequate for small signal applications, it is not suitable for high power applications. If it is used in high-power applications, its overall component volume must be proportionally enlarged to meet the high-power and high-current requirements. [Summary of the Invention] Therefore, the object of the present invention is to provide a flat-chip package with a side contact surface welding of a circuit element and a manufacturing method thereof, which can be suitable for the automated mass production of electrical contact terminals with good conductivity and heat dissipation properties. Suitable for high power circuit components. In order to achieve the foregoing object, the present invention provides a flat chip type package of a circuit element with a side contact welding and no lead pins, which includes a flat chip type package body and at least two electrical contact terminals. Flat chip package body contains water vapor seal

1244744 V. Description of the invention (: 3) The packing material encapsulates at least one circuit element die of the circuit element in an air-tight manner. The electrical contact terminals are respectively electrically connected to corresponding circuit nodes of the at least one circuit element die, one of which is to electrically solder a circuit node of the die to its corresponding electrical contact terminal with a metal conductor; Each of these electrical contact terminals includes a horizontal solder surface exposed on the outer surface of the soldering surface of the package body, and a side contact surface exposed on the outer surface of the package body and substantially perpendicular to the soldering surface. And the horizontal solder surface and the side contact surface can solder the electrical contact terminal to a corresponding circuit pad of a printed circuit board to assemble the package on the printed circuit board. Each of these electrical contact terminals is made of a single conductive material. The invention also provides a method for fabricating a circuit element on a substrate made of a conductive material with a side contact surface and a non-lead flat-chip package. The matrix has a plurality of element crystals formed on a grain surface of the substrate. Grain-surface conductive lines, each of the grain-surface conductive lines includes a first conductive segment and a second conductive segment that are physically independent from each other; the steps of the manufacturing method include: (a) on the grain surface An element die is set on the first conductive segment of the grain conductive circuit, and the first electrode of the die is electrically connected to the first conductive segment of the grain conductive circuit, and the second The electrode is electrically connected to the second conductive segment of the grain conductive line, one of which is to electrically solder a circuit node of the grain to its corresponding electrical contact terminal with a metal conductor; (b) is electrically insulated The material water completely and air-tightly covers the element crystal grains and all the conductive lines on the crystal grain surface of the substrate; (c) the soldering surface of the substrate opposing the crystal grain surface is substantially located on the first surface; Position between the first and second conductive segments Etching which can etch reaches the first and second conductive

Page 9 1244744 V. Description of the invention u :) Depth of electrical separation between each other: (d) On the soldering surface, it is substantially located at the electrical connection between each two adjacent circuit elements of the first and second conductive Etching is performed at the positions between the segments to a depth that can electrically separate the connected first and second conductive segments from each other, and respectively form respective side interfaces of the two connected first and second conductive segments; And (e) cutting the water-air-sealed substrate to divide all the element dies into individual discrete circuit elements. [Embodiment] Fig. 1 shows a perspective view of a crystal grain surface of a substrate of a circuit element of a preferred embodiment of a flat-chip package of a circuit element of the present invention. As shown in the figure, the substrate 100 ′, which typically has hundreds of discrete circuit elements arranged to support the entire matrix arrangement, has a plurality of pairs of discrete circuit elements on the surface of the grain surface 110 of the initial conductive line 1. 1 1 A, 1 1 1 B, 1 1 2A, 1 1 2B, ... and 1 1 6 A, 1 1 6 B, etc. are arranged in a two-dimensional orthogonal matrix as shown in the figure . The approximate range of each element in the matrix is indicated by a dashed line. For example, the range indicated by the dashed line range 1 2 3 includes two adjacent conductive lines 1 1 3A and 1 13B. Although there are 113 conductive lines, the initial process of this process The stage is still electrically connected with the conductive line 1 1 2 B of the adjacent element 1 2 2. The dotted line in the figure roughly indicates the relative boundary position between the two. Note that the substrate 100 itself, in the early stages of this process, was also used as the base carrier sheet for a large number of circuit elements produced in batches according to the present invention.

1244744 V. Description of the invention (5) The substrate shown in FIG. 1 serves as the basis of the discrete circuit element of the present invention. The entire substrate is a plate with good electrical conductivity, which can be formed, for example, from a copper sheet. Plate. All conductive lines on the substrate 100 shown in FIG. 1 can be made by using technology such as development etching (photolithography). FIG. 2 is a partial enlarged view of FIG. 1, which shows the grain surface of the substrate. Details of the configuration of the initial conductive line. In Figures 1 and 2, each rectangular area surrounded by a dashed line, as before, represents the physical extent of a discrete circuit element. For example, as shown in FIG. 2, the range indicated by the dashed line 1 2 4 is the physical range of a complete discrete circuit component of the present invention. Among them, at the approximate center of the range 1 2 4, as indicated by the dashed area 1 5 4 The position is the position where the element die will be positioned. Note that as shown in the perspective view of FIG. 2, the asymmetrical pattern of the conductive circuit along the long axis direction (horizontal direction in the figure) on the substrate 100 grain surface 110 of the substrate. According to a preferred embodiment of the discrete circuit component of the present invention, the conductive circuit is within the component footprint range 122 of a component of another component shown in FIG. 2 along the short axis direction (vertical direction in the figure). The conductive lines 1 1 2A and 1 1 2B are substantially symmetrical in shape. However, as can be understood by those skilled in the art, non-symmetric conductive line patterns are also feasible. The conductive lines 1 12A and 1 12B are essentially two conductive patterns that are physically independent of each other. Each of the conductive lines 112A and 112B has a conductive line segment extending toward the center of the element. One of the two conductive lines faces the center of the component, that is, the fixed positioning of the component die extends, and the other conductive line is not

Page 11 1244744 V. Description of the invention (, 6) Extends to the center by a considerable extent so that the two entities do not contact each other. In the embodiment shown in FIG. 2, the conductive line 1 1 2 A on the right is a conductive line segment that extends more toward the center of the element. However, as will be understood by those skilled in the art, it is also possible to arrange the conductive line on the left to reach the center of the component. After the conductive circuit matrix in FIG. 2 is formed by using a process such as last name engraving, the metal surface of each conductive circuit can be processed by various processes such as electroplating to form an oxidation-resistant surface layer, which is beneficial to co-existence with component grains in subsequent process steps. Gold (eutectic) and / or soldering treatment, and is also more suitable for the use of materials such as epoxy resin for sealing mold processing of component grains. In a preferred embodiment of the present invention, the metal suitable for the plating treatment includes nickel, gold and the like. Fig. 3 is a cross-sectional view of the substrates of Figs. 1 and 2, which are cross-sectional views taken along the major axis directions of the conductive lines 113A, 113B, 114A, and 114B in Figs. Note that the cross-sectional view of FIG. 3 shows that all the conductive lines on the substrate 100 and its grain plane 110 are made of a single conductive sheet such as copper. Then, the die of the discrete circuit element can be set in the position shown in FIG. 3. For example, within the range of one of the component units 1 2 4 in the figure, a component die will be positioned at position 1 5 4. The cross-sectional view of FIG. 4 shows that the crystal grains 4 1 4 of a discrete circuit element are set on the crystal grain surface 1 1 0 of the substrate 100. The electrode 'of the element die 414 is electrically connected to the conductive line 1 1 4 A on the die face 110 on the substrate 100. The electrical connection between the die 4 1 4 and the conductive line 1 1 4A can be used, for example

Page 12 1244744 V. Description of the invention ο) '' For example, heating in an electric furnace to melt the solder previously formed on the lower surface of the crystal grains 4 1 4 and / or the positions of the conductive lines 1 5 4 and cool the crystal grains 4 1 4 is welded on the position 1 5 4 of the conductive line 1 1 4 A. For high power requirements, the permanent electrical bonding between the lower surface of the grain 4 1 4 and the conductive line 1 1 4 A may, for example, form a co-gold (e u t e c t i c) in order to withstand the passage of a large current.

When the electrode on the lower surface of the circuit element die 4 1 4 and the conductive line 1 1 4 A on the die face reach a stable electrical connection, the other end of the die 4 1 4, that is, another electrode on the top As shown in FIG. 4, a metal conductor such as a jumper / wire, or preferably, for example, a lead frame 4 3 4 with good conductivity can be used to communicate with the substrate 1 0 0 grain surface 1 1 0 Another conductive line 1 1 4 B on the electrical connection. FIG. 4A is a perspective view showing a structure in which the discrete circuit element dies in FIG. 4 are formed by electrode bonding using a lead frame by soldering. In contrast to lead wires, lead frames are basically thick-plate conductive metals with a set thickness and width. Because it has good electrical conductivity and thermal conductivity due to its relatively large volume, it is very suitable for applications that must handle circuit components with relatively high power. After completing the architecture shown in Figures 4 and 4 A, the electrodes of each component die have been electrically connected to the corresponding solder joints within their respective substrate ranges (component ranges indicated by dashed lines in Figures 1 and 2). On the terminals. at this time,

The electrical structure of each component has been constructed, but the discrete circuit components still arranged in the matrix can be processed for hermetic seal. The cross-sectional view of FIG. 5 shows a case where the crystal grains of the discrete circuit element of FIG. 4 are coated with a water-tight material 50 0. This sealing coating can be performed, for example, by a die casting method. Just use the mold on the substrate

Page 13 1244744 V. Description of the invention (8) A space with an appropriate height is formed above the grain surface 1 1 0, and it can be used, for example, by injecting molten (softened) water and gas sealing material into the space, which can be convenient and convenient. It can be easily made into a water-air-tight package 5 00 to protect the grains 4 1 3, 4 1 4 and the like. After that, as shown in the cross-sectional view of FIG. 6, at this time, the processing of the welding surface of the substrate 100 can be performed. Basically, the soldering surface of the substrate 100 can be etched in a controlled manner using lithographic technology, and the conductive material at a specified position on the soldering surface of the substrate is set to a set depth. This controlled engraving process can electrically separate the individual electrodes of the mother-element unit from the conductive lines, that is, as shown in the cross-sectional view of FIG. 6. Taking the circuit element to which the element die 4 1 4 in FIG. 6 belongs as an example, the die 414 which has been protected by the water-vapor sealing layer 5 0 0, the conductive line 11 4A of the bottom electrode and the conductive line of the top electrode thereof 1 1 4 B. After the etching process between the two, as shown in the cross-sectional view of FIG. 6, they can be electrically isolated. Similarly, the controlled etching process in FIG. 6 can also electrically isolate and separate adjacent conductive lines between two adjacent element units. For example, the bottom electrode conductive lines 1 1 4 A and the top electrode conductive lines 1 1 3 B of the grains 4 1 4 and 4 1 3 in the figure have also been electrically isolated. Note that as shown in FIG. 6, at this time, the exposed material between adjacent conductive lines on the soldering surface of the substrate 100 is the packaging material 500. FIG. 7 is a perspective view of the welding surface of the substrate of FIG. 6, which shows the structural details of the welding surface of the substrate 100 in this process stage. Note that the bottom surface 2 1 0 of the substrate 100 is exposed at this time, and the convex electrodes lie above the substantially flat surface of the substrate, which are the element electrodes formed by the aforementioned conductive circuits of each grain. E.g,

Page 14 1244744 V. Description of the Invention (g)-"Wide ~ 51 + The dotted line range 123 contains the element electrodes 123 A and 123B. 2 Next, as shown in the cross-sectional view of FIG. 8, between the electrodes exposed on the surface of the substrate 100 soldering surface 10, an insulating material can be filled at this time. This filling process can supplement the overall mechanical strength of the component. For example, T 'of the two electrodes 124A and 124B of the element die 414 on the soldering surface of the substrate may be filled with an insulating substance 8 I 4. The filling material may be any suitable insulating material, but preferably it is the same material as the user of the package 500. Thereafter, the cross-sectional view of FIG. 8A shows the structure of the substrate of FIG. 8 after further etching processing. The purpose of this further etching is to electrically separate the conductive lines that are still electrically connected between adjacent two components at this time, and form the side contact surfaces of the electrical contact terminals of the components in the future. As shown in the figure, under the appropriate lithographic pattern, a controlled metal etching process is used to remove a part of the conductive metal, and then a side can be formed between the two components to which the grains 4 13 and 414 belong. The edge contact surface etching space 8 4 4, and the edge contact surface etching spaces 8 4 3 and 8 4 5 are respectively formed on the opposite sides of the two components. It is noted that the depth of the etch-etch line today can completely separate the conductive circuit metal layers that are still in electrical communication between two adjacent elements at this time. The exposed metal surfaces of the etching spaces 8 4 3, 8 4 4 and 8 4 5 at each side contact surface are the side contact surfaces of the electrical contact terminals of each individual component. For example, the formation of the side contact surface etching space 8 4 4 forms the element die 4 1 4 and the side contact surface 1 2 4 C of the electrical contact terminal (ie, the conductive line 丨 2 4A) on the right side of the component and the device die. 4 1 3 The side contact surface of the left electrical contact terminal of the component (ie, the conductive line 1 2 3 B) 2 3 D. The metal surface of each electrical contact terminal,

1244744 V. Description of the invention no) Including the bottom surface of each conductive line and the contact surfaces of each side. At this time, it can be performed, for example, chemical plating. If these metal surfaces are plated with a metal layer such as nickel and / or gold, a soldered surface of the individual electrical contact terminals of the separated individual components can be formed. Fig. 8B is a perspective view of the soldering surface of the substrate of Fig. 8A, which shows the exposure of two electrical contact terminals of each component. Taking the components marked by dashed line 1 2 2 as an example, the left electrical contact terminal, that is, the conductive line 1 2 2 A, exposes its bottom surface and its corresponding side connection surface 1 2 2 C.

The substrate structure shown in Figures 8 A and 8 B can now be cut into discrete discrete circuit elements. Note that the cutting between two adjacent elements can be performed by substantially aligning the centerline of the space between the two elements. As shown in Fig. 9, the components 9 1 4 in the cutting diagram must be cut along the cutting lines 9 4 4 and 9 4 5. In addition, as can be understood, along the directions not shown in the figure, which are substantially perpendicular to the cutting lines 9 4 4 and 9 4 5, two cuts must be performed to completely separate the component 9 1 4. FIG. 10 is a cross-sectional view of a flat-chip discrete circuit component package according to the present invention, in which two electrical contact terminals of the component package 914, that is, electrodes 124A and 1 2 4 B each have a recessed side. For example, the outer side wall of the electrode terminal 1 2 4 A has a depression 1 0 2 6, and the inner side wall thereof has a depression 1 0 2 4 and 1 0 2 2, and the electrode

The terminal 1 2 4 B has a recess 1 0 2 7 on its outer side wall, and a recess of 1, 2 5 and 10 2 3 on its inner side wall. The recessed portions on the vertical sidewalls of these electrodes can be achieved by controlling the etching time length when the aforementioned conductive segments are etched. The existence of these recessed areas helps the packaging material to firmly hold the two conductive contact terminals. FIG. 11 shows a circuit according to a preferred embodiment of the present invention.

Page 16 1244744 V. Description of the invention (in 'component flat chip package manufacturing method and cut and separated a circuit component, a single structure of the rear perspective view. Figure 1 2 shows Figure 1 1 component single A perspective view of the soldering surface of the body structure. Figures 1 and 14 show perspective views of the back surface and soldering surface of another circuit element single structure of the present invention. This circuit component can be two types of components as shown in Figures 1 1 and 12 The connection of a single body has four electrical contact terminals. Note that the electrical contact terminals 1311, 1313, etc. of the component 1300 in the figure are similar to the terminals 1 1 1 1 of the component 1100 in FIG. Large-area conductive junctions other than the surface. Figures 15 and 16 show perspective views of the back surface and soldering surface of another circuit element single structure of the present invention, respectively, which can be four types of component elements shown in Figure 11 The body connection has four rows of four electrical contact terminals each. The electrical contact terminals 1511, 1513, etc. of the element 1 500 in the figure are similar to the terminals 1 1 1 1 of the element 1100 in Fig. 11. Figs. 1 to 3 The multiple electrical contact terminal circuit elements shown in 6 Suitable for, for example, integrated active or passive circuit elements such as diodes. On the other hand, FIG. 17 shows a perspective view of a soldering surface of a single structure of another circuit element of the present invention. Three electrical contacts of this circuit element 1700 The terminals 1 7 1 1, 1 7 1 3, and 1 7 1 2 are arranged in an asymmetrical form, and can be applied to the needs of discrete circuit elements such as a transistor that requires three pins. Fig. 1 8 further shows the present invention. A perspective view of the soldering surface of another circuit element with a single structure, which has a plurality of electrical contact terminals arranged on four sides. Note that the circuit element 1 800 in the figure has four electrical contact terminals (1811) on each of its two wider sides. , 1813, 1815 and 1817 and 1812, 1814, 1816 and 1818),

1244744 V. Description of the invention (12) and its narrow sides each have only one electrical contact terminal 1 8 2 1 and 1 8 2 2. Such an electrical contact terminal arrangement of the circuit element 1 800 is equally applicable to, for example, integrated active or passive circuit elements such as a diode or a transistor. In a typical component pin assignment method, the wide-side electrical contact terminal may be a signal pin of a plurality of individual discrete circuit components contained in the component 180, such as the positive and negative pins of a diode. The narrow-side electrical contact terminals can be used for common ground or a common power source or common ground such as common anode or common cathode diode. As can be understood by those skilled in the art, although the circuit element 1 800 in the figure has substantially a single electrical contact terminal on the side of the element on the left and right sides, it can also arrange more than one Electrical contact terminals to suit the needs of different components. Although the foregoing explanatory text is a complete description of a specific embodiment of the present invention, its various modifications, variations, and equivalent applications are still possible. For example, although the detailed description of the foregoing embodiments only uses discrete circuit elements to describe the present invention, as can be understood by those skilled in the art, under the SMT type, various sizes of EIA standard chips are discrete. Diodes, such as Zener, Schott ky, etc., or discrete capacitors, whether polarized or not, or discrete resistors, or even the nature of active or integrated circuits, regardless of whether a dual electrical connector or more than a dual electrical connector is required The circuit components of the connector are all applicable to the manufacturing method disclosed in the present invention. In addition, the present invention is not only applicable to the common 1310, 1206, 0805, and SOD 3 2 3, SOD 5 2 3 and other SMT E I A standard chip sizes, and it is particularly suitable for smaller SMT discrete circuit elements. For another example, this

1244744 V. Description of the invention (13) The conductive lines on the welding surface of the board may be further covered with a nickel layer or a gold layer. In addition, although the application of high power is emphasized in the explanatory text of the present invention, as can be understood by those skilled in the art, the flat chip package of the present invention can also be applied to non-high power applications such as signal components. . Therefore, the foregoing description should not be used to limit the present invention, and its scope should be defined by the text of section B of the scope of patent application attached later.

Page 19 1244744 Brief Description of Drawings Figure 1 shows a perspective view of a crystal grain surface of a substrate of a circuit element of a preferred embodiment of a flat-chip package for making a circuit element of the present invention. Fig. 2 is a partially enlarged view of Fig. 1 showing the details of the configuration of the initial conductive circuit on the substrate grain plane. FIG. 3 is a cross-sectional view of the substrate of FIG. 1. The cross-sectional view of Fig. 4 shows that a discrete circuit element die is positioned on the die face of the substrate 'and forms an electrical connection of the element electrodes. FIG. 4A is a perspective view showing a structure in which the discrete circuit element die in FIG. 4 is formed by electrode bonding using a lead frame by soldering. The cross-sectional view of FIG. 5 shows that the discrete circuit element of FIG. 4 is covered with a water-tight material. The cross-sectional view of FIG. 6 shows the structure after the soldering surface of the substrate of FIG. 5 is etched. FIG. 7 is a perspective view of a soldering surface of the substrate of FIG. 6. The cross-sectional view of FIG. 8 shows the structure after the soldering surface of the substrate of FIG. 6 is filled with an insulating material. The cross-sectional view of FIG. 8A shows the structure of the substrate of FIG. 8 after further #etching processing. FIG. 8B is a perspective view of a soldering surface of the substrate of FIG. 8A. The cross-sectional view of FIG. 9 shows the substrate structure of FIG. 8 cut into discrete discrete circuit elements. Fig. 10 is a cross-sectional view of a flat-chip discrete circuit component package according to the present invention, in which recessed sides of two electrical contact terminals are shown. FIG. 11 shows the manufacturing and cutting according to a preferred embodiment of the present invention.

1244744 Schematic illustration A perspective view of the back of a single component with a single structure. FIG. 12 shows a perspective view of a soldering surface of the element structure of FIG. 11. Figures 13 and 14 show perspective views of the back surface and the soldering surface of another circuit element single structure of the present invention, respectively, which have four electrical contact terminals. Figures 15 and 16 show perspective views of the back surface and the soldering surface of another circuit element single structure of the present invention, respectively, which have four rows of four electrical contact terminals each. Fig. 17 shows a perspective view of a soldering surface of a single circuit element structure of the present invention. FIG. 18 shows a perspective view of a soldering surface of another circuit element single structure of the present invention, which has a plurality of electrical contact terminals arranged on four sides.

Page 21

Claims (1)

Ϊ244744 Bu Shi 1 Zhiri Xiu (poly) original rte mouth eight people--· 1 〆 .-: f '· * ---- I Case No. B: 7 2 6. The scope of the patent application I. A flat chip package with side f soldered metal block electrical contacts, which includes: contact, sub-circuit element, flat chip package body Contains at least one circuit element that encapsulates the circuit element with water and airtightness: at least two electrical contact terminals that are water and airtight, and are respectively electrically connected to the corresponding circuit node of the two-way component die, one of them to ° H to V — one of the electrical grains of the circuit node is electrically welded to a pair of j M metal conductors. Each of these electrical contact terminals includes-water contact contacts-on the outer surface of each individual welding surface, and exposed. ^, The outer surface of the package body exposed on the package and substantially perpendicular to the soldering surface and the side contact surface can make the electrical contact, and the corresponding wiring material of the β-horizontal solder board is The = on the printed circuit ... the electrical contact terminals are in the shape of a printed circuit board. Made from early conductive material β 2 · As the lightning failure of item 1 of the patent application range-from u to, where the at least one thunder & day 1 circuit is a flat chip type sealed circuit element It is a diode crystal. 3. If the lightning failure of item 1 of the patent application range is from u, the flat plate type seal of the at least one Thunderbolt θI circuit 7L piece is a crystal grain. 4. If the lightning failure -π u 1 package of the first patent application scope, wherein the at least one circuit element crystal is a circuit circuit ^^ flat chip seal Page 1 2005. 05. 27. 022 1244744 6. Scope of patent application 5 · If the circuit element # 1 of the patent scope of the application is cleared, where at least-Lei Yuanyuan 侔 said private film \ road piece of flat film The 7G pieces of the die-closing circuit are the resistance grain soil seals. 6 As the circuit element package of the first item in the patent scope of Shenyan, the at least _circuit element grains are the chips of the flat-chip sealing circuit component. . There are active and flat pieces of flat piece type and a flat piece that encloses the circuit. The two electrical corresponding circuit node electrical terminals each include an external surface that is perpendicular to the welding surface. The pad can be used to connect the various types of contacts The side contact surface is welded with a metal block package, which includes: a contact terminal circuit_ type package body, which contains a circuit element die of one of the water-air-sealed components; and a if, water-air-tight if terminal, which is electrically The ground is connected to the point, and one of them is to connect the crystal rice to the corresponding electrical contact material with a metal conductor; each one of the: and is exposed outside the package body = :. "One side of the connection surface; the horizontal shell." The electrical contact terminals are welded to the printed circuit. Front side: Γ; ίΓPrinted circuit board :::: Made from a conductive material. 8. A kind of matrix multiple element crystal grain guides are formed on the grain surface of a flat block-type package connection panel of a metal block-shaped electrical contact terminal circuit element made on a conductive material substrate; 1244744 correction said Six, apply for a special--------- one or more of these grain plane conductive lines each include a body independent of each other = a first conductive segment and a second conductive segment; the manufacturing method steps Including (a) determining the element grain on the first conductive segment of the grain conductive circuit of the grain plane, and electrically connecting the first electrode of the grain to the first conductive segment of the grain conductive circuit And electrically connect the second electrode of the element die to the second conductive segment of the die conductive line, one of which is to electrically weld a circuit node of the die to its corresponding electric conductor with a metal conductor Contact terminals; (b) the substrate is completely water-tightly covered with an electrically insulating substance The element grains on the grain plane and all of the conductive lines; (c) the soldering plane of the substrate opposing the grain plane is substantially located between the first and second conductive segments Etching, which etches to a depth where the first and second conductive segments can be electrically separated from each other; (d) on the welding surface, which is located substantially at every two adjacent electrical connections between the first and second The position between the conductive segments is electrically connected to each other so that the connected first and second conductive segments are electrically separated from each other; it reaches the depth of the two connected first and second conductive segments, and (E) Cutting the water-air-sealed substrate and dividing it into individual discrete circuit components by grains. The crystal electrical contact terminals 2 of these components include a horizontal solder surface. Each of these ―On the external surfaces of the soldering surfaces, and exposed on the package ^ $ the package body is substantially perpendicular to the soldering surface ― the side edge is connected to the external surface of the body and J244744 Case No. 9¾ ^ 94- ·? Year and month Amendment VI. Patent application scope 9. If the method of patent application scope item 8 is used, after this step (c), it includes a step of filling the insulating substance in the etching place. . 10. The method according to item 8 of the patent application, wherein the circuit element crystal grains are diode crystal grains. 11. The method according to item 8 of the patent application, wherein the crystal grains of the circuit element are transistor crystal grains. 12. The method according to item 8 of the patent application, wherein the circuit element crystal grains are capacitor crystal grains. 13. The method according to item 8 of the patent application, wherein the circuit element grains are resistance grains. 14. The method according to item 8 of the patent application, wherein the circuit element die is a die including active and passive circuit components. Page 4 2005.05.27.025