1238517 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體元件之製作方法，且特別是有關於一 種能與低壓元件相容之高壓元件半導體製程。 【先前技術】 如該行業者所知，將高壓元件與低壓元件，如高/低壓金氧半 導體⑽s)電晶體，同時整合製狀频電雜術乃胃知技藝。例 如，使用低壓元件來製造控制電路，使用高壓元件來製作可電程 ^^tili^||(Electrically Programmable Read-Only-Memory ^ EPROM)或者是液晶顯示器的驅動電路等等。 -般為了秋高壓錄半導體電晶體元件触通道效應，主要 是利用形成元件隔離結構來使源極/汲極和閘極之間的距離增 加而達到降低通運内橫向電場之目的。如此，金氧半導體電晶 體元件即使在高操作電壓（如3〇v至的操作下，仍能正常運 作。 目前高屢元件和低壓元件相容之半導體製程中，其低壓元件仍 1238517 多採用G. 5至0· 6微米之製程製作。為提高元件積集度，同時使 高壓元件能相容於更低之低難作(如3· 3似符合運算速度 更快之需求，财必要導人(U5微米町之製程來製造低壓元件。 除了製程複雜度增加之外，若以習知40V高壓元件製程搭配 3. 3V低壓元件製程尚具有下列幾點缺失，而猶待進一步改進： ⑴習知高壓元件製程，皆是在錢化销定義主動區域之 後才進行高壓N型井(High-Voltage N WeU，刪〇以及高壓p型 ^(High-Voltage P Well . HVPW)a^(p〇st^implant)^^^ 長，然後高溫驅入，待高溫驅入完成後，必須再除去植入後氧化 層。如此，造成後續成長之場氧化層（Field 〇xide，F〇x)嚴重侵 蝕氮化矽層底部，此底侵（encroachment)現象將導致低壓元件之 主動區長度及寬度不易控制，以致嚴重影響低壓元件之操作特性。 (2) 習知高壓元件製程，漸層摻雜區（gra(ie regi〇ns)驅入 為必須之步驟。但驅入前氧化層成長以及驅入後之氧化層去除將 造成場氧化層（FOX)邊緣薄化(edge thinning)，進而導致低壓元 件操作時產生嚴重之扭結效應（kink effect)。 (3) 習知高壓元件製程，將高壓N型場佈植區與高壓p型場 佈植區的植入步驟在場氧化層形成之前進行，這些用作為通道中 斷(channe 1 stop)之場佈植區隨後繼續接受高溫之漸層摻雜區 (grade regions)驅入，如此，造成植入離子橫向擴散較遠。 1238517 ⑷先前技藝中，為顧及低顯_元件__多晶石夕間 極係分別以不同光罩分開較義並_，然而如此卻容易在高、 低[7L件之乂界處存有多晶石夕_殘留物，影響到產品之良率。 【發明内容】 有鑑於此，本發明之主要目的在提供一種相容於更低操作壓 (如3〜4V)T〇件之高壓(3〇〜術)元件製程，並解決前述習知技藝之 問題。 為達前述目的，根據本發明之較佳實施例，本發明提供一種製 作具有向壓元件與低壓元件積體電路之方法，應用於一基底上， 该基底至少包含一高壓元件區以及一低壓元件區，且基底表面包 括一第一墊氧化層，該方法包含有： 進行一第一離子佈植製程，於該高壓元件區之該基底内形成一 第一電性第一井區； 進行一苐二離子佈植製程，於該高壓元件區之該基底内形成一 笫二電性第二井區； 去除該第一墊氧化層； 於該基底表面形成一第二墊氧化層； 於5亥弟一墊氧化層上沈積一罩幕層； 1238517 暴路出部分之該第二墊氧化 於該罩幕層中形成複數個開口 層； 進行一第三離子佈植製程，植 植弟电性離子於該高壓元件區 亥弟二電性第二井區中，形成第-漂流擴散層； 進行一第四離子佈植製裎，M 曰 她植人，料贿低壓元件 區，以於該低壓元件區内形成—第—電性第三井區； 進行一第五離子佈植製程，棺楚— 植入第一電性離子於該低壓元件 區，以於該低壓元件區_成_第二雜第四井區； 進行-第六離子佈植製程’植人第二紐離子於該祕元件區 之該第一電性第—井區中，形成第二漂流擴散層； 進订氧化仏，在未被該罩幕層紐之該複數個開口形成複數 個牟件隔離結構； 去除該罩幕層以及該第二墊氧化層； 於該基底上形成一第一閘極氧化層； 進行第七與第八離子佈植製程，將第一電性離子以及第二電性 離子穿透該元件_結構，分雌人該第二電性第二井區以及該 第-電性第-井區’於高壓元件區軸複數個第—通道中斷 區； 進灯第九離子佈植製程，於該低壓元件區之該第二電性第四井 區形成第二通道中斷摻雜區； 進灯第九離子佈植製程，於該低壓元件區之該第二電性第四井 1238517 區形成第一電性反穿潰(APT)摻雜，· 去除該低壓元件區之該第一閘極氧化層； 於該低壓元件區形成第二閘極氧化層；以及 於該基底上形成複數個閘極。 為了使f審查委員能更近一步瞭解本發明之特徵及技術内 容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與_制用，麟絲對本㈣純限制者。 【實施方式】 本《明係提供-種製作具有高壓元件與低壓元件積體電路之 新半導體製财法’可建構包含有可於_(gate)端及汲極 (drain)端均於3〇〜撕高電壓下操作之高壓廳元件，以及相容 -於閘極端與祕端均於3〜4V低賴下操狀憾元件，其 中該高壓MOS元件與該低壓職元件之閘極氧化層的厚度分別介 於700 900埃以及5〇〜70埃之間。本發明之高壓M〇s元件製程特 職用於以場氧化層廳為主結構，具有在場氧化層下方之漂流 擴政層（drift layer)。本發明之低壓職元件則以LDD型M〇s結 構為主。 10 1238517 請茶閱第1圖至第18目，其緣示的是本發明較佳實施例一種 製作具有縫元件與低航件積體電路之方法的剖面示意圖。首 先，如第i圖所示，提供-半導體基底1〇，例如p型石夕基底。半 導體基底10至少分為-高壓元件區域11〇以及—低塵元件區域 120在问壓几件區域11〇内預計製作形成複數個高廢電晶體 元件’而在低壓元件區域120 _預計形成複數個低塵廳電晶 體元件。在形成塾氧化層12之後，以第零層對準方式，在高壓元 件區域m内利用光阻14(又稱為「高麼N井光阻層」或圖中所示 之麵W PHOTO」）疋義出面壓元件區域11〇内預計植入n型井之 開口 15。進行N型離子佈植製程，將N型推f經由光阻14之開口 15植入半導體基底10’在高屢元件區域11〇内形成n型井心产 後，藉由高溫熱製程來進行N型井16驅入，以及去除光阻14。2 謂「第零層鮮方式」私,_戦在_道上·底層溝準對 準圖案(alig_t _〇麵行倾黃辅之鮮。 如第2圖所示，在高麼元件區域110内利用光阻24(又稱為「含 塵P井光阻層」或圖中所示之「刪麵」）定義_元件= 域11〇内預計植人P型井之開口 25。進行P型離子佈植製 p型摻質經由光阻24之開σ25植入半導體基㈣，在高牛 _削内形成Ρ型井26。隨後，去除光阻％以及墊氧化。 接耆’藉由高溫熱製程來進行井區植人物的驅入。 1238517 ★弟―3 _不’於半導體基底10表面上形成塾氧化層32，隨 4 進仃化學氣相沈積(Chemicai Vapor l)eposlti〇n，CVD)製程， 於墊乳化層32上沈積—厚度約為·埃左右之氮切層. ★第4圖所不’進行黃光以及侧製程，定義出待形成場氧化 層區域，將氮化秒層34定義成具有開口 35a、35b、35c、35d、35e、— 5g之遮罩圖案。開口 35a、35b、35c、、脱、脱及 35g暴路出部分的塾氧化層32，並定義出待形成場氧化層之位置。 在後績製私中，將透過開口 35a、35b、35c、35d、脱、财及咖，籲 於半導體基底10表面上形成場氧化層。 、，如第5圖所示，進行一黃光製程，於半導體基底ι〇上形成— 光阻圖案（又稱為「N漂流擴散層光阻(N DRIFT PHOTO)」）44，其 八有開口 45，暴露出氮化石夕層34之開口 35a。接著，進行一離 子佈植製程，經由開口 45以及開口 35a，並藉由氮化發層％之自 行對準，將N型摻質植入半導體基底1〇之p型井26内形成n型 # 漂流擴散層52。隨後，再進行歸紗活倾μ型漂流擴散層 52内的摻質。 如第6圖所示，再進行一黃光製程，於半導體基底1〇上形成 、 一光阻圖案（又稱為「低壓N型井區光阻(LVNW PHOTO)」）54，其 具有一開口 55，在低壓元件區域120内預計植入N型井之位置。 12 1238517 妾著進行一 N型離子佈植製程，經由開口 55佈植，於半導體美 底10内形成N型井66。 如第7圖所示，進行另一黃光製程，於半導體基底1〇上形成 光阻圖案（又稱為「低壓P型井區光阻(Lvpw PHOTO)」）74，其 具有一開〇 75，在低壓元件區域120内預計植入p型井之位置。 接著，進行一 P型離子佈植製程，經由開口 75佈植，於半導體基 底ίο内形成p型井76。接著，進行N型井66以及p型井％之高 溫驅入活化製程。 如第8圖所示，進行一黃光製程，於半導體基底10上形成— 光阻圖案（又稱為「P型漂流擴散層光阻(p DRIFT pH〇T〇)」如4， 其具有一開口 85，暴露出氮化矽層34之開口 35d。接著，進行一 離子佈植製程，經由開口 85以及開口 35d，並藉由氮化石夕層料 之自行對準’將p型摻質植入半導體基底1〇之N型井16内形成p 型漂流擴散層56。隨後，去除光阻84。 如第9圖所*，進行場氧化層製程，以氧化方式，經由氣化矽 層 34 之開口 35a、35b、35c、35d、35e、35f 及 35g，於半導體基 底ίο表面上形成厚度約5咖埃之場氧化層95a、95b、95c、咖、 95e 95f及95g。其中’場氧化層95a以及分別形成在n型 13 1238517 漂流擴散層52以及P型漂流擴散層56上。 如第10圖所示，去除氮化石夕層34。然後進行離子佈植製程， 於高壓元件區域110的P型井26以及N型井16内分別形成N型 漸層摻雜區（grade regi〇n)152以及P型漸層摻雜區156，其中 型漸層摻雜區152與N型漂流擴散層52相鄰接，p型漸層播雜區 156與P型漂流擴散層56相鄰接。 、品 如第11圖所示，接著進行一清洗製程，將半導體基底忉表面 上的墊氧化層32以及一定厚度的場氧化層去除。 如第12圖所示’接著，進行熱氧化製程，於半_基底10的 裸露石夕表面上成長高品質的高壓閘極氧化層160，其厚度約為 700〜900 埃。 如第13圖所不，以光阻定義，並以p型離子佈植以及n型離 子佈植分別在高壓το件區域11Q内的p型井26以及N型井形 成p型通道中斷摻雜區182以及N型通道中斷摻㈣186。如該^ 業者所知，P型通道中斷摻雜區182以及N型通道中斷摻雜區186 係1成場氧化層下方。需找，本發明P ^通道巾斷摻雜區⑽ 以及N型通道中斷摻雜區186係在場氧化層形成之後進行，因此 14 1238517 建議採用高能離子佈植， 明p型撕斷摻雜區^及=化層脱及95ί。而由於本發 氡化層形成之後n 係在場1238517 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a high-voltage device semiconductor manufacturing process that is compatible with low-voltage devices. [Prior art] As is known to those in the industry, it is a gastric know-how to integrate high-voltage components and low-voltage components, such as high / low voltage metal-oxide semiconductors) transistors, and integrate preformed frequency electric hybrid technology. For example, a low-voltage component is used to manufacture a control circuit, and a high-voltage component is used to make an electrically programmable ^^ tili ^ || (Electrically Programmable Read-Only-Memory ^ EPROM) or a driving circuit of a liquid crystal display and the like. -In general, in order to achieve the channel effect of high voltage recording semiconductor transistor elements, the formation of the element isolation structure is mainly used to increase the distance between the source / drain and the gate to reduce the lateral electric field in the transportation. In this way, the metal oxide semiconductor transistor device can still operate normally even under high operating voltage (such as 30v to operation). At present, in the semiconductor process compatible with high-voltage components and low-voltage components, its low-voltage components are still 1238517 mostly G .5 to 0.6 micron manufacturing process. In order to improve the component accumulation and make high-voltage components compatible with lower and lower difficulty (such as 3 · 3 seems to meet the need for faster computing speed, it is necessary to guide people (U5 micron manufacturing process to manufacture low-voltage components. In addition to the increased complexity of the process, if the conventional 40V high-voltage component process is matched with the 3.3V low-voltage component process, the following points are still missing, and further improvements are needed: In the process of high-voltage components, high-voltage N-wells (High-Voltage N WeU, deleted 0, and high-voltage P Well. HVPW) a ^ (p〇st ^ implant) ^^^, and then driven at high temperature. After the high-temperature drive is completed, the post-implantation oxide layer must be removed. In this way, the subsequent growth of the field oxide layer (Field 〇xide, F〇x) seriously erodes the nitride 1. the bottom of the silicon layer ment) phenomenon will cause the active area length and width of the low-voltage component to be difficult to control, which will seriously affect the operating characteristics of the low-voltage component. (2) Knowing the process of high-voltage components, the gradually doped region (gra (ie regi0ns)) is driven into A necessary step. However, the growth of the oxide layer before the drive-in and the removal of the oxide layer after the drive-in will cause the field oxide (FOX) edge thinning, which will cause a serious kink effect during the operation of low-voltage components. (3) Knowing the process of high-voltage components, the implantation steps of the high-voltage N-type field implantation area and the high-voltage p-type field implantation area are performed before the field oxide layer is formed, and these are used as the field of channel interruption (channe 1 stop). The implantation area continues to be driven by high-temperature grade regions, which causes the implanted ions to diffuse laterally far away. 1238517 ⑷ In the previous technology, in order to take into account the low display_component__ 多 晶石 夕 间The poles are separated by different photomasks, but it is easy to have polycrystalline stone residues in the high and low [7L pieces of the boundary], which affects the yield of the product. [Contents of the Invention] Yes In view of this, the owner of the present invention The purpose is to provide a high-voltage (30 ~~) technology process that is compatible with lower operating voltage (such as 3 ~ 4V) T0 pieces, and to solve the problems of the aforementioned conventional techniques. In a preferred embodiment, the present invention provides a method for fabricating an integrated circuit having a compressive element and a low-voltage element, which is applied to a substrate, the substrate includes at least a high-voltage element region and a low-voltage element region, and the surface of the substrate includes a first pad An oxide layer, the method includes: performing a first ion implantation process to form a first electrical first well region in the substrate of the high voltage element region; performing a two ion implantation process on the high voltage element A second electric well area is formed in the substrate of the area; the first pad oxide layer is removed; a second pad oxide layer is formed on the surface of the substrate; a mask layer is deposited on the pad oxide layer ; 1238517 The second pad in the part of the storm road is oxidized in the cover layer to form a plurality of opening layers; a third ion implantation process is performed, and the electric ions are implanted in the high voltage component area. In Erjing District, Into the first-drift diffusion layer; perform a fourth ion implantation plutonium, M said that she is planted, and is expected to bridging the low-voltage component area to form a first-electrical third well area in the low-voltage component area; Five ion implantation process, coffin — implant the first electrical ion into the low-voltage component area, so that the low-voltage component area _cheng_ the second hybrid fourth well area; carry out-the sixth ion implantation process' planting people A second button ion forms a second drift diffusion layer in the first electrical first-well region of the secret element region; the erbium oxide is ordered, and a plurality of holes are formed in the plurality of openings that are not connected by the mask layer. Piece isolation structure; removing the mask layer and the second pad oxide layer; forming a first gate oxide layer on the substrate; performing the seventh and eighth ion implantation processes to place the first electrical ions and the second Electrical ions penetrate the element structure, and the female is divided into the second electrical second well area and the -electrical -well area on the axis of the high-voltage component area. An ion implantation process forms a second channel in the second electrical fourth well region of the low-voltage component region. Interrupt the doping region; enter the ninth ion implantation process of the lamp, form a first electrical reverse breakdown (APT) doping in the second electrical fourth well 1238517 region of the low voltage element region, and remove the low voltage element region The first gate oxide layer; forming a second gate oxide layer on the low-voltage element region; and forming a plurality of gate electrodes on the substrate. In order to enable the reviewing committee to further understand the features and technical contents of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are for reference and production only. [Embodiment] This "Provided by the Ming Department-A New Semiconductor Financial Method for Manufacturing Integrated Circuits with High-Voltage Components and Low-Voltage Components" can be constructed to include both the gate and drain terminals at 30%. ~ Tear the high-voltage hall components that operate under high voltage, and are compatible-both the gate extreme and the secret end are operated at a low voltage of 3 ~ 4V. Among them, the high-voltage MOS element and the low-voltage element have gate oxide layers. The thickness is between 700 900 Angstroms and 50 to 70 Angstroms. The high-voltage Mos element manufacturing process of the present invention is specially used for the field oxide layer hall as the main structure and has a drift layer below the field oxide layer. The low-voltage component of the present invention is mainly based on the LDD-type Mos structure. 10 1238517 Please refer to Figures 1 to 18 for the tea. The edge is a schematic cross-sectional view of a method for manufacturing an integrated circuit with a seam element and a low-altitude part according to a preferred embodiment of the present invention. First, as shown in Fig. I, a-semiconductor substrate 10 is provided, such as a p-type stone evening substrate. The semiconductor substrate 10 is at least divided into-a high-voltage element region 11 and-a low-dust element region 120. It is expected that a plurality of high-waste transistor elements will be formed within a few regions 110 and a low-voltage element region 120. Low dust room transistor components. After the erbium oxide layer 12 is formed, a photoresist 14 is used in the high-voltage element region m in a zero-level alignment method (also referred to as "high N-well photoresist layer" or the surface W PHOTO shown in the figure). The n-well opening 15 is expected to be implanted in the area of the surface pressure element 11. The N-type ion implantation process is performed. The N-type pusher f is implanted into the semiconductor substrate 10 ′ through the opening 15 of the photoresist 14. After the n-type core is formed in the high-repetition element region 11, it is performed by a high-temperature thermal process. The N-type well 16 is driven in, and the photoresist is removed 14. 2 It is referred to as the "zero-level freshness method", and the _ on the _ road and the bottom trench aligning pattern (alig_t _〇 surface is lined with yellow auxiliary. As shown in Figure 2 As shown in the figure, the photoresist 24 (also called "dust-containing P-well photoresist layer" or "cut surface" shown in the figure) is used in the high-element area 110 to define the _component = P type in the field 11 The opening 25 of the well. P-type ion implantation of p-type dopants was implanted into the semiconductor substrate through the opening σ25 of the photoresist 24 to form a P-type well 26 in the high-cut silicon. Subsequently, the% photoresist and pad oxidation were removed. . Then, the high-temperature thermal process is used to drive the planting characters in the well area. 1238517 ★ brother ―3 _NO 'forms a plutonium oxide layer 32 on the surface of the semiconductor substrate 10, and then proceeds to chemical vapor deposition (Chemicai) Vapor l) eposltin, CVD) process, deposited on the pad emulsified layer 32-a nitrogen-cut layer with a thickness of about Angstroms. And a process side, define the field oxide region to be formed, the nitride is defined to have an opening 35a, 35b, 35c, 35d, 35e, second layer 34 - 5g of the mask pattern. The openings 35a, 35b, 35c, and 35g of the plutonium oxide layer 32 at the outflow portion define the position where the field oxide layer is to be formed. In the post-production system, a field oxide layer is formed on the surface of the semiconductor substrate 10 through the openings 35a, 35b, 35c, 35d, detachment, wealth, and coffee. As shown in FIG. 5, a yellow light process is performed to form a photoresist pattern (also called “N DRIFT PHOTO”) 44 on a semiconductor substrate ι, which has openings. 45. The opening 35a of the nitrided stone layer 34 is exposed. Next, an ion implantation process is performed, through the opening 45 and the opening 35a, and by self-alignment of the nitrided layer%, an N-type dopant is implanted into the p-type well 26 of the semiconductor substrate 10 to form an n-type # Rafting diffusion layer 52. Subsequently, the dopant in the spinning-returning and tilting μ-type drift diffusion layer 52 is performed. As shown in FIG. 6, a yellow light process is further performed to form a photoresist pattern (also referred to as “low-voltage N-well photoresist (LVNW PHOTO)”) 54 on the semiconductor substrate 10, which has an opening. 55. The location where the N-type well is to be implanted in the low-voltage component area 120. 12 1238517 An N-type ion implantation process is carried out, and an implantation is performed through the opening 55 to form an N-type well 66 in the semiconductor substrate 10. As shown in FIG. 7, another yellow light process is performed to form a photoresist pattern (also referred to as “low-voltage P-type well area photoresist (Lvpw PHOTO)”) 74 on the semiconductor substrate 10, which has an opening of 75 The position where the p-type well is to be implanted in the low-voltage component region 120. Next, a P-type ion implantation process is performed, and implantation is performed through the opening 75 to form a p-type well 76 in the semiconductor substrate. Next, a high temperature drive activation process for N-type wells 66 and p-type wells is performed. As shown in FIG. 8, a yellow light process is performed to form a photoresist pattern on the semiconductor substrate 10 (also referred to as “P-type drift diffusion layer photoresist (p DRIFT pH〇T〇)” such as 4, which has a The opening 85 exposes the opening 35d of the silicon nitride layer 34. Next, an ion implantation process is performed, through the opening 85 and the opening 35d, and the p-type dopant is implanted by self-alignment of the nitride nitride layer material A p-type drift diffusion layer 56 is formed in the N-type well 16 of the semiconductor substrate 10. Then, the photoresist 84 is removed. As shown in FIG. 9 *, a field oxide process is performed, and the silicon oxide layer 34 is oxidized through the opening of the gasified silicon layer 34. 35a, 35b, 35c, 35d, 35e, 35f, and 35g, forming field oxide layers 95a, 95b, 95c, 95e, 95f, and 95g with a thickness of about 5 cai on the surface of the semiconductor substrate. Among them, the field oxide 95a and They are formed on the n-type 13 1238517 drift diffusion layer 52 and the p-type drift diffusion layer 56. As shown in FIG. 10, the nitride nitride layer 34 is removed. Then, an ion implantation process is performed on the P-type well in the high-voltage element region 110. N-type graded doped regions (26) are formed in N-type wells 26 and 16, respectively. And a P-type gradient doped region 156, in which the type-graded doped region 152 is adjacent to the N-type drift diffusion layer 52, and the p-type gradient doped region 156 is adjacent to the P-type drift diffusion layer 56. As shown in FIG. 11, a cleaning process is then performed to remove the pad oxide layer 32 and the field oxide layer of a certain thickness on the surface of the semiconductor substrate. As shown in FIG. 12 'Next, a thermal oxidation process is performed. A high-quality high-voltage gate oxide layer 160 is grown on the exposed surface of the substrate 10, and its thickness is about 700 to 900 angstroms. As shown in FIG. 13, it is defined by photoresist, and is implanted with p-type ions and n-type. Ion implantation forms p-type channel interruption doped region 182 and N-type channel interruption dopant 186 in p-type well 26 and N-type well in high-voltage το element region 11Q, respectively. As the industry knows, P-type channel interruption doped The region 182 and the N-type channel interruption doped region 186 are below the field oxide layer. It is necessary to find that the P ^ channel interruption doped region ⑽ and the N-type channel interruption doped region 186 of the present invention are performed after the field oxide layer is formed. Therefore, 14 1238517 is recommended to use high-energy ion implantation, p-type tearing doped regions ^ and = Delamination and 95ί. And because of the formation of the present chemical layer n is present
型通道t顏,仃’〜好處在於P m道帽摻雜㈣2以及N 生物⑽㈣溫影響，產 阻件區域則之㈣井光罩，定義光 θ不再以離子佈植製程調整高屢元件區域η〇之臓元 _愿_。隨後以先前定義高遷元件區域110之N型井， “罩定義光阻（圖未不）’再以離子佈植製程調整高遷元件區域· 110之PM0S元件的啟始電壓（y比）。 接著，再以先前定義低壓元件區K12〇iP型井光罩，定義光 阻（圖未示）’再分別以p型及N型離子佈植製程於p型井76植入 P 31通道中斷摻雜區與N型反穿潰(Ant i -Punch-Through，APT)摻 φ 雜 276。 如第14圖所示，以光阻覆蓋高壓元件區域11〇，僅暴露出低壓 元件區域120。進行低壓M0S元件（N/PM0S)之啟始電壓調整之離子 佈植。然後將低壓元件區域120内的閘極氧化層16〇蝕刻去除。 之後’在進入爐管乳化’成長低壓閘極氧化層260，其厚度約為 15 1238517 50〜70埃。 如第15圖所示，接著沈積堆疊之約1500埃之多晶石夕層以及約 腳埃之金屬魏_糊示），再分麻賴元件區域胸 及遞元件區域120的主動區域内將其絲成瞻gs閘極結構 310 320 330 340。接著，進行閘極側壁子的形成、金屬石夕化 層回火以及健元件區域12G _瞒雜汲極(Ughtiy此㈣Type channel t, 仃 ′ ~ The benefit is that the P m channel cap is doped with ㈣ 2 and N. The effect of biological temperature is on the ohmic mask, and the masking area is the mask of the well, which defines the light θ no longer adjusted by the ion implantation process. 〇 之 臓 元 _ 愿 _. Subsequently, using the N-type well previously defined in the high transition element region 110, "the mask defines the photoresist (not shown in the figure) ', and then the ionization process is used to adjust the starting voltage (y ratio) of the PM0S element in the high transition element region 110. Next, the K12iP well mask of the low-voltage component area was previously defined, and the photoresist (not shown) was defined. Then the p-type well 76 was implanted in the p-type well 76 to interrupt the doping with p-type and N-type ion implantation processes. And N-type anti-breakthrough (Ant i-Punch-Through, APT) doped with φ impurity 276. As shown in Figure 14, cover the high-voltage element area 11 with a photoresist, and only expose the low-voltage element area 120. Perform low-voltage MOS Ion implantation of the initial voltage adjustment of the device (N / PM0S). Then, the gate oxide layer 160 in the low-voltage device region 120 is etched away. Then, the low-voltage gate oxide layer 260 is grown 'emulsified in the furnace tube', which The thickness is about 15 1238517 50 ~ 70 angstroms. As shown in FIG. 15, the stacked polycrystalline layer of about 1500 angstroms and the metal foot of the foot angstroms are deposited), and then divided into the malay component area and In the active area of the transmission element area 120, it is wired into a gs gate structure 310 320 330 34 0. Next, the formation of the gate sidewalls, the tempering of the metallization layer, and the 12G area of the active element (Ughtiy this ㈣
Drain，_製程。進行LDD製程時，高壓元件區域ιι〇係以光阻 覆蓋。 如第16圖所示，先接著利用光阻層340錢出高愿元件區域 110内要植入高濃度摻質之開口區域35〇a、35〇b、驗及漏。 然後經由開口區域35Ga、咖b、35Gc及細絲刻暴露出來的 没極及源極上方的氧倾，高魏化層胁紐絲光阻層糊。 如第17圖所示’然後分別再以PVN+光罩定義高低壓MOS元件 植入W辰度N型及p雜質。再進行祕/汲極高溫回火製程。 如第18圖所不，進行介電I 500的沈積，以及後續金屬化製 程。金屬化製程包括金屬接觸插塞6〇2以及導線層，之製作。 由上可A本&明製作具有高壓元件與低壓元件積體電路之方 法至少包括有下列優點： 1238517 1⑴本發明練元件製程，是在錢姆較義主動區域之 月|』，即進行高壓N型井(隨)以及高射型井（刪)植入後 (_t-impiant)氧化層絲，錢再高溫驅人，再除去驅入後之 乳化層。因此，可避免魏化層魏氮化料底部之問題。 ⑵一本發明高壓元件製程，將漸層推雜區(抑如邮·) 入^㈣極氧化層成飼時完成。不需驅人前氧化層成長以 及驅入後之氧化層去除’可避免場氧化層邊緣薄化⑹辟 thmmng)，改善習知低壓元件操作時產生扭結效應㈤故 effect)。 本1明向壓元件製程，將尚壓元件區的N型通道中斷摻 雜區與P型通道中斷摻雜區的植入步驟在場氧化層形成之後進 行因此改善通道中斷摻雜區的植入離子橫向擴散問題。 ⑷本發明高壓元件製程，在晶片上之高、低壓元件區之交 界處不會存有多晶石夕籬琶殘留物，可提高產品之良率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 17 1238517 第1圖至第18圖顯示本發明較佳實施例一種製作具有高壓元 件與低壓元件積體電路之方法的剖面示意圖。 【主要元件符號說明】 10 半導體基底 12 墊氧化層 14 HVNW光阻 15 開口 16 N型井 24 HVPW光阻 25 開口 26 P型井· 32 墊氧化層 34 氮化矽層 35a、 35b、35c、35d、35e、 35f、 35g 開口 44 N型漂流擴散層光阻 45 開口 52 N型漂流擴散層 54 低壓N井光阻 55 開口 56 P型漂流擴散層 66 N型井 74 低壓P井光阻 75 開口 76 P型井 84 P型漂流擴散層光阻 85 開口 95a、 95b、95c、95d、95e、 95f、 95g 場氧化層 110 南壓元件區域 120 低壓元件區域 152 N型漸層摻雜區 156 P型漸層摻雜區Drain, _ process. During the LDD process, the high-voltage component area ιι is covered with a photoresist. As shown in FIG. 16, the photoresist layer 340 is used to first deposit the opening regions 35a, 35b with high concentration of dopants in the high-wish-element region 110, and then inspect and leak. Then, through the opening region 35Ga, Cab, 35Gc, and the filaments exposed by the electrode and the oxygen over the source electrode, the high-wetting layer threatens the wire photoresist layer paste. As shown in FIG. 17 ', the PVN + mask is then used to define the high and low voltage MOS devices and implant W-type N-type and p-type impurities. Then perform the secret / drain high temperature tempering process. As shown in Figure 18, the dielectric I 500 is deposited and the subsequent metallization process is performed. The metallization process includes the production of a metal contact plug 602 and a wire layer. The method of making integrated circuits with high-voltage components and low-voltage components from the above can at least include the following advantages: 1238517 1⑴The component manufacturing process of the present invention is in the month of the active area of the Cham's meaning | ", that is, high voltage N-type wells (with) and high-firing type wells (deletion) are implanted with (_t-impiant) oxide wire, which is driven at a high temperature, and the emulsified layer after removal is removed. Therefore, the problem of the bottom of the nitrided layer can be avoided. (1) The process of the high-voltage component of the present invention is completed when the gradual doping area (such as a postal) is fed into the anodic oxide layer for feeding. It is not necessary to drive the growth of the front oxide layer and the removal of the oxide layer after the drive-in to prevent thinning of the edge of the field oxide layer (thmmng), and to improve the kink effect caused by the conventional low-voltage component operation). In the present invention, the process of implanting an N-type channel interruption doped region and a P-type channel interruption doped region in a still-pressed element region is performed after the field oxide layer is formed, thereby improving the implantation of the channel interruption doped region. The problem of lateral ion diffusion. ⑷ In the high-voltage component manufacturing process of the present invention, polycrystalline stone fence residues will not be stored at the junction of the high and low-voltage component areas on the wafer, which can improve the yield of the product. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention. [Brief description of the drawings] 17 1238517 Figs. 1 to 18 show cross-sectional schematic diagrams of a method for manufacturing an integrated circuit having a high-voltage element and a low-voltage element according to a preferred embodiment of the present invention. [Description of main component symbols] 10 semiconductor substrate 12 pad oxide layer 14 HVNW photoresistor 15 opening 16 N-type well 24 HVPW photoresistor 25 opening 26 P-type well 32 pad oxide layer 34 silicon nitride layer 35a, 35b, 35c, 35d , 35e, 35f, 35g Opening 44 N-type drift diffusion layer photoresistor 45 Opening 52 N-type drift diffusion layer 54 Low-pressure N-well photoresistor 55 Opening 56 P-type drift diffusion layer 66 N-well 74 Low-pressure P-well photoresistor 75 Opening 76 P-type Well 84 P-type drift diffusion layer photoresist 85 Opening 95a, 95b, 95c, 95d, 95e, 95f, 95g Field oxide layer 110 South pressure element region 120 Low voltage element region 152 N-type gradient doped region 156 P-type gradient doped Miscellaneous area
18 1238517 160 186 276 310、 340 350a 500 604 閘極氧化層 182 P型通道中斷摻雜區 N型通道中斷摻雜區 260 閘極氧化層 N型反穿潰摻雜 320、330、340 閘極結構 光阻層 、350b、350c、350d 開 口區域 介電層 602 金屬接觸插塞18 1238517 160 186 276 310, 340 350a 500 604 Gate oxide layer 182 P-type channel interruption doped region N-type channel interruption doped region 260 Gate oxide layer N-type reverse breakdown doping 320, 330, 340 Gate structure Photoresist layer, 350b, 350c, 350d Open area dielectric layer 602 Metal contact plug
導線層Wire layer
1919