1233724 五、 發明說明（1 ) [ 發 明所屬技術 領域】 本 發明係關於 類比放大器，特別是有 關具有偏 差補償 電 容 功 能的類比放 大器。 [ 習 知技術】 按 ，如眾所 週知，在液晶顯示 元件（LCD : Li qi: lid Cr y s t a 1 D i s p 1 a y )之源極驅動器（s 〇 u r c e drive r)等方 面 廣 泛的使用類 比放大器，而在單一源 極驅動器 晶片上 採 用 對 應輸出個數 之數百個類比放大器。 此 情況下，當 利用半導體製造程序製 造晶片之 情況時 數 百 個類比放大 器將隨工程上的失調（m i i sma t ch ) ，而產 生 分 別 不同的隨機 (r andom )偏差。所以， 即便數百 個類比 放 大 器 全部被賦加 相同的輸入電壓，類比 放大器相 互間亦 姐 j\\\ 法 獲 得相同的輸 出電壓。 所 以，若LCD 面板屬利用具不同的隨 機補償的 類比放 大 器 進 行驅動的話 ，便將導致LCD面板之色彩（co 1 〇 r )品 質 大 幅 降低，所以 類比放大器的補償在電 路上便形 成極其 重 要 的 因素。 第 1圖所示係 通常之類比放大器的符 號，乃具 有在正 輸 入 端 (+ )上賦加輸入電壓（v i η )，而在負 輸入端（ -)則具 有 驅 動 輸出負荷之 類比放大器的輸出電壓 (V 〇 u t )被 回饋的 構 造 〇 第 2圖所示係 第1圖符號所表示之類 比放大器 的電路 圖 ， 乃 由輸入端1 < 3、輸出端20及頻率補 -3- 償用電容 器（C C )所 1233724 五、發明說明（2) 構成。 輸入端1 0係由將輸入電壓（V 1 η )以閘極輸入的電晶體 (Mil)、將回饋輸出信號以閘極進行賦加的電晶體（ΜΙ2)、 屬電晶體（Mil，ΜΙ2)各負載的電晶體（ΜΒ1，ΜΒ2)、·及將偏壓 (V b i a s )以聞極賦加並供給偏壓電流（b i a s c u r r e n t )的電 晶體（Μ I B )所構成。另，輸出端2 0係由在電晶體（Μ I 1 )的 汲極端連接閘極並牽引驅動輸出節點的電晶體（MOD )、與 將該偏壓（Vb 1 a s )以閘極賦加並牽引驅動輸出節點的電晶 體（MOB )所構成。頻率補償用電容器（CC )係形成於電晶體 (MOD )之閘極端與源極端之間。 相關上述構造的動作進行說明。若賦加輸入電壓（V i η ) 的話，隨電晶體Mil與ΜΙ2之閘極與源極電壓差，流通於 電晶體Mil與電晶體MI2上的電流便將產生差異，藉此變 化電壓而控制電晶體MOD，俾產生輸出電壓（Vout)。 此外，如前述，隨半導體技術上的電晶體Mil、MI2、 MB 1、MB2之程序失調（譬如電晶體寬度與長度之比率、及 各電晶體之臨界電壓値不同）的放大器，本身亦將具有偏 差（〇 f f s e t ) 〇 所以，當LCD源極驅動器晶片屬由數百個類比放大器所 構成之情況時，具相互不同的隨機偏差的類比放大器’便 將驅動LCD面板，導致LCD面板之色彩品質大幅降落的缺 點產生。 【發明欲解決之課題】 1233724 五、 發明說明 ( 3) 本 發 明有 鑑 於上述習知諸項技術問題點缺失 ，其目 的 在 於 提 供 一種 具 偏差補償功能之類比放大器。 [ 解 決 發明 之 手段】 緣 是 ，爲 達 成上述目的，本發明之類比放大 器，其特 徵 在 於 :具備有放大器與偏差補償機構；其中， 該放大 器 係 賦 加於 正輸 入 端的輸入電壓，且將本身之輸出 電壓回 饋 於 負 輸 入 端且 驅 動的放大器；而該偏差補償機構 係具備 有 回 饋 該 放 大器 之 輸出電壓，並將該輸出電壓與該 輸入電 壓 進 行 比 較 ，且 儲 存該放大器偏差値的落差互補電 容器， 將 該 輸 入 電 壓與 該 落差値的差提供予該正輸入端， 並由該 放 大 器 的 輸 出電 壓 去除偏差的偏差補償機構。 [ 發 明 實施 態 樣】 以 下 ，爲 對 本發明予以更具體的說明，請參 閱所附 圖 示 ， 針對相關 本 發明之各種實施例進行詳細說明 〇 (第- -實施例） 第 3 圖所示係相關本發明一實施例之類比放 大器的 方 塊 構 造 圖 〇 請 參 閱第 3 圖所示，相關本發明之類比放大 器，係包括 有 賦 加 於正 輸 入端（+ )的輸入電壓（V i η );將本 身之輸 出 電 壓 回 Atfa m 於負 輸 入端（-)並驅動的放大器1 00 ; 爲將放 大 器. 100 之 輸出 電 壓（Voiit)進行回饋，並比較該輸 出電壓 與 輸 入 電 壓 (Vin )， 而儲存放大器100之偏差値， 再將輸 入 電 壓 (Vin )與偏差値之差提供予正輸入端（+ )，f -5- 由輸出 電 壓 1233724 五、發明說明（4) (Vout)去除偏差的偏差補償部200。 放大器1 00係可由譬如第2圖所示電路及其他多種電路 所構成，且偏差補償部200可獲得多種的實施例。 第4圖所示係第3圖所示本發明類比放大器之偏差補償 部之較佳實施例。 請參閱第4圖所示，偏差互補部2 0 0係由除放大器1 0 0 之外的切換器及電容器所構成。 具體而言，偏差補償部係由形成於屬放大器1 〇〇之正輸 入端（+ )的第一節點（netl)與屬輸入電壓（Vin)端之第三節 點（net3)之間的第一切換器（swi )、放大器10〇之輸出電 壓（Vout )端形成於第二節點（net2)與第四節點（net4)(形 成於第一節點與第二節點間之通路上）之間的第二切換器 (3〜2)、形成於第三節點（11以3)與第四節點（11以4)之間的 第三切換器（sw3)、形成於第二節點與屬放大器1〇〇輸出 端之第二節點（net 2)及輸出負載間之第四切換器（sw4)、 形成於第四節點（ne t 4 )與第一節點（ne t 1 )之間的頻率補償 用電容器（Coc)所構成。 此外，第四切換器（s w4 )係在輸出負載較少，或放大器 以低速動作之情況時，便可省略。再者，各切換器係可採 用通常的NM0S電晶體、PM0S電晶體、或傳導電晶體等。 第 5圖所示係針對第 4圖之各切換器（swl，sw2, sw3，sw4)的 ΟΝ/OFF 關係，模示（mode) pi、模示 Φ 2、模 示#3、及模示形成一週期，並由放大器產生輸出。 1233724 五、發明說明（5) 第6A圖至第6D圖所示係各模式之個別電路圖。 透過第5圖及第6圖，就從第4圖之類比放大器動作及 放大器輸出電壓（Vout)中，去除偏差的過程進行說明。 首先第6A圖所示’當賦加輸入電壓（Vin)時，在將偏差 値儲存於偏差補償電容器（Coc )的過程中，第一與第二切 換器（swl，sw2)將被接通（turn on)，而第三與第四切換器 (sw3，sw4)則位於被斷開（turn off)的模式p 1區間。因爲 第一切換器（swl)被接通，所以若將輸入電壓Vl n賦加於 正輸入端（+ )的話，放大器的輸出電壓Vout便將形成含偏 差値△ V之電壓値的Vin + Δ V。另，因爲第一節點（net 1 ) 電壓爲Vin，而第三節點（net3)電壓則爲Vin + △V，所以 輸入電壓V i η與回饋後的輸出電壓V 1 η + Δ V之比較結果的 偏差値Δν，便儲存於偏差補償電容器（Coe)中。 其次，第6B圖所示係爲確保模示（/) 1與模示p 3間之非 重疊（Ν ο η - 〇 v e 1· 1 a p )定時區間的過程，第一、第二、第三 及第四切換器（swl , sw2 , sw3，sw4)便全部在被斷開的模示 P 2區間。 另，第一、第二切換器（swl, sw2)之斷開時序，與第三 、第四切換器（sw3 , sw4)之斷開時序並未相互重疊，若可 N時接通（Turn on)與斷開（Turn off)的話，便不再需要 此過程。 其次，第6C圖所示係將輸入電壓Vi η與偏差値Δν，提 供予放大器100的正輸入端（ + )，並由輸出電壓Vout去除 1233724 五、發明說明（6) 偏差的過程，第二、第四切換器（s w 3，s w 4 )將被接通，而 第一、第二切換器（s w 1，s W2 )則於被斷開之模示（/) 3的區間 0 因爲弟二切換^(swS)被接通^所以在正輸入v而（+ )上便 被賦加Vm-Δ V，所以放大器的輸出電壓Vout便將由 Vin + AV値輸出Vin値，而使第四切換器被接通，譬如如 LCD面板之類的輸出負載，便形成已去除偏差値的輸出電 壓V 〇 u t進行驅動。 其次，第6D圖所示係爲確保模示¢) 3與模示p 1間之非 重疊（Non-over lap)定時區間的過程，第一、第二、第三 及第四切換器（swl，sw2, sw3，sw4)便全部在被斷開的模示 ¢) 4區間。第三、第四切換器（sw3，sw4)之斷開時序，與第 一、第二切換器（swl，sw2)之接通定時，並未相互重疊， 若可同時接通與斷開的話，便不再需要此過程。 (第二實施例） 第7圖所示係相關本發明另一實施例之類比放大器的方 塊構造圖。 請參閱第7圖所示，相關本發明之類比放大器，係包括 有賦加於正輸入端（+ )的輸入電壓（V 1 η );將本身之輸出電 壓回饋於負輸入端並驅動的放大器100;爲將放大器100 之輸出電壓（Vout)進行回饋，並提供該輸出電壓與輸入電 壓Vin進行比較，而儲存放大器100之偏差値，再將輸 入電壓（V i η )與偏差値之差提供予負輸入端（-)，由放大器 1233724 五、發明說明（7) 100之輸出電壓（Vout)去除偏差的偏差補償部500。 放大器1 00係可由譬如第2圖所示電路及其他多種電路 所構成，且偏差互補部5 0 0可獲得多種的實施例。 第8圖所示係第7圖所示本發明類比放大器之落差互補 部之較佳實施例。 請參閱第8圖所示，偏差互補部5 0 0係由除放大器1 0 0 之外的切換器及電容器所構成。 具體而言，偏差補償部係由形成於屬放大器100之負輸 入端（-)的第一節點（n e t 1 )與屬放大器1 〇 〇之第二節點 (n e t 2 )之間的第一切換器（s w 1 )、形成於被賦加輸入電壓 的第三節點（net 3)與第四節點（net4)(形成於第三節點與 第二節點間之通路上）之間的第二切換器（s W2 )、形成於第 四節點（net 4)與第二節點（n et2)之間的第三切換器（Sw3) 、形成於第二節點與屬放大器1 〇〇輸出端之第二節點 (net2)及輸出負載間之第四切換器（SW4)、以及形成於第 四節點（ne t 4 )與第一節點（ne t 1 )之間的偏差補償電容器 (Coc)所構成。 此外，第四切換器（sw4)係在輸出負載較少，或放大器 以低速動作之情況時，便可省略。再者，各切換器係可採 用通常的NM0S電晶體、PM0S電晶體、或傳導電晶體等。 第8圖所示係類比放大器之各切換器，係具備第5圖所 示接通與斷開定時，且模示（mode) p 1、模示P 2、模示φ 3、及模示Ρ4形成一週期，並由放大器產生輸出。 12337241233724 V. Description of the invention (1) [Technical field to which the present invention belongs] The present invention relates to analog amplifiers, and more particularly to analog amplifiers having an offset compensation capacitor function. [Conventional technology] As is well known, analog amplifiers are widely used in the source driver (s 〇 urce drive r) of liquid crystal display elements (LCD: Li qi: lid Cr ysta 1 D isp 1 ay), and in Hundreds of analog amplifiers with corresponding output numbers are used on a single source driver chip. In this case, when a semiconductor manufacturing process is used to manufacture a wafer, hundreds of analog amplifiers will have different random deviations (r andom) depending on the engineering misalignment (mi sma t ch). Therefore, even if hundreds of analog amplifiers are all given the same input voltage, the analog amplifiers also get the same output voltage. Therefore, if the LCD panel is driven by an analog amplifier with different random compensation, it will cause a significant decrease in the color (co 1) quality of the LCD panel, so the compensation of the analog amplifier will form an extremely important factor on the circuit. . The symbol of the normal analog amplifier shown in Figure 1 has the input voltage (vi η) applied to the positive input (+), and the output of the analog amplifier that drives the output load at the negative input (-). The structure of the voltage (Vout) is fed back. The circuit diagram of the analog amplifier shown by the symbol in Fig. 1 shown in Fig. 2 is composed of input terminal 1 < 3, output terminal 20 and frequency compensation -3- compensation capacitor. (CC) Institute 1233724 V. Description of the Invention (2) Composition. The input terminal 10 is a transistor (Mil) that inputs an input voltage (V 1 η) by a gate, a transistor (MIL2) that adds a feedback output signal by a gate, and a transistor (Mil, MIL2) Transistors (MB1, MB2) for each load, and transistors (M IB) that apply a bias voltage (V bias) to a bias electrode and supply a bias current (biascurrent). In addition, the output terminal 20 is a transistor (MOD) connected to the gate electrode at the drain terminal of the transistor (M I 1) and driving the output node, and the bias voltage (Vb 1 as) is added to the gate and The traction drive output node is composed of a transistor (MOB). The frequency compensation capacitor (CC) is formed between the gate terminal and the source terminal of the transistor (MOD). The operation of the above structure will be described. If the input voltage (V i η) is applied, the difference between the gate and source voltages of transistors Mil and MI2 will cause a difference in current flowing between transistor Mil and transistor MI2 to control the voltage. The transistor MOD, 俾 generates an output voltage (Vout). In addition, as mentioned above, the amplifiers with the transistor Mi, MI2, MB1, MB2 in semiconductor technology (such as the ratio of the width and length of the transistor and the threshold voltage of each transistor are different) will also have an amplifier Deviation (〇ffset) 〇 Therefore, when the LCD source driver chip is composed of hundreds of analog amplifiers, analog amplifiers with mutually different random deviations will drive the LCD panel, resulting in a large color quality of the LCD panel The disadvantages of landing arise. [Problems to be Solved by the Invention] 1233724 V. Explanation of the Invention (3) The present invention has the disadvantages of the above-mentioned conventional technical problems, and aims to provide an analog amplifier with a deviation compensation function. [Means for solving the invention] In order to achieve the above-mentioned object, the analog amplifier of the present invention is characterized by having an amplifier and a deviation compensation mechanism; wherein, the amplifier is given an input voltage to the positive input terminal, and The output voltage is fed back to the negative input terminal and driven amplifier; and the deviation compensation mechanism is provided with a complementary capacitor that feeds back the output voltage of the amplifier, compares the output voltage with the input voltage, and stores the amplifier's deviation 値The difference between the input voltage and the drop 値 is provided to the positive input terminal, and the deviation compensation mechanism of the deviation is removed by the output voltage of the amplifier. [Aspect] The following embodiment of the invention, to be more specific description of the present invention, illustrated in the appended see, for various embodiments of the present invention is related to a detailed description of the square (second - - Example) shown in FIG. 3 based on the relevant A block diagram of an analog amplifier according to an embodiment of the present invention is shown in FIG. 3. The analog amplifier of the present invention includes an input voltage (V i η) applied to a positive input terminal (+); The output voltage of the amplifier itself is returned to Atfa m at the negative input (-) and driven by the amplifier 100; in order to feed back the amplifier's 100 output voltage (Voiit) and compare the output voltage with the input voltage (Vin), the storage amplifier The deviation of 100, and then the difference between the input voltage (Vin) and the deviation 提供 is provided to the positive input terminal (+), f -5- by the output voltage 1233724 V. Description of the invention (4) (Vout) The deviation compensation section that removes the deviation 200. The amplifier 100 can be composed of, for example, the circuit shown in FIG. 2 and various other circuits, and the deviation compensation unit 200 can obtain various embodiments. Fig. 4 shows a preferred embodiment of the deviation compensation section of the analog amplifier of the present invention shown in Fig. 3. Please refer to FIG. 4. The deviation complementary section 200 is composed of a switch and a capacitor other than the amplifier 100. Specifically, the deviation compensation unit is formed by a first node (netl) formed on the positive input terminal (+) of the amplifier 100 and a third node (net3) on the input voltage (Vin) terminal. The output voltage (Vout) terminal of the switch (swi) and the amplifier 10 is formed between the second node (net2) and the fourth node (net4) (formed on the path between the first node and the second node). Two switches (3 to 2), a third switch (sw3) formed between the third node (11 to 3) and a fourth node (11 to 4), formed at the second node and a slave amplifier 100. The second node (net 2) at the output end and the fourth switch (sw4) between the output load, and a frequency compensation capacitor formed between the fourth node (ne t 4) and the first node (ne t 1) ( Coc). In addition, the fourth switch (sw4) can be omitted when the output load is small or the amplifier operates at low speed. In addition, as each switcher, a general NMOS transistor, a PMOS transistor, or a conductive transistor can be used. Figure 5 shows the ON / OFF relationship for each switch (swl, sw2, sw3, sw4) in Figure 4, mode pi, mode Φ 2, mode # 3, and mode formation One cycle, and the output is generated by the amplifier. 1233724 V. Description of the invention (5) Figures 6A to 6D are individual circuit diagrams of each mode. The process of removing the deviation from the analog amplifier operation and the amplifier output voltage (Vout) of Fig. 4 will be described with reference to Figs. 5 and 6. First, as shown in FIG. 6A, when the input voltage (Vin) is applied, the first and second switches (swl, sw2) will be turned on in the process of storing the deviation 値 in the deviation compensation capacitor (Coc) ( turn on), and the third and fourth switches (sw3, sw4) are in the interval p 1 of the mode that is turned off. Because the first switch (swl) is turned on, if the input voltage Vl n is applied to the positive input terminal (+), the output voltage Vout of the amplifier will form Vin + Δ with a voltage 値 ΔV V. In addition, because the voltage at the first node (net 1) is Vin and the voltage at the third node (net3) is Vin + △ V, the comparison result of the input voltage Vi i η and the output voltage V 1 η + Δ V after feedback The deviation 値 Δν is stored in the deviation compensation capacitor (Coe). Secondly, the process shown in Figure 6B is to ensure the non-overlapping (N ο η-〇ve 1 · 1 ap) timing interval between the model (/) 1 and the model p 3, the first, second, and third And the fourth switches (swl, sw2, sw3, sw4) are all in the disconnected mode P 2 interval. In addition, the turn-off timing of the first and second switches (swl, sw2) and the turn-off timing of the third and fourth switches (sw3, sw4) do not overlap with each other. ) And Turn off (Turn off), this process is no longer needed. Secondly, as shown in FIG. 6C, the input voltage Vi η and the deviation 値 Δν are provided to the positive input terminal (+) of the amplifier 100, and the output voltage Vout is used to remove 1233724. 5. Description of the invention (6) The deviation process, the second The fourth switch (sw 3, sw 4) will be switched on, and the first and second switches (sw 1, s W2) will be shown in the disconnected mode (/) 3 because of the second Switching ^ (swS) is turned on ^ So Vm-Δ V is added to the positive input v and (+), so the output voltage Vout of the amplifier will be output from Vin + AV 値 Vin 値, so that the fourth switch When switched on, for example, an output load such as an LCD panel, an output voltage Vout is removed from the deviation 値 to drive. Secondly, the process shown in Figure 6D is to ensure a non-over lap timing interval between modulo ¢) 3 and modulo p 1. The first, second, third, and fourth switches (swl , Sw2, sw3, sw4) are all in the disconnected mode ¢) 4 interval. The turn-off timing of the third and fourth switches (sw3, sw4) and the turn-on timing of the first and second switches (swl, sw2) do not overlap each other. If they can be turned on and off at the same time, This process is no longer needed. (Second Embodiment) Fig. 7 is a block diagram of an analog amplifier according to another embodiment of the present invention. Please refer to FIG. 7, the analog amplifier of the present invention includes an input voltage (V 1 η) applied to the positive input terminal (+); an amplifier that feeds back its output voltage to the negative input terminal and drives the same 100; In order to feedback the output voltage (Vout) of the amplifier 100 and provide the output voltage to be compared with the input voltage Vin, the deviation 値 of the amplifier 100 is stored, and then the difference between the input voltage (V i η) and the deviation 提供 is provided The pre-negative input terminal (-) is removed by the offset compensation unit 500 of the amplifier 1233724. V. The output voltage (Vout) of the invention (7) 100. The amplifier 100 can be composed of, for example, the circuit shown in FIG. 2 and various other circuits, and the deviation complementary section 500 can obtain various embodiments. Fig. 8 shows a preferred embodiment of the drop complementary portion of the analog amplifier of the present invention shown in Fig. 7. Please refer to FIG. 8, the deviation complementary section 500 is composed of a switch and a capacitor other than the amplifier 100. Specifically, the deviation compensation unit is a first switch formed between a first node (net 1) of the negative input terminal (-) of the amplifier 100 and a second node (net 2) of the amplifier 100. (Sw 1), a second switch formed between a third node (net 3) to which an input voltage is applied and a fourth node (net4) (formed on a path between the third node and the second node) ( s W2), a third switch (Sw3) formed between the fourth node (net 4) and the second node (net 2), and a second node (formed at the second node and the output terminal of the amplifier 100) net2) and a fourth switch (SW4) between the output load and an offset compensation capacitor (Coc) formed between the fourth node (ne t 4) and the first node (ne t 1). In addition, the fourth switch (sw4) can be omitted when the output load is small or the amplifier operates at low speed. In addition, as each switcher, a general NMOS transistor, a PMOS transistor, or a conductive transistor can be used. Each switch of the analog amplifier shown in FIG. 8 is provided with the on and off timings shown in FIG. 5 and has a mode p 1, a mode P 2, a mode φ 3, and a mode P 4 A cycle is formed and the output is generated by the amplifier. 1233724
五、發明說明（8) 第9A圖至第9D圖所示係各模式之個別電路圖，與第一 實施例中所說明的第6A圖至第6D圖的動作，實質上相同 〇 即，當在第一與第二切換器（swl，sw2)被接通，而第三 與第四切換器（sw3，sw4)則被斷開的狀態下，賦加輸入電 壓V i η時，偏差値△ V便儲存於偏差補償電容器（Co c )中（ 請參閱第9A圖，模示φΐ)。 於輸出負載與輸出節點（n e t 2 )呈短路（s h 〇 r t )狀態下， 將輸入電壓V i n與偏差値△V之差値，提供給負輸入端（-) ，而由輸出電壓Vout去除偏差値Δν(請參閱第9D圖，模 不9 3)。爲模不φ 1與模不φ 3間之非重疊（Non-overlap) 定時區間模示p 2，與模示p 3與模示p 1間之非重疊 (Non-overlap)定時區間模示p 4，在各模式間並未重疊的 情況時，便可省略（可省略第9B圖與第9D圖之模示p 2與 模示φ 4 )。 本發明之技術思想，雖依上述較佳實施例進行具體陳 述，但請注意上述實施例僅爲說明使用，並非僅限定於 此。另，舉凡屬本發明技術領域中之專家，在本發明技 術思想範疇內，均可實施各種實施例。 【發明功效】 本發明之類比放大器，藉由本身具備去除偏差功能，譬 如當構成LCD源極驅動器晶片之類的數百個類比放大器時 ，各類比放大器便將依實質相同的電壓位準，以驅動LCD -10- 1233724 五、發明說明（9) 面板，而達提昇LCD面板之色彩品質的功效。 【圖式簡單說明】 第1圖係通常類比放大器之符號圖。 第2圖係第1圖符號所展現之類比放大器的電路圖。 第3圖係本發明一實施例之類比放大器的方塊圖。 第4圖係第3圖中所示相關本發明類比放大器之偏差補 償部之較佳實施例圖。 第5圖係第4圖及第8圖之各切換器的ON/OFF關係定 時圖。 第6A圖至第6D圖係第4圖之類比放大器的各動作模式 電路圖。 第7圖係本發明另一實施例之類比放大器的方塊構造圖 〇 第8圖係第7圖中所示相關本發明類比放大器之偏差補 償部之較佳實施例圖。 第9A圖至第9D圖係第8圖之類比放大器的各動作模式 電路圖。 【圖示符號說明】 10 輸入端 20 輸出端 100 放大器 200 偏差補償部 500 偏差補償部 -11- 1233724 五、發明說明（10) CC 頻 率 補 償 電 容 器 Co c 偏 差 補 償 電 容 器 Mil 電 晶 體 MI2 電 晶 體 MIB 電 晶 體 MOD 電 晶 體 Ne t 1 第 一 節 點 Ne t 2 第 二 節 點 Net 3 第 二 節 點 Ne t4 第 四 節 點 s w 1 第 -美 切 換 器 s w 2 第 二 切 換 器 s w3 第 二 切 換 器 s w4 第 四 切 換 器 Ψ 1 模 示 φ 2 模 示 Ψ 3 模 示 ψ 4 模 示 -12-V. Description of the invention (8) The individual circuit diagrams of each mode shown in Figures 9A to 9D are substantially the same as the operations of Figures 6A to 6D described in the first embodiment. That is, when the When the first and second switches (swl, sw2) are turned on, and the third and fourth switches (sw3, sw4) are turned off, when the input voltage V i η is applied, the deviation 値 △ V It is stored in the deviation compensation capacitor (Co c) (see Fig. 9A, the model φΐ). When the output load and the output node (net 2) are in a short-circuit (sh rt) state, the difference between the input voltage V in and the deviation 値 △ V is provided to the negative input terminal (-), and the deviation is removed by the output voltage Vout.値 Δν (see Figure 9D, Modular 9 3). Is a non-overlap timing interval modulo p 2 between modulo φ 1 and modulo 3, and a non-overlap timing interval modulo p between modulo p 3 and modulo p 1 4. It can be omitted if there is no overlap between the modes (the modal illustrations p 2 and φ 4 of FIGS. 9B and 9D can be omitted). Although the technical idea of the present invention is specifically described in accordance with the above-mentioned preferred embodiments, please note that the above-mentioned embodiments are for illustrative purposes only and are not limited thereto. In addition, various experts in the technical field of the present invention can implement various embodiments within the scope of the technical idea of the present invention. [Effects of the invention] The analog amplifier of the present invention has a function of removing deviations, for example, when constituting hundreds of analog amplifiers such as LCD source driver chips, the various analog amplifiers will be at substantially the same voltage level. To drive the LCD -10- 1233724 V. Description of the invention (9) Panel, to achieve the effect of improving the color quality of the LCD panel. [Schematic description] Figure 1 is a symbol diagram of a common analog amplifier. Figure 2 is a circuit diagram of the analog amplifier shown by the symbol in Figure 1. FIG. 3 is a block diagram of an analog amplifier according to an embodiment of the present invention. Fig. 4 is a diagram showing a preferred embodiment of the deviation compensation section of the analog amplifier of the present invention shown in Fig. 3. Fig. 5 is a timing chart of the ON / OFF relationship of each switch in Figs. 4 and 8. 6A to 6D are circuit diagrams of each operation mode of the analog amplifier of FIG. 4. FIG. 7 is a block diagram of an analog amplifier according to another embodiment of the present invention. FIG. 8 is a diagram of a preferred embodiment of the deviation compensation section of the analog amplifier according to the present invention shown in FIG. Figures 9A to 9D are circuit diagrams of each operation mode of the analog amplifier shown in Figure 8. [Illustration of Symbols] 10 Input 20 Output 100 Amplifier 200 Deviation Compensation Unit 500 Deviation Compensation Unit 11-1232424 V. Description of the Invention (10) CC Frequency Compensation Capacitor Co C Deviation Compensation Capacitor Mil MI2 Transistor MIB Transistor Crystal MOD Transistor Ne t 1 First node Ne t 2 Second node Net 3 Second node Ne t4 Fourth node sw 1 Second-US switch sw 2 Second switch s w3 Second switch s w4 Fourth switch器 1 model φ 2 model Ψ 3 model ψ 4 model -12-