TWI222273B - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device, wherein when the input signal IN for the oscillation having the first power voltage VDD1 is inputted into the gate terminal of PMOS transistor PM51with the second power voltage VDD2 higher than the first power voltage for operation, the PMOS transistors PM1 to PM4 will be conducted with level conversion; the source terminals for PM1, PM3 and PM2, PM4 of the PMOS transistors are connected with the first power voltage and the second power voltage; and, the gate terminal for PM4 of the PMOS transistor are connected with the drain terminals for PM1, PM2 of the PMOS transistor, the gate terminal for PM2 of the PMOS transistor are connected with the drain terminals for PM3, PM4 of the PMOS transistor; the inversed signal of the input signal IN and the input signal IN are inputted into the gate terminals for PM1 and PM2 of the PMOS transistor; and, the oscillation between the reference voltage VSS for the input signal IN and the first power voltage VDD1 are level-converted into the oscillation between the first and the second power voltages, and outputted from the PM1, PM2 of the PMOS transistor, and connected for controlling the PMOS transistor PM51.

Description

1222273 发明 Description of the invention (The description of the invention should be made clear: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the simple description of the invention) [Technical Field to which the invention belongs] The present invention relates to a kind of A semiconductor device with an interface having a power supply voltage of 5 voltage level conversion signal level, in particular, relates to a semiconductor device that can perform signal level conversion to a signal of a higher voltage level without frequent current consumption. BACKGROUND OF THE INVENTION 10 An output buffer circuit capable of outputting a signal of a voltage level higher than its own power supply voltage is disclosed in the patent document described below. In patent document i, as shown in Fig. 15, four intermediate converters are used which operate on the power supply voltage in the order of gradually increasing voltage levels, and then the lower voltage level is used to reduce the voltage level of the output voltage 〇υτ. Increase the voltage level in sequence to 15 P white (VL1, VH1), (VL2, VH2), (VL3, VH3), (VL3, VDD2) and we can see that the output signal at higher voltage levels is less than 20 The voltage levels vL 1 to VL3, VH1 to VH3 in the power supply voltage of this intermediate converter are obtained by dividing the higher voltage level VDD2 by the resistance elements 105 to ui. The prior art documents are shown below. Gazette Patent Document 1 · Japanese Patent Laid-Open Publication No. Hei 10-22810 describes the output buffer circuit disclosed in Patent Document 1 in a state where the output is 5 Ω, the invention description shows the number OUT, and the resistance element 105 is used. To 111, the power supply voltage VDD2 is divided to obtain voltage levels VL1 to VL3 and VH1 to VH3 to be supplied to the intermediate converter. Therefore, after the transition of the logic level of the input signal IN propagates through the intermediate converter, the logic state of the input > output # of the intermediate converter is fixed. Although no current is consumed in the intermediate converter, the power supply voltage VDD2 passes Resistive elements 105 to 1U cause regular current consumption. When a technology field in which a low current consumption operation such as a portable device is desired is used, there is a problem of frequent current consumption. The present invention has been made to solve the problems of the conventional technology. The purpose is to provide a signal connection between the second circuit group operated by the first power supply voltage and the second circuit group operated by the second power supply that is higher than the first power supply voltage. A semiconductor device that performs level conversion in the case of current consumption.

[Explicit content; J invention's disclosure In order to achieve the aforementioned purpose, the i-th semiconductor device has an i-th battery which operates between the reference voltage and the i-th power source ^ 2 and the reference voltage and The second power group of the i-th power source is willing to operate between the second power source ㈣ of the power level, and its special test is to include ... The conductive type electric-migration-controlled high-roof-side element ’is the input section of the second circuit group to perform the rotation control of the aforementioned second power supply; and the one-stage conversion circuit’ is the first! The interface of the circuit group to the second circuit group ’is at the first! The power supply unit and the second power supply house perform an operation as a power source, and the conduction voltage control type high-voltage side element is turned on; and the 4-level conversion circuit has a conductive type of voltage control type. The element is provided between the voltage-controlled high-voltage side element and the first voltage power source and supplies the first power voltage when the voltage-controlled high-voltage side element is turned on; and a voltage-controlled second element of the first conductivity type , Is provided between the voltage-controlled high-voltage side element and the second voltage power supply, and when the voltage-controlled high-voltage side element is made non-conducting, the second power supply voltage is supplied. In the first aspect of the semiconductor device, in order to switch between the i-th circuit group and the second circuit group, a level conversion circuit that operates between the first power supply voltage and the second power supply I can be used. The level conversion circuit supplies the first and second power supply voltages through the first and second elements of the voltage-controlled element of the first conductivity type, and makes the second circuit group of the voltage-controlled element of the first conductivity type. The high-side components are conductive and non-conductive. Accordingly, since the level conversion circuit is configured to supply the second power supply voltage to the first power supply instead of the reference voltage, the applied voltage difference becomes a voltage difference between the first and second power supply voltages. The voltage difference between the second power supply voltages can be used to configure the interface using components that cannot ensure the withstand voltage. In addition, in order to ensure the withstand voltage, it is not necessary to make an intermediate third power supply voltage by distributing the ratio of the first and second power supply voltages. Therefore, there is no current consumption that is distributed in proportion to the power supply voltage. In addition, "the second power supply voltage is used as the reference voltage, and there is no constant current consumption in the high-voltage side components that control conduction and non-conduction according to the supplied voltage level." 2 Power supply voltage, and conducting control.发明 Description of the invention Here, since the i-th and second elements provided in the level conversion circuit are composed of the first conductivity type having the same conductivity type as the high-voltage side element, the level conversion circuit can be easily configured to float relative to the reference voltage. Turn-on control of the i-th and second power supply voltages. The semiconductor device according to the second aspect is the semiconductor device according to the second aspect, and is preferably connected to the aforementioned circuit group in the aforementioned voltage-controlled type element. Thereby, the voltage signal from the first circuit group can be constantly input to the level conversion circuit. In addition, the third aspect of the semiconductor device is the semiconductor device of the first or second aspect, and the level conversion circuit further includes a voltage control type third element of the i-th conductivity type, which is provided for voltage control. Between the second type element and the first power supply voltage, and when the voltage control type second element is turned on, the first power supply voltage is supplied; and one! The conductive type voltage control type fourth element is provided between the voltage control type second element and the second power supply voltage, and when the voltage control type second element is made non-conductive, the second power supply voltage is supplied. In the third semiconductor device, the second element of the voltage control type is supplied by the third and fourth elements of the voltage control type! And the second power supply voltage, and controls conduction and non-conduction. Here, the third and fourth elements are also the first conductivity type, and operate as a constituent element of the level conversion circuit between the i-th power source voltage and the second power-source voltage. In addition, the semiconductor device having the M 4 aspect is a semiconductor device with the 3 aspect, and the fourth element is turned on in response to the supply of the first power source by the first element, and the second element is provided in the second power source by the second element. Voltage instead of conduction, inventor. With this, the second and fourth elements that perform voltage control based on the second power supply voltage will not have regular current consumption, and within the range of the withstand voltage of the element, the first and second power supply voltages are switched to conduct conduction and non-operation. On-ground control. The semiconductor device according to the fifth aspect is in the semiconductor device of the third aspect. The level conversion circuit is preferably connected to the i-th circuit group in the voltage-controlled third element. Thereby, the voltage signal from the first circuit group can be constantly input to the level conversion circuit. In addition, the semiconductor device according to the sixth aspect is the first one that operates between the first power source! The circuit group, and the second circuit group that operates between the second power source and the second power source, which are higher than the first power source, the power tail, and the white tail, are characterized by including: an output PM0s transistor , Is set in the input section of the aforementioned second circuit group, and is turned on by supplying the i-th power supply voltage through the gate terminal, and outputs the second power supply voltage; and the one-stage conversion circuit is from the i-th circuit group to The interface of the second circuit group, which operates between the first power source and the second power source as a power source, and turns on the control output PMOS transistor; wherein the level conversion circuit has a first PMOS transistor. It is located in the path from the power source to the output terminal, and the gate terminal is used to supply the g1 # number from the first circuit group to turn on the controller. 2continued transistor, which is placed in the path of the terminal from the second power supply voltage to the output pM0s transistor, and borrows the gate terminal to supply the first signal of the first power supply voltage. '-帛 3 PM〇s transistor, which is arranged by the first power supply 1222273 Explain the path to the gate terminal of the 2PM0S transistor, and to supply the second signal from the first circuit group by the gate terminal to turn on the controller; and a 4PM0S transistor, which is configured by the second power supply The voltage is in the path of the gate terminal of the 2PM0S transistor, and the first or second power supply voltage is supplied to the gate terminal through the first or 2PM0S 5 transistor to become conductive or non-conducting; Either terminal of the 3PM0S transistor can be controlled to be conductive. Regarding the sixth aspect of the semiconductor device, the first PMOS transistor is turned on, and the first power supply voltage is supplied to the gate terminal 10 of the output PMOS transistor and the gate terminal of the fourth PMOS transistor to turn on the two transistors. By turning on the fourth PMOS transistor, the second power supply voltage can be supplied to the gate terminal of the second PMOS transistor, and the second PMOS transistor is non-conductive. At this time, the third PMOS transistor is non-conductive. In contrast, when the first PMOS transistor is non-conducting and the third PMOS transistor is conducting, the second PMOS transistor is 15 conducting, and the output PMOS transistor and the fourth PMOS transistor are non-conducting. Here, the terminals of each transistor can be Directly coupled, or connected through circuit elements with voltage-reducing functions such as resistance elements or diode elements. It is only necessary to have a structure in which a voltage greater than a threshold voltage is applied between the gate and source 20 terminals when the first power source voltage is supplied to the gate terminal. In addition, the high-level voltages of the first and second signals supplied from the first circuit group may be the first power supply voltage, or may be a voltage that boosts the first power supply voltage, or a voltage that is converted to a higher level. The voltage. Among the high-order voltages in the first and second signals, the first and third PMOS transistors are non-conducting. 10 1222273 Accordingly, since the level conversion circuit is configured by supplying the first power supply voltage to the i-th power supply voltage instead of the reference voltage, the applied voltage difference becomes the voltage difference between the first and second power supply voltages. Number! It is not necessary to ensure the withstand voltage of the second power supply voltage to the 5th 4PM0S transistor, and it can be composed of a lower withstand voltage element. When switching levels, it is not necessary to make an intermediate third power supply voltage by proportionally distributing the first and second power supply voltages, and there is no current consumption due to the proportional distribution. Moreover, the semiconductor device according to the seventh aspect is the semiconductor body device of the sixth aspect, and the first and second signals are preferably logic signals which are mutually opposite. Thereby, only one of the first and third PMOS transistors can be turned on. The semiconductor device according to the eighth aspect is the semiconductor device according to the sixth aspect, and the first and second NMOS transistors with a predetermined bias voltage often applied to the gate terminal are connected to the i and 3 pMOS transistors. The path from the crystal to the 2nd and 15th 4PMOS transistors is arranged in the path between the output and the gate extreme + of the 4PM0S transistor or to the point where the gate terminal diverges. In the eighth aspect of the semiconductor device, when the first or third pM0s transistor is turned on by the first or second signal, the 帛 1 and second NMOS transistors are turned on, and when the first or third PM0S transistor receives When the non-conducting control is 20, the voltage of the non-terminal of the 1 or 2 NMOS transistor is reduced by the first or second signal and then supplied to the i or 3 pMOS transistor. When the 1st or 3PMMOS transistor is turned on, the output and the 4PM0S transistor's gate terminal or the 2pM0s transistor's gate 11 1222273 发明, description of the invention ... The editor gives the first power supply voltage, and at the same time, when the non-conduction, the supply industry steps down the voltage through the second power supply voltage to the Jth or 3pMOS transistor. When the first or third PM0S transistor is formed with the same threshold voltage as the output PMOS transistor or the second and fourth PM0S transistors, the first or third PM0S transistor can be controlled in a non-conductive manner. The semiconductor device according to the ninth aspect is the semiconductor device of the eighth aspect, and the gate terminals of the second and second NMOS transistors should be connected to a predetermined bias voltage source. In addition, the semiconductor device related to the tenth aspect is the ninth semiconductor device, and it is preferable to have a voltage step-down section, which is provided at a gate from a predetermined bias voltage source to the aforementioned first and second NMOS transistors. Within the path of the extremes. Moreover, the semiconductor device according to the eleventh aspect is the semiconductor device according to the tenth aspect, and the voltage step-down portion is preferably a diode element or a transistor formed by connecting the diodes, or the foregoing diode element and the electric element. Multi-segment connection or combination of crystals. The semiconductor device 15 in the twelfth aspect is the semiconductor device in any one of the ninth to eleventh aspects, and the predetermined bias voltage source is a second power source voltage or a voltage source externally supplied. Accordingly, the gate terminals of the first and second NMOS transistors apply appropriate predetermined bias voltages. Moreover, the semiconductor device in the thirteenth aspect is a semiconductor 20-body device in the sixth aspect. The third PMOS transistor system has a higher threshold voltage than the output PMOS transistor, the second PMOS transistor, and the fourth PMOS transistor. Therefore, even when the first and second NMOS transistors are not provided, the first or third p] VI0s transistor can be non-conductively controlled without being restricted to the conduction of the output PMOS transistor or the second and fourth PMOS transistors. . 12 1222273 发明, description of the invention ′ When the first and second NMOS transistors are provided, the voltage range of the predetermined bias voltage can be further expanded. In addition, the semiconductor device according to the 14th aspect is the semiconductor device according to the 6th aspect, and a gate voltage control unit for controlling the voltages of the respective gate terminals of the 5th and 1th PMMOS transistors is further provided. In the fourteenth aspect of the semiconductor device, when the gate voltage control unit is a voltage applied to the drain terminal of the first or third PM0S transistor greater than the voltage of the first power supply plus the first predetermined voltage, The voltage of the gate terminal of the first or third PM0S transistor is set to 10 volts of the second power source, and when the second power source voltage applied to the drain terminal of the first or third PM0S transistor is less than the first power source voltage When the voltage of the first predetermined voltage is added, the voltage of the gate terminal of the first or third PM0S transistor is set to the Jth power supply voltage. Therefore, when the first or third PM0S transistor is non-conductingly controlled, that is, the second power supply voltage is directly applied to the terminal without the 15 terminal, and the application can be controlled according to the voltage value of the second power supply voltage relative to the first power supply voltage. The voltage at the gate terminal and non-conducting to maintain the first! Or the 3 pMos transistor. And will not form through the first! Or the unnecessary current path of the 3PM0s transistor to the i-th power supply voltage can prevent unnecessary current consumption.

2 ′ And it is possible to control the i-th or 3rd PMOS transistor non-conductively without being stuck on the difference between the output voltage of the P transistor or the second and fourth PMOS transistor. Regarding the semiconductor devices of the 15th and 16th aspects, the semiconductor device of the 16th aspect is the electrical waste of the 14th aspect of the 1st power supply plus 1V of voltage. 13 Description of the invention 'It is preferable that the 1st or 3PM0S transistor The voltage when the drain terminal is turned on to the first power supply voltage side. At this time, the first predetermined voltage should be a voltage corresponding to the threshold voltage of the first or third PMOS transistor. The semiconductor device according to the seventeenth aspect is a half-conductor device of the fourteenth aspect, and the gate voltage control unit is provided between the first circuit group and the gate terminal of the first or third PM0S transistor. . In the 17th aspect of the semiconductor device, when the gate terminal of the i-th or 3PM0S transistor is set to the second power supply voltage, the first gate electronic control unit can prevent the second power supply voltage from being changed by the When the gate terminal of the 3pm0s 10 transistor is applied to the first circuit group, and when the gate terminal of the third or third PM0S f crystal is set to the i-th voltage, the first circuit group and the first or Gate terminal of the 3PM0S transistor. This prevents the second power supply voltage from being applied to the first circuit group operating at the first power supply voltage, and does not apply an overvoltage to the constituent elements of the i-th circuit group. The semiconductor device according to the eighteenth aspect is the semiconductor device according to the seventeenth aspect. The first inter-electrode voltage control unit has a first transistor, and the 5PM0S transistor system has a drain terminal and a source terminal connected respectively On the first circuit group side and the first! Or the 20th side of the free terminal of the 3pM0s transistor. Therefore, if the 5PM transistor is turned on, the gate terminal of the first or third transistor is set to the i-th power supply voltage. If it is non-conducting, it is set to the gate terminal of the first or 3PM0S transistor. The second power supply voltage is not applied to the first circuit group. "The semiconductor device of the 19th aspect is in the half of the 17th aspect 14 1222273", Invention Description 5 Conductor Device "The first gate voltage control unit has a _third read transistor, and the 3NM0S power The drain terminal and source terminal of the crystal system are connected to the side of the first circuit group and the gate terminal of the first or third S-transistor, respectively, and the intermediate terminal is connected to the first! tSource㈣ 者. With this, even if the second power source is set at the gate terminal of the first or third PM0S transistor, the voltage applied to the first circuit group can be limited to a voltage less than the threshold voltage of the third power source voltage element minus the threshold voltage of the 3NM0S transistor. Without overvoltage applied to the ^ th circuit group. In addition, there is a semiconductor device of the type M 2 0H recorded in the first half of the sample. In the conductor device, the gate electrode control section has a second inter-electrode voltage control section, which is connected to the gate terminal of the 5PM0S transistor. Set the voltage. In the semiconductor device related to the 2G aspect, when the gate terminal of the ## 丨 or 3ρΜ〇§ transistor is set to the second power supply voltage, the 5th transistor can be contacted by the second interrogator voltage control unit. The gate terminal is set at the 2 U power supply voltage and becomes the first! Or, when the gate terminal of the 3PM0s transistor is set to the first power supply voltage, the gate terminal of the 5PM0S transistor is set to a voltage lower than the voltage at which the 5PMQS f crystal starts to be turned on. Thereby, the conduction control between the terminals of the first circuit group and the i-th or 3 PM-transistor can be performed by the 5th PMQS t crystal. Here, the semiconductor device of the 20th and 21st aspects is the semiconductor device of the 2nd () aspect, and the electrical waste that starts to be turned on should be the voltage of the first power supply minus the threshold voltage of the 5PM0S transistor. . In addition, the semiconductor device according to the 22nd aspect is the semiconductor device according to the 20th aspect. The second gate voltage control unit includes a sixth PMOS power 15 1222273. A crystal of the invention, and a source of the 6PM0S transistor system. The terminal and the drain terminal are respectively connected to the drain terminal side of the first or 3PM0S transistor and the gate terminal side of the aforementioned 5PM0S transistor, and the gate terminal is connected to the first power supply voltage. Therefore, when the second power supply voltage is greater than the first power supply voltage plus the threshold voltage of the 5th 6PM0S transistor, the 6PM0S transistor can be turned on, and the gate terminal of the 5PM0S transistor can be set to the second power source. Voltage is non-conducting. And by adding the threshold voltage of the 6PM0S transistor to the threshold voltage of the 1 or 3PM0S transistor, the second power supply voltage can be prevented from going from the gate terminal of the 1 or 3PM0S transistor to the 10th circuit group of the 1st transistor Apply. The semiconductor device according to the twenty-third aspect is the semiconductor device according to the twenty-second aspect. The second gate voltage control unit has a fourth PMOS transistor, and the drain terminal and the source terminal of the fourth PMOS transistor system are respectively connected to The drain terminal side of the first or third PMOS transistor and the gate electrode side of the fifth PMOS transistor 15 are controlled by the aforementioned first or second signal and its in-phase signal. Accordingly, when the second power supply voltage applied to the drain terminal of the first or third PMOS transistor is a voltage smaller than the first power supply voltage plus the threshold voltage of the sixth PMOS transistor, the sixth PMOS transistor is non-conductive. In this state, since the 4NMOS transistor is on, 20 and the voltage applied to the gate terminal of the 5PMOS transistor is limited to the voltage applied to the gate terminal of the 4NMOS transistor minus the threshold voltage. Turn on the 5th PMSO transistor. This state continues until the 6th PMOS transistor is turned on, and becomes non-conductive after the 6th PMOS transistor is turned on. 16 1222273 发明. Description of the invention. The semiconductor in the 24th aspect | is placed in the half of the 23rd aspect. In the body device, the first power source of the 4NM0S transistor is applied with the first power transfer or the first 1 The voltage at which the supply voltage drops. In addition, the semiconductor device according to the twenty-fifth aspect is a semiconductor device according to the twenty-fourth aspect, and further includes a voltage step-down section, which outputs the voltage level of the first or second signal or its in-phase signal after being stepped down. By. Thereby, the higher voltage level of the first or second signal or its in-phase signal can be applied as the power supply voltage of the 帛 1 circuit group, or it can be applied as a voltage stepped down by the 电源 i power supply voltage. The step-down voltage can be generated through the voltage step-down section. 15 The semiconductor device according to the twenty-sixth aspect is the semiconductor device according to the second () aspect. The gate voltage control unit of the second aspect has a 5NMOS transistor, and the 5NMOS 1 has no terminals and sources. The terminals are respectively connected to the gate terminal side of the 5PM0S transistor and the reference voltage, and the gate terminal is controlled by the inverted signal of the first or second signal. Thereby, the i-th or the third PM0S transistor whose first or second operation is a low voltage level will not be turned on, and the fifth PM0S transistor will be turned on. In addition, the semiconductor device of the 27th aspect is the semiconductor device of the 6th, 8th, or 22nd aspect, and there is an N-well potential control unit, which is set as the second power source according to the voltage level of the second power source voltage. The N-well potential of the 1st, 3rd, 5th, and 6th PMOS transistor when the voltage is applied to the 20 terminal. In the twenty-seventh aspect of the semiconductor device, when the second power source voltage is greater than the first power source voltage plus the second predetermined voltage, the nth, third, fifth, and sixth PM0S can be controlled by the n-well potential control unit. The n-well power of the transistor 17 1222273 玖, the description of the invention is set to the second power supply voltage, and when the second power supply voltage is less than the first power supply voltage plus a second predetermined voltage, the N-well potential is set to the first power supply Voltage. Accordingly, since the potential of the N-well of the PMOS transistor is set to an appropriate voltage in accordance with the voltage level of the second power source 5 voltage, it does not become a floating state in a specific voltage level. The potential of the N-well can be set according to the voltage level of the second power supply voltage, so that the stable circuit can always be operated. The semiconductor device according to the twenty-eighth aspect is the semiconductor device according to the twenty-seventh aspect. The N-well potential control unit has an eighth PM0S electric 10 crystal. The source terminal is connected to the first power supply voltage, and The ninth terminal and the rear gate terminal are connected to the N well; a 9PMOS transistor, the source terminal is connected to the drain terminal of the first or third PMOS transistor, and the drain terminal and the rear gate terminal are connected to N And the gate terminal is connected to the first power supply voltage; and a PMOS transistor control section is connected to the gate terminal of the 8th PMOS 15 transistor and conducts control of the 8th PMOS transistor. In the twenty-eighth aspect of the semiconductor device, when the second power supply voltage in the source terminal of the ninth PMOS transistor is greater than the first power supply voltage plus a second predetermined voltage, the ninth PMOS transistor is turned on and supplied to the second The power supply voltage is in the N well. on the other hand. The 8th PMOS transistor can be controlled by the 20 PMOS transistor control section. When the second power source voltage is less than the first power source voltage plus the second predetermined voltage, the eighth PMOS transistor is turned on and the first power source voltage is supplied to the N-well. The semiconductor device according to the twenty-ninth aspect is the semiconductor device according to the twenty-eighth aspect. The voltage of the first power supply voltage plus the second predetermined voltage is eighteenth 1222273. 发明, Description of the invention...... 9PM0S 电The voltage at which the crystal starts to conduct. The semi-V body device in the 30th aspect is the semiconductor device in the 28th aspect, and the second predetermined voltage is a voltage equivalent to the threshold voltage of the 9PM0S transistor. Thereby, the second power supply voltage is the voltage of the first summer power supply voltage plus the threshold voltage of the 9 pM0s 5 transistor, and the N-well potential is switched between the first power supply voltage and the second power supply voltage. In addition, the semiconductor device according to the 33rd aspect is the semiconductor device of the 6, 18, or 22 d. The semiconductor device has an N-well potential control unit that applies a second power supply voltage to the The μ potential of the first, ⑺3, 35, and 帛 6PM0s transistors when the terminal is drained is set to the second power supply voltage. In the semiconductor device according to the 33rd aspect, when the second power source is applied to the non-polar terminal, the N-well potential of the third, third, fifth, and sixth PM0S transistors can be set to 2nd power supply voltage. Accordingly, since the second power supply voltage 'is applied to the second power supply voltage through the drain terminal of the PMOS transistor, the specific voltage level' does not become a floating state. ^ The semiconductor device of the 34th aspect is in the semiconductor device of the 33rd aspect. The aforementioned N-well potential control unit has an 8PM0S electric 20 crystal ^ source terminal connected to the first power source, Extreme terminal and rear s: Shanzi is connected to N well, ^^ extreme terminal is connected to the 1st or 3PM0S ^ said the body and / or the extreme terminal; 帛 9P delete the transistor, the source terminal is connected; A or 3PMQS The drain terminal of the transistor, the JL drain terminal and the first terminal are connected to the N well; and-PMC) S transistor control unit, 19 1222273 玖, the description of the invention is connected to the gate terminal of the aforementioned 9PM0S transistor And used to turn on and control the 9PM0S transistor. In the semiconductor device of the 34th aspect, the 9PM0S transistor can be controlled by a PMOS transistor. When the second power supply voltage is applied to the 5th drain terminal of the first or third PM0S transistor, the 9PM0S transistor can be turned on and the second power supply voltage can be supplied to the N well. Thereby, when the second power source voltage is applied to the drain terminal of the first or third PMOS transistor, the potential of the N-well can be converted to the second power source voltage. In addition, the semiconductor device according to the 31st aspect is the half 10th conductor device of the 28th aspect, and the PMOS transistor control section has a 6NMOS transistor, and the source terminal is connected to the gate of the 8th PMOS transistor. A terminal connected to the drain terminal of the first or the third PMOS transistor, and the gate terminal is applied with the first power supply voltage or a pre-voltage that is lower than the first power supply voltage, and a tenth PMOS transistor, The source terminal is connected to the 15th or 3rd PMOS transistor, the non-terminal is connected to the gate terminal of the aforementioned 8th PMOS transistor, the gate terminal is connected to the aforementioned J-th power supply voltage, and the rear gate terminal is Connected to N well. The semiconductor device according to the thirty-fifth aspect is the semiconductor device according to the thirty-fourth aspect. The PMOS transistor control section has a 6NMs 20 transistor, and the source terminal is connected to the ninth PMOS transistor. A gate terminal whose drain terminal is connected to the first power supply voltage, and a voltage applied to the drain terminal of the first or third PMOS transistor or a predetermined voltage lower than the voltage is applied to the gate terminal; and a 10th PMOS voltage Crystal, the source terminal is connected to the first power supply voltage, the drain terminal is connected to the 20PM of the 9PM transistor. 晶体, the description of the invention, the gate terminal, the gate terminal is connected to the first terminal of the 3PM0S transistor Terminal, and the rear gate terminal is connected to the N well. In the semiconductor device of the 31st or 35th aspect, the 6NM0S transistor can be used to cause the voltage applied to the terminal of the fork power supply or the 5th 3PM0S transistor line terminal, or a predetermined voltage lower than the aforementioned voltage. The voltage minus the threshold voltage of the 6NM0S transistor is the upper limit voltage, it is applied to the gate terminal of the 8th or 9PM0S transistor, and the 8th or 9PM0S transistor is turned on. On the other hand, by using the i0pM0s transistor, the voltage of the second power supply voltage greater than the i-th power supply voltage plus the intervening voltage of 10 or the i-th power supply voltage greater than the second power supply voltage plus When the voltage of the upper threshold voltage is turned on, the 10 PMOS transistor can be turned on, and the 8 or 9 PMOS transistor can be turned off. The semiconductor device according to the thirty-seventh aspect is the semiconductor device according to the thirty-first or thirty-fifth aspect, and the predetermined voltage is preferably the i 15 power supply system among most power supply systems. The semiconductor device according to the thirty-eighth aspect is a semiconductor device according to the thirty-third or thirty-fifth aspect, and it is preferable to have a second voltage step-down portion. The second voltage step-down portion is arranged at the gate end of the 6NM transistor. And the drain terminal of the first power supply voltage or the first or the third PMMOS transistor, and applied to the first power supply voltage or the first! Or, after the voltage level of the drain terminal of the 3pM0s transistor 20 is lowered, a predetermined voltage is input. 6NMOS transistor, the semiconductor device related to the 32nd aspect is included in the semiconductor device according to the 31st aspect, or the semiconductor device related to the 36th aspect is included in the semiconductor device according to the 35th aspect, the PMOS transistor control unit It also has a j-th voltage step-down section. The first voltage step-down section is connected to the source terminal of the 21st, 2222273th, invention description body, and the voltage signal from the source terminal is stepped down and input to the 8th. Or the gate terminal of the 9PM0S transistor. Thereby, the conduction control of the 8th or 9PM0S transistor can be performed, and the potential of the N well will not be in a floating state. At this time, the step-down voltage can be applied to the gate terminal of the 8th or 5th 9PM0S transistor. And can reliably turn on the 8th or 9PM0S transistor. Brief Description of the Drawings Fig. 1 is a circuit diagram showing an embodiment of the present invention. Fig. 2 is a circuit diagram showing the first method for preventing the PMOS crystal 10 constituting the level conversion circuit from being turned on incorrectly. Fig. 3 is a circuit diagram showing a second method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. Fig. 4 is a circuit diagram showing a third method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. 15 Figure 5 shows a specific example of the third method in Figure 4. Fig. 6 is a circuit diagram showing a fourth method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. Fig. 7 shows the characteristics of the gate terminal voltage of the PMOS transistor PM5 in the fourth method. 20 Figure 8 shows the characteristics of the gate terminal voltage of the PMOS transistor PM1 in the fourth method. Fig. 9 is a circuit diagram showing a first specific example of the N-well potential control section in the fourth method. Fig. 10 is a circuit diagram showing a specific example of the 22nd 2222273 of the N-well potential control unit in the fourth method, a description of the invention. Fig. 11 shows the switchover of the well potential of the n-well potential control unit of the first and second specific examples. Fig. 12 is a circuit diagram showing a 35th specific example of the N-well potential control section in the fourth method. Fig. 13 shows a switchover of the well potential of the N-well potential control section of the third specific example. Fig. 14 is a circuit diagram showing a level conversion section for driving the low-voltage side of the NMOS transistor NM51 in the level conversion circuit of the embodiment. ) FIG. 15 is a circuit diagram showing a level conversion circuit of the conventional technology. I [Embodiment 3 Best Mode for Carrying Out the Invention] A detailed description will be given below of a semiconductor device according to the present invention with reference to the drawings, and referring to the drawings. Fig. 1 is a diagram showing the implementation of a semiconductor device to which the present invention is applied. Contains a first circuit group 3 that supplies the first power supply voltage VDD1 to the reference voltage νπ and operates; and a second circuit group 5 that supplies the reference voltage VSS that is higher than the first power supply voltage VDD. The second power supply voltage of the voltage level is an operator. The first circuit group 3 is a circuit portion requiring high-speed processing speed. In addition, it is a suitable circuit part suitable for high-performance and high-speed electronic equipment control or arithmetic processing. In order to achieve high performance and high speed, it is generally realized by fine-grained and advanced program technology. Therefore, the components of the first circuit group 3 exemplified by the inverter gate 131 are required to have a low power of 23 发明. The invention explains that the voltage operation m power supply voltage VDD1 is a low power supply Y suitable for this specification ... "constitutes the first circuit group 3 The components only need to ensure the withstand voltage in the first S primary power G VDD1 of the low power supply voltage, and compared with the first power supply dust VDD1, the high voltage of the second power supply voltage vDD2 cannot ensure the withstand voltage. At this time, The 2nd source power M VDD2 circuit group 5 cannot be applied to these components. It is a part of the circuit that operates on the second power supply voltage side 2 which is lower than the south power supply voltage. Moreover, it is applicable to the existing power supply system. The control part of the moving machine, etc., and other elements, devices, etc. of the predetermined voltage in the predetermined voltage control or drive circuits. These circuit parts are necessary for the high-performance and high-speed operation of the first power supply. [The second power supply of different voltage values of VDD1> 1 VDD2 is necessary. • The second power supply voltage VDD2 is higher than the first power supply voltage VDD1. The figure shows that the first circuit group 3 has the first power supply. The input signal IN of the vibration field is taken as the second circuit group 5 There | power supply voltage VDD2 Xi @ as β μ, eight of the output signal of the transducer towel 0UT output fields in the input IN of No. 4 in the i-th circuit group 3, for the treatment and control operation 20.

Result signal of processing and so on. In addition, the output signal OUT is set to the semiconductor in this way, and the external port P is output, and becomes the driving signal or control of other components or devices. In addition, it can also be considered as the input number 0 of «2 circuit group 5 — ~ training eight Porch, knife, and you have the same power, VDn? Μ & r «υΕ > 2 PMOS 1 24 1222273 as a voltage-side converter, description of the invention PM51, and a source terminal connected to the reference The voltage VSS is used as the NMOS transistor NM51 of the low-side converter. After the signal is input to the individual gate terminals by the level conversion circuit 1 described later, exclusive conversion control is performed. The individual drain terminals of the PMOS transistor PM51 and NMOS transistor NM51 are used as the source terminals of the PMOS / NMOS transistor PM / NM52, which are output terminals and the wave terminals connected to the two are connected to each other. The gate terminal of the PMOS / NMOS transistor PM52 / NM52 is connected to the first power supply voltage VDD1. PMOS / NMOS transistors PM52 / NM52 are turned on when 10 PMOS / NMOS transistors PM51 / NM51 are turned on. At this time, the non-conducting NMOS / PMOS transistors NM52 / PM52 are biased to saturation characteristics by applying a second power supply voltage VDD2 / reference voltage VSS to individual drain terminals. Therefore, among the drain terminals of the NMOS / PMOS transistor NM51 / PM51, the voltage of the lower threshold voltage of the NMOS transistor 15 is applied by the first power supply voltage VDD1, and the threshold of the PMOS transistor PM52 is applied by the first power supply voltage VDD1. Higher voltage. Therefore, in the second circuit group 5 in which the second power supply voltage VDD2 is applied to the reference voltage VSS, only the second power supply voltage VDD2 and the first power supply voltage VDD1 are applied to the PMOS / NMOS transistors PM51, 52 / NM51, and 52. The difference is 20 volts / the voltage of the first power supply voltage VDD1. As a result, the second circuit group 5 that supplies the second power supply voltage VDD2 having a relatively high voltage value can also be configured using a low-withstand voltage crystal. Furthermore, although the transistor system used for ensuring the withstand voltage is shown in the embodiment as a one-stage PMOS / NMOS transistor PM52 / NM52, 25 1222273 发明, description of the invention can also be made into a multi-stage structure with two or more stages. This form should be structured such that the voltage applied to the gate terminals of the MOS transistors can be appropriately adjusted and the applied voltage can be switched in stages. By adopting a multi-stage structure, when a second power supply voltage VDD2 of a higher voltage is supplied, a circuit with a low withstand voltage can also be used. 5 is a level conversion circuit 1 which is provided between the first circuit group 3 and the second circuit group 5 and performs level conversion of a signal from the first power supply voltage VDD1 to the second power supply voltage VDD2. In the level conversion circuit 1, the circuit for driving and controlling the gate terminal of the PMOS transistor PM51 of the high-side converter is regarded as only the 10-stage conversion section 4 on the high-side, and is composed of four PMOS transistors PM1 to PM4. . The source terminals of the PMOS transistors PM1, PM3, and PM2 and PM4 are connected to the first power supply voltage VDD1 and the second power supply voltage VDD2, respectively. The gate terminal of the PMOS transistor PM4 is connected to the drain terminals of the pMOS transistor PM1 and PM2, and is also connected to the gate terminal of the PMMOS transistor 15 PM51 (node N3). The gate of the PMMOS transistor pM2 is connected to the terminals (node N4) of the PMOS transistors PM3 and PM4. Furthermore, the gate terminal (node ni) of the PMMOS transistor pM1 is connected to the output node N1 of the inverter gate 131, and the gate terminal (node N2) of the PMOS transistor PM3 is connected to the input signal to . 2 In addition, the signal used to drive the gate terminal of the NMOS transistor pm51, which is used to control the low-side converter, is a signal that has undergone a change in voltage level relative to the input signal IN. Then, it is output from the low-level-side level conversion section 6 (see Fig. 14). Enter 彳. F1 is the voltage level 26 with the first power supply voltage VDD1 26 1222273 发明, description of the invention:; '-·.-; ..' '-;;.., Node N1 by inverter gate 131 becomes The lower level with the voltage level of the reference voltage VSS. The input signal IN is input to the gate terminal (node N2) of the PM3 transistor PM3, and a first power supply voltage VDD1 is supplied to the gate terminal. The node N1 is connected to the gate terminal (node N1) of the PMOS transistor PM1 5 and supplies a reference voltage VSS to the gate terminal. Since the source terminal of the PMOS transistor PM1 is connected to the first power supply voltage VDD1, the PMOS transistor PM1 is turned on. By turning on the PMOS transistor PM1, the first power supply voltage VDD1 can be supplied to the node N3 connected to its drain terminal, and to the gate terminals of the PMOS transistor PM4 and PM51. Since the source terminals of the PMOS transistors PM4 and PM51 are connected to the second power supply voltage VDD2, the first and second power supply voltages VDD1 and VDD2 are applied between the gate and source terminals of the PMOS transistors PM4 and PM51. difference. Therefore, on the condition that the voltage difference between the first and second power supply voltages VDD1 and VDD2 is larger than the threshold voltages of the PMOS 15 transistors PM4 and PM51, the PMOS transistors PM4 and PM51 can be turned on. By turning on the PMOS transistor PM4, the second power supply voltage VDD2 can be supplied to the node N4 connected to its drain terminal. As a result, the PMOS transistor PM2 is non-conductive, and the second power supply voltage VDD2 is not connected to the node N3 that supplies the first power supply voltage VDD1 through the 20 PMOS transistor PM1. In addition, since the node N4 is connected to the drain terminal of the PMOS transistor PM3, the PMOS transistor PM3 becomes the first power supply voltage VDD1 to the gate terminal (node N2), and the second power supply voltage VDD2 is supplied to the drain terminal. status. In addition, the first and second electrical voltages are applied between the gate and drain terminals. 27 1222273 (invention), the voltage difference between the source voltages VDD1 and VDD2. Therefore, on the condition that the voltage difference between the first and second power supply voltages VDD1 and VDD2 is smaller than the threshold voltage of the PMOS transistor PM3, the PMOS transistor PM3 is non-conductive. In addition, the first power supply voltage VDD1 is not connected to the node N4 that supplies the second 5 power supply voltage VDD2 through the PMOS transistor PM4. When the input signal IN is a low-level signal having a voltage level of the reference voltage VSS, the applied voltage level is reversed and becomes an operation state opposite to the foregoing. That is, the reference voltage VSS is applied to the gate terminal and the PMOS transistor PM3 is turned on, whereby the first power supply voltage VDD1 can be applied to the gate terminal and the PMOS transistor PM2 is turned on. Here, the voltage difference between the first and second power supply voltages VDD1 and VDD2 is larger than the threshold voltage of the PMOS transistor PM2. Since the second power supply voltage VDD2 is supplied to the node N3, the PMOS transistors PM4 and PM51 are non-conductive. Thereby, the second power supply voltage VDD2 will not be supplied to the output terminal OUT, and the second power supply voltage VDD2 will not be connected to the node N4 that supplies the first power supply voltage VDD1 through the PMOS transistor PM3. In addition, the PMOS transistor PM1 that applies the voltage difference between the first and second power supply voltages VDD1 and VDD2 between the gate and the non-terminals is based on the voltage difference between the first and 20 second power supply voltages VDD and VDD2 being less than the threshold voltage as Condition is non-conducting. Thereby, the first power supply voltage VDD1 is not connected to the node N3 which is supplied with the second power supply voltage VDD2 through the PMOS transistor PM2. On the other hand, the NMOS transistor NM51 supplies the signal in the same phase as the input signal IN to the gate terminal 12 through the low-level step conversion section 6 described later (Fig. 14). Exclusive conduction control with PMOS transistor PM51. By turning on the PMOS transistor PM51, the second power supply voltage VDD2 can be supplied to its drain terminal. If the PMOS transistor PM52 also has the same threshold voltage, it can be turned on, and a second power supply voltage VDD2 can be supplied to the output terminal OUT. Here, since the NMOS transistor NM51 is non-conducting, an output signal OUT having a voltage level of the second power supply voltage VDD2 can be output. In the case where the PMOS transistor PM51 is non-conducting, the 10 NMOS transistor NM51 is turned on, and a reference voltage VSS is supplied to its drain terminal. The NMOS transistor NM52 is also turned on in the same manner, and a reference voltage VSS is supplied to the output terminal OUT. In the level conversion circuit 1 shown in the embodiment, if the level conversion section 4 on the high voltage side is used, the voltage difference between the first power supply voltage VDD1 and the second power supply voltage 15 VDD2 is larger than the PMOS transistors PM2, PM4, and PM51. , PM52 threshold voltage, so if the gate terminal is controlled by the i and second power supply voltages VDD1, VDD2, it can be used as conducting and non-conducting. Moreover, the level conversion section 4 can be easily constituted by a PMOS transistor. In order to turn on and control the PMOS transistor PM51, the input signal IN that oscillates between the reference voltage 20 VSS and the first power supply voltage vDD1 is level-converted to oscillate between the first power supply voltage VDD1 and the second power supply voltage VDD2. When the signal is transmitted, a stable current path from the second power supply voltage VDD2 to the first power supply voltage VDD1 is not formed. In addition, the middle power supply voltage between the first power supply voltage VDD1 and the second power supply voltage VOD2 is 29 1222273. The third power supply voltage of the voltage range of the invention is not necessary, and it is not accompanied by the i and second power supply voltages VDD1 and VDD2. Recurrent current consumption

In addition, since the circuit is formed between the first power supply voltage 5 VDD1 and the second power supply voltage VDD2 instead of the reference voltage VSS, the applied voltage difference is the voltage difference between the first and second power supply voltages VDD1 and VDD2. . The PMOS transistors PM1 to PM4, which are the first to fourth PM0S transistors, do not need to ensure the withstand voltage of the second power supply voltage VDD2, and can be composed of low withstand voltage components.

10 Further, PMOS / NMOS for the input section of the second circuit group 5

Among the transistors PM51 / NM51, PMOS / NMOS transistors PM52 / NM52 are provided as transistors for ensuring withstand voltage, and only the second power supply voltage VDD2 and the first are applied to each of the transistors PM51, 52 / NM51, and 52. The difference between the 1 power supply voltage VDD1 / the voltage of the first power supply voltage VDD1, 15 can be composed of a low withstand voltage device. Among these low-withstand voltage MOS transistors, the gate oxide film thickness is also thinner, and the circuit operation can be accelerated. Here, when the PMOS transistor PM2 or PM4 is turned on and the second power supply voltage VDD2 is supplied at the node N3 or node 4, the PMOS transistor 20 body PM1 or PM3 must be used to cut off the node N3 or N4 to the first power supply voltage. The path of VDD1. The first to fourth methods of this method will be described below. Figure 2 shows the first method. That is, the PMOS transistors PM1 and PM3 are formed by transistors different from the PMOS transistors PM2, PM4, PM51, and PM52. Non-Conductive Control of PMOS Transistor 30 1222273 发明, Description of Invention In the case of PM1 or PM3, the first power supply voltage VDD1 is generally applied to the gate terminal by a signal from the first circuit group 3. In order to cut off the second power supply voltage VDD2 applied to the drain terminal, the threshold voltages of the PMOS transistors PM1 and PM3 must be regarded as a threshold voltage higher than the voltage difference between the first and second power supply voltages VDD1 and VDD2 5. As long as a transistor having a higher threshold voltage is used instead of the transistors PM2, PM4, PM51, PM52 constituting the PMOS transistor, it is sufficient. Figure 3 shows the second method. That is, the PMOS transistors PM1 and PM3 are composed of the same transistors as the PMOS transistors PM2, PM4, PM51, and PM52. To the gate terminals (nodes N1, N2) of the PMOS transistors PM1 and PM3, a voltage level conversion circuit LS is connected. The signal from the first circuit group 3 is input to the gate terminal through the conversion circuit LS. When the PMOS transistors PM1 and PM3 are non-conductively controlled, a signal of a voltage level VH higher than the first power supply voltage VDD1 is supplied to the gate terminal. If 15 switching circuits LS are set so that the voltage difference between the second power supply voltage VDD2 and the voltage level VH is smaller than the threshold voltage, the PMOS transistor PM1 can be maintained non-conductively when the second power supply voltage VDD2 is applied to the drain terminal. PM3. Figure 4 shows the third method. The third method is a structure in which NMOS transistors NM1 / NM2 are arranged between the PMOS transistor 20 between PM1 and PM2 / between PM3 and PM4. The drain terminal of the PMOS transistor PM1 / PM3 is connected to the source terminal of the NMOS transistor NM1 / NM2 (node 3A / 4A), and the drain terminal of the PMOS transistor PM2 / PM4 is connected to the NMOS transistor NM1 / NM2. Drain terminal (node 3/4). Common supply 31 1222273 玖, description of the invention Give a predetermined bias voltage VG to the gate terminals of the NMOS transistors NM1, NM2. Instead of supplying the bias voltage VB directly, a structure in which the bias voltage VB is supplied through the voltage step-down section 7 may be used. The voltage step-down section 7 has a structure as shown in FIG. 5. Between the second power supply voltage VDD2 and the gate terminals of the NMOS transistors NM1 and NM2, a step-down portion 71 connected to the NMOS transistor connected by a diode in a predetermined number of stages is arranged. The second power supply voltage VDD2 is supplied to the gate terminal (VG = VDD2 — VDN) when the step-down voltage VDN lowered by the step-down section 71 is reduced. In addition to the voltage reduction section 71, a structure capable of reducing or dividing the voltage, such as bonding a diode or a resistance element, can be applied, and a structure in which these are appropriately combined can also be used. Returning to Fig. 4, the specific operation will be described. When the PMOS transistor PM1 is turned on, the first power supply voltage VDD1 is supplied to the node 3A. At this time, the gate terminal voltage VG of the NNi0S transistor NM1 must be a voltage higher than the threshold voltage VthNl of the NMOS transistor NM1 (VG — VDD1 ^ VthNl) after the first power supply voltage VDD1 is added. Accordingly, the NMOS transistor NM1 is turned on and supplies the first power supply voltage VDD to the node 3. With this, the PMOS transistors PM4 and PM51 can be turned on. When the PMOS transistor PM1 is non-conducting, the second power supply voltage VDD2 is supplied to the node 3 through the 20 PM 0s transistor PM2. At this time, the 'NMOS transistor NM1 operates in the saturation region. At the node 3A, a voltage -VthNl) is subtracted from the gate terminal voltage VG minus the threshold voltage VthNl). In order to keep the PM0s transistor pM1 in a non-conducting state, it is required to supply a voltage (VG — VthNl) to the node 3A and a supply voltage of 32 1222273 玖. Invention of the PMOS transistor PM1 gate terminal (node N1) The voltage difference between the first power supply voltage VDD1 is smaller than the threshold voltage VthPl ((VG-VthNl) -VVD1 < VthPl) of the PMOS transistor PM1. PMOS transistor PM3 and NMOS transistor NM2 also perform the same operation. According to the method (3) in Figure 4, if

VthNl ^ VG- VDD1 < VthPl + VthNl ... (1) (VthN2 ^ VG — VDD1 < VthP3 + VthN2) can control the conduction and non-conduction of PMOS transistors PM1 and PM3. The above condition (1) is that the bias voltage VB is the second power supply voltage VDD2, and when directly applied as the gate terminal VG (VG = VDD2), it is VthN 1 S VDD2 — VDD1 < VthP 1 + VthN 1. When the second power supply voltage VDD2 receives a step-down voltage of 15 VDN through the step-down voltage section 71 and is applied as a gate terminal (VG = VDD2-VDN), it is

VthN 1 + VDN $ VDD2 — VDD1 < VthP 1 + VthN 1 + VDN. Furthermore, if there are voltage sources other than the first and second power supply voltages VDD1 and VDD2, other voltage sources may be considered. 20 Here, by using the voltage step-down section 71 or other voltage source, if the gate terminal voltage VG can be set lower, an NMOS transistor with a lower threshold voltage VthNl can be used. In addition, the types of transistors that can be used as the NMOS transistors NM1 and NM2 can be expanded. When the PMOS transistors PM1 and PM3 are non-conducting, a voltage stepped down by the first transistor 33 1222273 发明, description of the invention is supplied to the PMOS transistor PM1 or PM3. When the PMOS transistors PM1 and PM3 have the same threshold voltage as the PMOS transistors PM2, PM4, and PM51, the PMOS transistors PM1 and PM3 can be controlled to be non-conductive.

5 In the case of any of the first to third methods, if the PMOS transistors PM1 and PM3 are formed with threshold voltages higher than the threshold voltages of the PMOS transistors PM2, PM4, and PM51, the PMOS transistors can be easily performed. Non-conduction control of PM1 and PM3. In particular, when the NMOS transistors NM1 and NM2 are provided, the voltage range of the bias voltage VB can be further expanded. 10 Fig. 6 shows the fourth method, that is, the construction of controlling the voltage of the gate terminals in response to the voltages supplied to the drain terminals of the PMOS transistors PM1 and PM3. After the combination, the potential of the N well was adjusted. The PMOS transistors PM1 and PM3 can each have the same circuit structure. First, the gate voltage control unit 11 will be described. Between the gate terminal (node N1A) and the drain terminal (node N3) of the PMOS transistor PM1 15, a PMOS transistor PM7 having a gate terminal connected to the first power supply voltage VDD1 is connected. When the threshold voltage of the second power supply voltage VDD2 is higher than the first power supply voltage VDD1, it has a gate terminal (node N1A) that supplies the second power supply voltage VDD2 to the PMOS transistor PM1, and keeps the PMOS transistor PM1 at 20 to be non-conductive Function. The signal from the first circuit group is input to the gate terminal (node N1A) of the PMOS transistor PM1 through the PMOS / NMOS transistor PM5 / NM3. The gate terminal of the NMOS transistor NM3 is connected to a first power supply voltage VDD1. The gate terminal (node N11) of the PMOS transistor PM5 is 34 1222273. Description of the invention The PMOS transistor PM6 connected to the gate terminal through the first power supply voltage VDD1 and the input to the gate terminal (node N13) are from the first circuit. The NMOS transistor NM4 of the group signal or its in-phase signal is connected to the PMOS transistor PM1 and its terminal (node N3). 5 Here, in addition to the input of the high-level signal having the first power supply voltage VDD1 in the gate terminal (node N13) of the NMOS transistor NM4, it is also considered to input the signal stepped down by the step-down circuit B11 as the first Signal of 1 circuit group. The gate terminal (node Nil) is connected to the reference voltage VSS through the NMOS transistor NM5 10. In the gate terminal of the NMOS transistor NM5, the signal from the first circuit group is input by the inverter gate IU inversion. When the signal from the first circuit group is at a low level, the signal must be supplied to the gate terminal (node N1A) of the PMOS transistor PM1 through the PMOS / NMOS transistor PM5 / NM3. For the NMOS transistor NM3, the gate terminal is connected to the first power supply voltage VDD1, so the input signal can be turned on if the voltage level below the threshold voltage of the NMOS transistor NM3 is relative to the first power supply voltage VDD1. For PMOS transistor PM5, the gate terminal is connected to node N3 through PMOS / NMOS transistor PM6 / NM4. As for the 20 NMOS transistor NM4, it is non-conducting because a low-level signal is input to the gate terminal. The PMOS transistor PM6 is also connected to the first power supply voltage VDD through the gate terminal, and the node N3 moves to the first power supply voltage VDD1 and becomes non-conductive as the PMOS transistor PM1 is turned on, and then the path from the point N3 is cut. Off. In contrast, the NMOS transistor NM5 35 1222273 玖, invention description, because the input industry is turned on by the high-level signal inverted at the gate terminal. As a result, the PMOS transistor PM5 is also turned on. A low-level signal is supplied to the node N1A, and the PMOS transistor PM1 is turned on. When the signal from the first circuit group is at a low level, the voltage of the node N3 at the 5 level can be raised to the second power supply voltage VDD2 by the conduction of the PMOS transistor PM2. Figures 7 and 8 show the characteristics of the voltage level of the node N1A and the node N11 with respect to the voltage level of the second power supply voltage VDD2 supplied to the node N3. Here, the NMOS transistor NM5 is non-conducting because it supplies a low-level voltage to the 10 gate terminal. In addition, the PMOS transistors PM1, PM6, and PM7 are those having the same threshold voltage VthP. In addition, a description will be given assuming that the voltage level of the first power supply voltage VDD1 is at the node N13. If the voltage V (N3) of the node N3 is less than the voltage of the first power supply voltage VDD1 plus the threshold voltage VthP of the PMOS transistor PM6 (V (N3) < 15 VDD + VthP), when the PMOS transistor PM6 is non-conducting, NMOS The transistor NM4 is turned on in the saturation region. Therefore, the node Nil is supplied with the first power supply voltage VDD1 minus the threshold voltage VthN of the NMOS transistor NM4 (V (N11) = VDD1-VthN) (⑴ in Fig. 7). Here, if the NMOS transistor NM4 has a threshold voltage VthN that is deeper than the PMOS transistor PM5, the PMOS transistor PM5 is turned on.

In the above description, although the supply of the first power supply voltage VDD1 has been described as the voltage V (N13) of the node N13, the voltage V (N13) can also be used as the voltage stepped down by the step-down circuit B11. At this time, the node Nil will supply a lower voltage (V (N13)-VthN) ((II) in Fig. 7). Compared with the threshold voltage of the transistor PM5 of PMOS 36 1222273 (invention description), NMOS When the threshold voltage of the crystal NM4 is the same or lower, the PMOS transistor PM5 can also be turned on. Also, the PMOS transistor PM7 is also non-conducting, and the second power supply voltage VDD supplied to the node N3 is not supplied to the node N1A. 5 Therefore, at the gate terminal (node N1A) of the PMOS transistor PM1, a high-order signal is supplied from the first circuit group through the PMOS transistor PM5. Usually, this signal has the voltage level of the first power supply voltage VDD1 (Fig. 8). The voltage difference between the gate and drain terminals of the PMOS transistor PM1 is less than the threshold voltage and remains non-conductive. And a current path from the node 10 N3 to the first power supply voltage VDD1 will not be formed. If the voltage V (N3) of the node N3 is higher than the voltage of the first power supply voltage VDD plus the threshold voltage VthP of the PMOS transistor PM6 (v (N3) g VDD + VthP), the PMOS transistor PM6 is applied above the threshold voltage VthP Voltage and turn on, and the node Nl 1 and the node N3 are turned on 15 (V (N11) = V (N3)) (Figure 7). The voltage V (N11) becomes the second power supply voltage VDD2, and the PMOS transistor M5 becomes non-conductive. On the other hand, the PMOS transistor PM7 with the same threshold voltage VthP is turned on, and the node N1A is turned on with the node N3 (V (N1A) = V (N3)) (Figure 8). The voltage V (N1 A) becomes the second power supply voltage VDD2. The gate and drain terminals of the PMOS transistor 20 PM1 are at the same potential and remain non-conductive. And there will be no current path from node N3 to the first power supply voltage VDD1. As described above, if the gate voltage control unit 11 (Figure 6) in the fourth method, when the PMOS transistor PM1 (PM3) is not When turned on, even if the second power supply voltage VDD2 is directly applied to the drain terminal (node N3 (N4)) at 37 1222273 发明, the invention description, it can be switched according to the second power supply voltage VDD2 relative to the first power supply voltage VDD1. The voltage applied to the gate terminal (node N1A) is maintained, while the PMOS transistor PM1 (PM3) remains non-conductive. In addition, no unnecessary current path is formed from the drain 5 terminal (node N3 (N4)) to the first power supply voltage VDD1, and unnecessary current consumption can be prevented. The switching system of the voltage applied to the gate terminal (node N1A), if the threshold voltage VthP of the PMOS transistor PM6 and PM7 is the same as that of the PMOS transistor PM1 (PM3), the drain terminal (node N3 (N4)) is used. This voltage allows the PMOS transistor 10 PM1 (PM3) to switch from the voltage at which the drain terminal is turned on to the first power supply voltage side. In addition, the non-conduction maintenance of the PMOS transistor PM1 (PM3) can be performed stably regardless of the similarities and differences between the threshold voltages of the PMOS transistor PM1 (PM3) and the PMOS transistor PM2, PM4, and PM51. 15 The propagation control of the node N1A of the signal from the first circuit group can be performed by the conduction control of the PMOS transistor PM5. The second power supply voltage VDD2 supplied to the node N1A is not applied to the first circuit group by making the PMOS transistor PM5 non-conductive. Furthermore, by operating in the saturation field of the NMOS transistor NM3, the voltage applied to the first circuit group is limited to the voltage of the 20th power supply voltage VDD1 minus the threshold voltage without applying an overvoltage. Next, the N-well potential limiter 9 will be described. As shown in FIG. 6, in the level conversion circuit 1, the power supply voltage of the high-level side level conversion section 4 and the gate voltage control section 11 is the first power supply voltage VDD1. Generally, the potential of the N-well also biases the first power supply voltage. . However, the PMOS transistor PM1 (PM3) 38 1222273 (1) and (1) indicate that when PM5 to 7 are supplied with the second power supply voltage VDD2 to Nia, due to the voltage difference between the first power supply voltage VDD1 and the second power supply voltage VDD2, Therefore, a forward current flows from the p-type drain terminal to the N well Nw through the forward-biased junction. In order to avoid this flow, 5 bits of n-well power must be controlled. The N-well potential control unit 9a of the first specific example shown in FIG. 9 has a PMOS transistor PM8A, the source terminal of which is connected to the first power supply voltage VDD1, and the drain terminal and the rear gate terminal are connected to N-well Nw. And a PMOS transistor PM9A, the source terminal is connected to the gate terminal, the 10 drain terminal and the rear gate terminal are connected to the N well NW, and the gate terminal is connected to the first power supply voltage VDD1. The PMOS transistor PM8A is precisely connected to the PMOS transistor control section of the gate terminal (node pi) to control conduction and non-conduction. The PMOS transistor control section includes an NMOS transistor NM6A and 15 PMOS transistor PM10A, and a first voltage step-down section 91 is provided as necessary. NMOS transistor NM6A series, the drain terminal is connected to node N3, the source terminal is connected to the gate terminal (node P1) of the PMOS transistor PM8A through the first voltage step-down section 91, and the gate terminal is connected to the first power supply voltage VDD1. PMOS transistor PM10A series, the source terminal is connected to nodes N3 and 20, the drain terminal is connected to the gate terminal and the rear gate terminal of PMOS transistor PM8A are connected to the N well NW, and the gate terminal is connected to the first power supply voltage VDD1 ° 1 The voltage step-down section 91 is to step down the voltage from the source terminal of the NMOS transistor NM6A, and then supply it to 39 1222273 of the PMOS transistor PM8A. 发明 Description of the gate terminal (node P1). FIG. 9 shows a specific example in which the first voltage step-down unit 91 is incorporated. A specific example (A) is a step-down step in which a predetermined number of diodes are connected in series. By appropriately setting the predetermined number of diodes, when the PMOS transistor PM8A is turned on, a voltage equal to or lower than the threshold voltage of the first power supply voltage VDD1 minus the threshold voltage is supplied to the gate terminal (node P1) of the PMOS transistor PM8A. The specific example (B) divides the voltage of the source terminal of the NMOS transistor NM6A by a resistance element. If the voltage division ratio is appropriately set, a voltage lower than the threshold voltage of the first power supply voltage VDD1 minus the threshold voltage of the PMOS transistor PM8 A (node P1) can be supplied. The N-well potential control section 9B of the second specific example shown in FIG. 10 is a PMOS transistor control section, and a second voltage step-down section 92 is provided instead of the first specific example 9A (FIG. 9). Voltage step-down section 91. In the PMOS transistor control section, the 15 terminals of the NMOS transistor NM6B series source are directly connected to the gate terminal (node P1) of the PMOS transistor PM8B, and the gate terminal is connected to the first power supply through the second voltage step-down section 92 Voltage VDD1. The second voltage step-down unit 92 steps down the first power supply voltage VDD1 and biases the gate terminal of the NMOS transistor NM6B. With this, 20 can output the voltage appropriately reduced by the source terminal of the NMOS transistor NM6B and supply it to the node P1. A specific example of the second voltage step-down section 92 shown in FIG. 10 is the same as a specific example of the first voltage step-down section 91. By connecting a predetermined number of diodes in series (specific example (A)), and using a resistance element to perform the first power supply voltage VDD1 of 40 1222273 玖, the invention description divides the voltage (specific example (B)) to obtain a reduced voltage Voltage. Fig. 11 shows the switching waveforms of the potential γ (N3) of the node N3, the potential V (NW) of the NW NW and the PMOS transistor PM8A in the N-well potential control sections 9A and 9B (Figs. 9 and 10). Gate voltage V (P1) 5. In Figure 11, the case where the threshold voltages of NMOS / PMOS transistors are slightly equal (VthN and Vthp) is taken as an example. If the voltage V (N3) is equal to or higher than the i-th power supply voltage VDD1 plus the threshold voltage VthP (V (V3) ^ vdDI + VthP), the PMOS transistors PM10A and PM10B are turned on and the voltage ν (P1) is biased. The voltage is 10 V (N3), and it is regarded as the second power supply voltage VDD2. The PMOS transistors PM8A and PM8B are non-conductive. On the other hand, the PMOS transistors PM9A and PM9B are turned on, and the N-well potential V (NW) becomes the voltage V (N3). That is, it becomes the second power supply voltage VDD2. If the voltage V (N3) is reduced to a voltage smaller than the first power supply voltage VDD1 plus the threshold voltage VthP (V (N3) < VDDl + VthP), the P9 transistor PM9A, PM10A, PM9B, PM10B is Non-conducting. On the other hand, the NMOS transistors NM6A and NM6B are turned on. Before the voltage V (N3) is reduced to the voltage of the gate terminals of the NMOS transistors NM6A and NM6B minus the voltage of the threshold voltage VthN, since the 20 NMOS transistors NM6A and NM6B perform the saturation operation, the voltage of the source terminal is roughly It is fixed to a voltage obtained by subtracting the threshold voltage VthN from the voltage of the gate terminal. If the voltage is reduced again, the NMOS transistors NM6A and NM6B will conduct a linear action and turn on, and the voltage V (N3) will be output to the source terminals of the NMOS transistors NM6A and NM6B as usual. 41 1222273 发明, description of the invention • '-.,' Here, the voltage supplied to the gate terminal of the NMOS transistor NM6A, NM6B is the first power supply voltage VDD1 (Figure 9), or the voltage is stepped down by the first power supply voltage VDD1. Voltage (Figure 10). This voltage is supplied to the gate terminals (node P1) of the PMOS transistor PM8A, 5 PM8B directly (Figure 10) or after voltage reduction (Figure 9). When the first and second step-down sections 91 and 92 are not provided, the threshold voltage VthN of the NMOS transistors NM6A and NM6B minus the first power supply voltage VDD1 is set as the upper limit, and the voltage V (P1) of the node P1 is set. When the threshold voltages of the NMOS transistors NM6A, NM6B and PMOS transistors PM8A 10 and PM8B are slightly equal, the potential difference between the gate and source of the PMOS transistors PM8A and PM8B will be applied above the threshold voltage VthP, and will be turned on to supply the first 1 Power supply voltage VDD1 in N well NW. In addition, even if the threshold voltages of the NMOS transistors NM6A and NM6B and the PMOS transistors PM8A and PM8B are different, at least one of the first or 15 second voltage step-down sections 91 and 92 can be provided, which can fully make use of The voltage V (P1) of the node P1 is stepped down, and the PMOS transistors PM8A and PM8B are turned on. The N-well potential control unit 9C of the third specific example shown in FIG. 12 is the first and second specific examples 9A and 9B (FIGS. 9 and 10). The crystal PM8A and PM8B have a structure in which the connection relationship between the gate terminals of the PMOS transistors PM9A and PM9B and the first power supply voltage VDD1 is inverted. That is, the NMOS transistor NM6C and the PMOS transistor PM10C are set between the gate terminal (node P2) of the PMOS transistor PM9C and the first power supply voltage VDD1, and 42 1222273 玖, invention description NMOS transistor NM6C gate terminal The child is connected to node N3. The gate terminals of the PMOS transistors PM8C and PM10C are connected to the node N3. At this time, the first voltage step-down section 91 and the second voltage step-down section 92 can be connected in the same manner as in the first and second specific examples 9A and 9B. That is, the first voltage 5 step-down section 91 may be provided between the NMOS transistor NM6C and the node P2. The second voltage step-down section 92 is connected between the gate terminal of the NMOS transistor NM6C and the node N3. Regarding the third specific example 9C, FIG. 13 shows a waveform showing the relationship between the N-well potential V (NW) of the voltage V (N3) and the voltage V (P2) of the node P2. When the first and second voltage step-down sections 91 and 92 are not provided, the voltage V (N3) is lower than the first power supply voltage VDD1 plus the threshold voltage VthN, and the NMOS transistor NM6C performs a saturation operation. The voltage V (P2) of the gate terminal (node P2) of the PMOS transistor PM9C is the voltage of the supply voltage V (N3) minus the threshold voltage VthN. Under the condition that the two threshold voltages of NMOS / PMOS are slightly equal (VthN and VthP), the PMOS transistor PM9C is turned on, and the N-well potential V (NW) is the voltage V (N3). Since the voltage V (N3) at this time is the second power supply voltage VDD2, the N-well potential V (NW) is also the second power supply voltage VDD2. When the voltage V (N3) is greater than the voltage of the first power supply voltage VDD1 plus a threshold voltage of 20 VthN, the NMOS transistor NM6C performs a linear operation. The first power supply voltage VDD1 is supplied to the gate terminal (node P2) of the PMOS transistor PM9C. Then, the PMOS transistor PM9C is turned on, and a voltage V (N3) is supplied, that is, the second power supply voltage VDD2 to the N-well NW. In addition, since the operation of the first and second voltage step-down sections 91 and 92 is 43 1222273 发明, invention _ Ming ^ ^ ^ ^ y The use and effect are the same as those of the first and second specific examples 9A and 9B. Therefore, the description is omitted below. Here, if the voltage V (N3) is greater than the first power supply voltage VDD1 plus the threshold voltage VthN according to the effect of the voltage reduction by the first voltage step-down section 91, the voltage V (P2) is set to The industry level 5 is a voltage level stepped down by the first power supply voltage VDD1 through the first voltage step-down section 91 (Fig. 13, (II)), and if the voltage is dropped by the second voltage step-down section 92, the voltage V (P2) is set to the voltage level at which the first power supply voltage VDD1 is subtracted from the voltage level stepped down by the second voltage step-down section and then the threshold voltage VthN is subtracted (Fig. 13, (I)). 10 As described above, according to the first and second specific examples (Figures 9 and 10) and the third specific example (Figure 12) of the N-well potential control section, if the first voltage step-down section 91 is provided, The voltage output from the source terminal of the NMOS transistor NM6A to NM6C can be stepped down. If the second voltage step-down section 92 is provided, in the NMOS transistors NM6A 15 to NM6C, the predetermined voltage applied to the gate terminal can be stepped down by the first power supply voltage VDD1, and the source terminal for saturation operation can be reduced. The voltage value is stepped down. The voltage supplied to the nodes PI and P2 can be stepped down to the voltage of the first power supply voltage VDD1 minus the threshold voltage VthN 20 and the step-down voltage by the first or second voltage step-down sections 91 and 92. Furthermore, since the step-down performed by the first step-down section 91 becomes a fixed voltage value, the NMOS transistors NM6A to NM6C can also perform a step-down step of a predetermined voltage in the field of linear operation. If the first voltage step-down section 91 and the second voltage step-down section 92 are provided at the same time, the respective step-down voltages are added, and when the PMOS transistor PM8A, PM8B, 44 1222273 玖, invention description-吣 PM9C can be turned on, it can be applied The voltages V (P1) and V (P2) at the gate terminals (nodes PI and P2) are effectively reduced. The same effect can be achieved even if the first voltage step-down section 91 and the second voltage step-down section 92 are both provided simultaneously or separately. 5 PMOS transistor PM1 (PM3), PM5 to PM7, the potential V (NW) of the N well NW is controlled by the voltage V (N3) (V (N4)) applied to the node N3 (N4). If V (N3) (V (N4)) < VDDl + VthP is the first power supply voltage VDD1, V (N3) (V (N4)) 2VDDl + vthP is the voltage V (N3) (V (N4)) Constantly biased. As a result, N well NW will become floating. Also, no forward bias is applied between the interface with the drain terminal. Therefore, when the level is switched from the first circuit group 3 to the second circuit group 5, the potential V (NW) of the N well NW can be set reliably, and no unnecessary forward bias current flows. A stable circuit operation can be obtained with low current consumption. 15 FIG. 14 shows a specific example of the low-level step conversion section 6 in the step conversion circuit 1 of the embodiment. The input signal IN having the amplitude of the first power supply voltage VDD1 is converted into a signal having the amplitude of the bias voltage VB. The input signal IN is input to the inverter terminal composed of the PMOS transistor PM62 and the NMOS 20 transistor NM62 and the gate terminal of the NMOS transistor 61. The output terminal of the inverter gate is connected to the gate terminal of the NMOS transistor NM63. The source terminals of NMOS transistors NM61 and NM63 are connected to the reference voltage VSS, and the drain terminals are connected to the drain terminals of PM61 and PM63, respectively. 45 1222273 of PMOS transistors PM61 and PM63 发明, description of the invention The gate terminals are connected to the drain terminals of other transistors, and the source terminals are also connected to the bias voltage VB through the step-down portion 71 as necessary. And the connection point of the PMOS transistor PM63 and the NMOS transistor NM63 outputs the level-converted signal. 5 Also, input a low-level input signal IN. By turning on the NMOS transistor NM61 and using the gate terminal voltage of the PMOS transistor PM63 as the reference voltage VSS, the PMOS transistor PM63 can be turned on. In addition, the low-level signal inverted by the inverter gate is input to the gate terminal of the NMOS transistor NM63, and the NMOS transistor NM63 is non-conductive. Therefore, the output signal 10 passes through the PMOS transistor PM63 and becomes the bias voltage VB or its step-down voltage. Here, the output signal is input to the gate terminal of the PMOS transistor PM61 and makes the PMOS transistor PM61 non-conductive. The input signal IN is a low-level signal to which the reference voltage VSS is input. In this case, the NMOS transistor NM61 is non-conductive and cuts off the path from the gate terminal of the PMOS transistor PM63 to the reference voltage VSS. On the other hand, since the signal output by the high-level signal inverted by the inverter gate is input to the gate terminal of the NMOS transistor NM63, the NMOS transistor NM63 is turned on. Therefore, the output signal is transmitted to the reference voltage VSS through the NMOS transistor NM63. The output signal is input to the gate terminal of the PMOS transistor PM61 and turns on the PMOS transistor PM61, and the PMOS transistor PM63 is kept non-conductive. The high level of the output signal is the bias voltage VB or its step-down voltage. By taking this voltage level as a voltage level higher than the first power supply voltage VDD1, the gate terminal of the NMOS transistor NM51 becomes deeply biased 46 1222273, and high-speed operation with an increase in driving capability can be expected. INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device which operates between a first circuit group operating at a first power supply voltage and a second circuit group operating at a second 5 power supply voltage higher than the first power supply voltage. In order to perform signal conversion between phases, a level conversion circuit capable of operating with the power source carried by the first power supply voltage and the second power supply voltage is provided, and there is no frequent current consumption and level conversion can be performed. Brief description of the L diagram 3 10 FIG. 1 is a circuit diagram showing an embodiment of the present invention. Fig. 2 is a circuit diagram showing a first method for preventing the PMOS transistor constituting the level conversion circuit from being turned on incorrectly. Fig. 3 is a circuit diagram showing a second method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. 15 Fig. 4 is a circuit diagram showing a third method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. FIG. 5 shows a specific example of the third method in FIG. 4. Fig. 6 is a circuit diagram showing a fourth method for preventing erroneous conduction of the PMOS transistor constituting the level conversion circuit. 20 Figure 7 shows the characteristics of the gate terminal voltage of the PMOS transistor PM5 in the fourth method. Fig. 8 shows the characteristics of the gate terminal voltage of the PMOS transistor PM1 in the fourth method. Fig. 9 is a circuit diagram showing the first 47 1222273 of the N-well potential control section in the fourth method, and a description of the invention. Fig. 10 is a circuit diagram showing a second specific example of the N-well potential control section in the fourth method. Fig. 11 shows the switching of the well potential of the N-well potential control unit 5 of the first and second specific examples.

Fig. 12 is a circuit diagram showing a third specific example of the N-well potential control section in the fourth method. Fig. 13 shows a switchover of the well potential of the N-well potential control section of the third specific example. 10 FIG. 14 is a circuit diagram showing a level conversion section for driving the low-voltage side of the NMOS transistor NM51 in the level conversion circuit of the embodiment. FIG. 15 is a circuit diagram showing a level conversion circuit of the conventional technology. [The main components of the diagram represent the symbol table] 1... Level conversion circuit

11. ..Gate voltage control section 3 ... 1st circuit group 4 ... High-voltage side level conversion section 5 ... 2nd circuit group 6 ... Healthy side level conversion section 7 .... Voltage step-down section 71 ... Voltage section 9,9A-C ... N-well potential control section 91 ... First voltage step-down section 92 ... Second voltage step-down section 48 1222273 玖, Description of the invention 105 ~ 111 ... Resistance element B11 ... Step-down circuit 111, 131 ... inverter gate IN ... input signal LS ... voltage level conversion circuit

Nl-4, N11, N13, N1A, N3A-4A, NP1 ~ P2 ·· Nodes NM1 ~ 5, NM6A4C, NM51 ~ 52, NM61 ~ 63 ... NMOS transistor NW ... N well OUT ... output signal PM1 ~ 7, PM8AC, PM9A-C, PM10A-C, PM51 ~ 52, PM61 ^ 63 ... PMOS transistor VB ... bias voltage VDD1 ... first power supply voltage VDD2 ... second power supply voltage VDN … Buck voltage VH1 ~ 3 ... High voltage level VL1 ~ 3 ... Low voltage level VSS ... Reference voltage 49

Claims (1)

1222273 Patent application, patent application ^ 丨 h kinds of semiconductor devices, which have the reference voltage and the first! Features of the i-th circuit group operating as a power supply between power supply voltages and the second circuit group acting as a power supply operating between a reference voltage and a second power supply voltage having a voltage level higher than the aforementioned first power supply voltage. 5 consists of: a voltage-controlled high-voltage element of the first conductivity type, which performs the output control of the second power supply voltage in the input section of the second circuit group; and a one-stage conversion circuit, which is performed by the first The first circuit group goes to the interface of the second circuit group of the tenth circuit, and operates between the first power supply voltage and the second power supply voltage as a power source, and turns on and controls the voltage-controlled South House side component; and the level The conversion circuit includes: a voltage-controlled first element of the first conductivity type, which is provided between the aforementioned voltage-controlled high-voltage side element and the aforementioned voltage power source ', and is supplied to the voltage-controlled high-voltage side element when it is turned on; The first power supply voltage; and a voltage-controlled second element of the first conductivity type, which are provided on the voltage-controlled high-voltage side element and the second voltage. When the voltage-controlled high-side element is made non-conductive between 20 power sources, the second power source voltage is supplied. 2. The semiconductor device according to item 1 of the scope of patent application, wherein the level conversion circuit is connected to the aforementioned circuit group in the aforementioned voltage-controlled first element. 50 1222273 Patent application scope 3. If the semiconductor device of the first or second patent application scope, the level conversion circuit further includes a first conductive type voltage control type third element, which is set at the aforementioned voltage Between the control-type second element and the aforementioned first power supply voltage and supplying the aforementioned power supply voltage when the voltage-controlled second element is turned on; and a voltage-controlled fourth element of the first conductivity type, It is provided between the voltage-controlled second element and the second power supply voltage, and when the voltage-controlled second element is rendered non-conductive, the second power source voltage is supplied. 4. The semiconductor device according to item 3 of the scope of the patent application, wherein the voltage-controlled fourth element is turned on because the first voltage-controlled voltage supplied by the aforementioned voltage-controlled i-th element is supplied, and the second voltage-controlled The element supplies the second power supply voltage instead of the conductor. 15 5. If the vehicle is identified in item 3 of the scope of patent application, the conductor device of the upper shell and the upper shell of the cow is identified, in which the level conversion circuit is in the aforementioned voltage complaint. Connected to the aforementioned circuit group. 6. A semiconductor device 'system, a first circuit group having a reference voltage and a S1 power supply voltage as a power source, and a second power supply voltage between the reference voltage and a level higher than the aforementioned power supply voltage The second power source that operates between power sources is characterized in that it includes: an output PMOS transistor, which enters the segment, and is borrowed from the gate terminal to supply the power set in the second circuit group to the first power supply voltage. And continuity, 51 20 1222273, who applied for the patent scope and performed the output of the aforementioned second power supply voltage; and the bit & conversion circuit is the interface from the aforementioned first circuit group to the aforementioned second circuit group, and in the aforementioned section The power supply operates between the power supply voltage and the second power supply, and controls the output pM0s 5 transistor. The level conversion circuit includes: a first PMQS transistor, which is configured by the i power supply The voltage is in the path of the gate terminal of the output PM0S transistor, and the controller is turned on by supplying the first signal 10 from the aforementioned circuit group at the gate terminal; The second PMOS transistor is arranged in a path from the aforementioned second power supply voltage to the gate terminal of the output PMOS transistor described above, and is turned on by supplying the first signal of the aforementioned first power voltage to the gate terminal; 15 A third PMOS transistor is arranged in the path from the first power voltage to the gate terminal of the second PMOS transistor, and the controller is turned on by supplying the second signal from the first circuit group to the gate terminal. ; And a fourth PMOS transistor 'is arranged in the path from the aforementioned second power supply voltage of 20 to the gate terminal of the aforementioned second PMOS transistor, and is supplied to the gate terminal through the aforementioned first or second PMOS transistor The aforementioned first power supply voltage or the second power supply voltage becomes conductive or non-conducting; and one of the aforementioned first and third PMOS transistors is conductive 52 1222273. Patent application scope ':: L ...地 控制。 Control. 7. The semiconductor device according to item 6 of the scope of patent application, wherein the first signal and the second signal are logic signals which are mutually inverted. 8. The semiconductor device according to item 6 of the patent application scope includes: a 1NM0S transistor, which is arranged in the path from the aforementioned 1PM0s transistor to the aforementioned 2PM0S transistor, and is arranged to the aforementioned output PMOS transistor The gate terminal or the path to the point where the gate terminal diverges; and a 2NM0S transistor, which is located in the path from the 3Pm0s transistor to the 4PM0S transistor, The gate terminal of the 2PM0S transistor or the path up to the divergence point of the gate terminal; and the aforementioned first or 2NM0S transistor system often applies a predetermined bias voltage to the gate terminal, and the first Or the 31st transistor is turned on by the first or second signal, and when the first or third PM0S transistor receives non-conduction control, the first or second signal is used to make the first The voltage of the drain terminal of the first or second NMoS transistor is stepped down and then supplied to the aforementioned third or third PMOS transistor. 9. The semiconductor device according to item 8 of the application, wherein the gate terminals of the second and second NMOS transistors are connected to a predetermined bias voltage source. 10. If the semiconductor device according to item 9 of the patent application scope further has a voltage step-down section, it is arranged in the path from the aforementioned predetermined bias voltage source to the gate terminal of the aforementioned 及 and 苐 2NMOS transistors. 53 1222273 Patent application scope 11. If the patent application scope item 10, the semi-corporeal arrangement, the aforementioned voltage step-down part is a diode formed by a diode element or a diode_position, or the aforementioned two The polar body element is connected with or combined with the electric crystal and the hungry earth. 12. The semiconductor device according to any one of claims 9 to u in the scope of the patent application, wherein the predetermined bias voltage source is a voltage source from the aforementioned ’4 2 or a voltage source externally supplied. 13. The semiconductor device according to item 6 of the scope of patent application, wherein the u-th transistor system has a higher threshold than the aforementioned output PMOS transistor, the aforementioned second PMOS transistor, and the aforementioned fourth pMOS transistor. Voltage. a The semiconductor device according to item 6 of the patent application scope further has a -gate voltage control section, which is provided at each gate terminal of the jth and 3pMos transistors described above, and when applied to the i or When the aforementioned second power voltage of the drain terminal of the 3pM0s transistor is greater than the aforementioned first power voltage plus the first predetermined voltage, the voltage of the aforementioned gate terminal is set to the aforementioned second power voltage, and when applied When the second power supply voltage of the drain terminal of the first or third PMOS transistor is less than the voltage of the first power supply voltage plus the predetermined voltage, the voltage of the gate electrode is set to the first power supply voltage. 15. If the semiconductor device according to item 14 of the patent application scope, wherein the voltage between the i-th power supply voltage and the first predetermined voltage is the first or third PMOS transistor from the non-electrode side to the first power supply voltage Side voltage. 54 1222273 For patent application, please apply for the full-time semi-conductor of the 14th item, as described above. The above-mentioned \ Predetermined electricity μ When the aforementioned 丨 or 3PMGS transistor starts from the drain terminal side to the aforementioned first power supply On the voltage side, it corresponds to the threshold voltage of the first! Or the third PMOS transistor. 17. For example, the semiconductor device of the "item 14", wherein the closed-electrode control unit is provided with the first circuit group and the aforementioned circuit. There is a first gate voltage control unit between the gate terminal of the i-th or the third PMOS transistor, and when the gate terminal of the aforementioned! Or the third PMOS transistor is set to the aforementioned second power source, 'may To prevent the second power supply voltage from being applied to the first circuit group by the terminal between the first or third PMOS transistor, and when the gate terminal of the third or third PMOS transistor is set to the third power supply voltage, The gate terminal of the first circuit group and the i or 3 PMOS transistor can be turned on. 15 18. For the semiconductor device according to item 17 of the patent application scope, wherein the μ-pole voltage control section has a 5th pMOS transistor, The 5th pM. s Transistor system The drain terminal and the source terminal are connected to the terminal side of the aforementioned! circuit group and the aforementioned first or third transistor, respectively. 20 19. For a semiconductor device in the 17th scope of the patent application, Wherein, the U-th electrode transistor has a 3rd NMOS transistor, and the 0s transistor system has no terminal and source terminal connected to the i-th circuit group side and the first or third PMOS transistor respectively. The gate terminal side and the closed terminal connected to the aforementioned first power supply voltage. 20. For the semiconductor device of the 18th in the scope of patent application, in which the voltage between 55 volts and the patent scope is the same as the first Or The voltage control section has a second voltage control section, and the 3PM0S transistor is used to record the second power supply voltage when the power supply voltage is set. What is the electricity of 5PM0S transistor? The intermediate terminal is set to the aforementioned first power source $ Said the voltage of the threshold voltage of the 5PM0S transistor 22. For the semiconductor device of the 20th scope of the patent application, wherein the second transistor, the 6PMOS electrode voltage control section has a 6PMMOS source terminal And the drain terminal are respectively connected to the drain terminal side of the aforementioned third or third PMOS transistor and the gate terminal side of the aforementioned 5pMOS transistor, and the gate terminal is connected to the aforementioned power source 23. The semiconductor device according to item 22, wherein the second gate voltage control section has a fourth PMOS transistor, and the drain terminal and the source terminal are connected to the negative terminal side of the first or 3PMMOS transistor, respectively. And the gate terminal side of the aforementioned 5th PMOS transistor, and the gate terminal is controlled by the aforementioned first or second signal and its in-phase signal. 24. If the semiconductor device according to item 23 of the scope of patent application, wherein the gate terminal of the fourth NMOS transistor is applied with the aforementioned first power supply 56 1222273, the patent application voltage is applied or the voltage is stepped down by the aforementioned first power supply voltage The voltage. 25. If the semiconductor device in the 24th scope of the application for a patent, further has a voltage step-down section 'depresses the voltage level of the aforementioned first or second signal or its in-phase signal' and outputs it as the aforementioned step-down voltage By. 5 26. The semiconductor device according to item 20 of the patent application scope, wherein the second gate voltage control section has a 5NMMOS transistor, and the 5NmMOS transistor system has a drain terminal and a source terminal connected respectively. At the gate terminal side and the reference voltage of the aforementioned 5PM0S transistor, the gate terminal is controlled by the inverted signal of the aforementioned first or second signal. 1〇27. If the semiconductor device under the scope of patent application No. 6, 18, or 22 has an N-well potential control unit, when the aforementioned second power supply voltage is greater than the aforementioned first power supply voltage plus a second predetermined voltage , The potentials of the aforementioned 丨, 3, 5 and 6 PM0S transistor wells when the aforementioned second power supply voltage is applied to the drain terminal are set to the aforementioned 2 15 1 source voltage, and less than When the voltage of the first power supply voltage plus the second predetermined voltage is set, it is set to the power supply voltage. For example, the semiconducting device of the 27th in the scope of patent application, where the μ well potential control unit has: 20-8th PMOS transistor, the source terminal is connected to the aforementioned π source voltage, and the drain terminal and the rear open terminal The n-pole is connected to the aforementioned ν well;-the 9th PMOS transistor 'system source terminal is connected to the aforementioned] or the OS transistor's non-terminal, and the non-electrode and the rear terminal are connected to the aforementioned N-well, And the open terminal is connected to the i-th power supply 57 1222273, and the voltage range of the patent application is applied; and a PMOS transistor control unit is connected to the gate terminal of the aforementioned 8PM 0s transistor, and conducts control of the aforementioned 8PM. S transistor 29. The semiconductor device according to item 28 of the patent application, wherein the voltage at the t-th power supply voltage plus the second predetermined voltage is the voltage at which the 9 ps transistor starts to conduct. 30. If the semiconductor device according to item 28 of the patent application scope, the second predetermined voltage is a cattle conductor device corresponding to the voltage term of the threshold voltage of the 9PM0S transistor, wherein the PM0s transistor control section has: For a GS transistor, the source terminal is connected to the gate terminal of the 15th 8PMOS transistor, and the drain terminal is connected to the gate terminal of the third or third transistor, and the aforementioned is applied to the gate terminal. The first power supply M or a scheduled power supply with a lower voltage than the aforementioned first power supply, and a 10th PMOS transistor, the source engages you # 极 缟 子 connected to the extreme end of the aforementioned 1st 3PMOS transistor + 20 j 丄 · If the patent, the fine range terminal and the extreme terminal are connected to the gate terminal of the aforementioned 8th PMOS transistor, and the open gate is connected to the aforementioned first terminal 32. If the patent control scope is the 31st, the transistor control section has A step-down unit is connected to the aforementioned source terminal, and the rear terminal is connected to the aforementioned N well. Item of the semiconductor device'its_the PM0s first voltage step-down section, the first voltage 6NMOS transistor source terminal, and 58 1222273 it, application patent range 1222273 step down the voltage signal from the source terminal , And then input the gate terminal of the 8th PMOS transistor. 33. If the semiconductor device under the scope of patent application No. 6, 18, or 22 has an N-well potential control unit, the N-well potential control unit applies' more the aforementioned second power supply voltage to j; and the aforementioned The potentials of the N wells of the fifth, sixth, and sixth PMOS transistors are set to the aforementioned second power supply voltage. 34. If the semiconductor device according to item 33 of the patent application scope, the n-well potential control section has: ίο an eighth PMOS transistor, the source terminal of which is connected to the aforementioned section] power supply terminal ′ 'no terminal and rear gate terminal Connected to the aforementioned _, and the gate terminal is connected to the aforementioned! Or the drain terminal of the 3PM () S transistor;-the 9th contact S transistor, the source terminal is connected to the non-terminal of the 3rd PMOS transistor, and the non-terminal and the closed terminal are connected to The aforementioned N-well; and the s-transistor control unit, which is connected to the gate terminal of the aforementioned deleted transistor and is used to conduct and control the aforementioned 9 PM-transistor. 3) The semiconductor device according to item 34 of the scope of patent application, wherein the pM0s transistor control unit has: a 6NMOS transistor H, the source terminal is connected to the gate terminal of the 9th PMOS transistor, no terminal Connected to the aforementioned section! The power supply voltage is applied at the gate terminal and is applied to the first or third node.