1220934 A7 _ B7 五、發明說明（/ ) [發明領域] 本發明係槪括關於自動測試設備，且尤指一種校正方 法，其運用“金製元件（golden devke)”與校正波形以準確 且快速地描述半導體測試器參數之特徵。 [發明背景] 半導體元件製造係典型包括在晶圓與封裝元件階層 (level)二者之測試處理。測試係通常电自動測試設備(ATE， automatic test equipment)所實施，其模擬_種操作條件以 驗證各個元件之功能性。隨著現代半導體元件性能階層提 高，元件製造者係加諸增高重要性於ATE準確度以使得元 件生產量爲最大化。 參考第一圖，槪括指示爲10之一典型半導體測試器包 括一測試器控制器12，諸如一大型電腦(mainframe)或個人 電腦（PC) ’以執行供控制元件測試之一測試程式。供產生 、傳送以及接收往來於~或多個待測試元件(DUT，device-under-test) 16的測試器訊號之接腳電子電路（pin electronics) 20 (參考第二圖)係一般爲配置遠離於控制器(其 內一測試頭14) ’並且係定位鄰近於該等DUT以使得測試 器訊號傳播延遲爲最小化。測試器接腳電子電路係經常包 含由數百至超過一千個通道（channel)，其經由一測試器介 面18而耦接至對應數目之DUT輸入/輸出(1/〇)與位址/時 脈(A/CLK)接腳。 第二圖說明介於接腳電子電路20與DUT 16之間的一 _______ 3 ^紙济、尺度適用中國國家標準（q\js)A4規格（210 X 297公爱)~" "" -- (請先閒讀背面之注意事項再填寫本頁) 丨 --訂·--------線丨 1220934 A7 ’ ___ _B7 ____ 五、發明說明（> )1220934 A7 _ B7 V. Description of the Invention (/) [Field of the Invention] The present invention relates to automatic test equipment, and in particular to a calibration method, which uses "golden devke" and calibration waveforms to accurately and quickly To describe the characteristics of the semiconductor tester parameters. [Background of the Invention] Semiconductor device manufacturing typically includes test processing at both the wafer and package element level. The test is usually performed by an automatic test equipment (ATE), which simulates various operating conditions to verify the functionality of each component. As the performance level of modern semiconductor components increases, component makers are increasing the importance of ATE accuracy to maximize component production. Referring to the first figure, a typical semiconductor tester, indicated as 10, includes a tester controller 12, such as a mainframe or personal computer (PC) 'to execute a test program for testing the control elements. Pin electronics 20 (refer to the second figure) for generating, transmitting, and receiving tester signals to or from multiple device-under-test (DUT) 16 (refer to the second figure) are generally configured to be far away from The controller (with a test head 14 therein) is positioned adjacent to the DUTs to minimize the tester signal propagation delay. Tester pin electronic circuits often include hundreds to more than a thousand channels, which are coupled to a corresponding number of DUT input / output (1/0) and address / hour via a tester interface 18 Pulse (A / CLK) pin. The second figure illustrates a _______ 3 between the pin electronic circuit 20 and the DUT 16 ^ paper economy, the scale applies the Chinese national standard (q \ js) A4 specification (210 X 297 public love) ~ " " "-(Please read the precautions on the back before filling this page) 丨 --Order · -------- line 丨 1220934 A7 '___ _B7 ____ V. Description of the invention (>)
局階層訊號路徑或通道。形成於一元件介面板(DIB，device interface board) 24的傳輸線路22與導電線跡(trace)係定出 介於接腳電子電路與DUT之間的訊號路徑，藉以維持一個 50歐姆的環境。雖然該接腳電子電路係定位靠近DUT，然 而沿著介於接腳電子電路與DUT之間的傳輸線路與PCB 線跡所傳播的種種訊號係易於受到種種形式之訊號降級 (degradation) ° 欲使得上述之訊號降級爲最小化，一種半導體測試器 係經常進行規則的校正以確保測試結果爲可靠且爲可重複 至一高度的精密度與準確度。一種習用的校正架構 (calibradon scheme)係涉及運用“金製元件”，諸如於授與 Hitchcock之美國專利第6,032，1〇7號所述者。金製元件係 類似於所測試者之半導體元件，其特性係爲習知且因此可 定義一 “標準（standard)”或參考。藉著運用金製元件，歸 因於接腳電子電路以及測試器-至-DUT的介面之訊號路徑 不確定性係可被偵測並且校正。 儘管習用的金製DUT校正（GDC，golden DUT calibration)方法係對於其所意欲之低準確度的應用而良好 運作，該種方法係對於高準確度的實施而爲顯現有問題。 習用的GDC方法所具有之一個典型問題係涉及運用規則的 測試圖樣（pattern)以校正測試器通道。正規的測試圖樣係 設計以施壓（stress)—個半導體元件並且試圖判別多個失敗 (fail)機構(諸如“固著(stick-to)”失敗或單元-對-單元（cell-tocell)旁漏情形“（bleedmg)”）。然而，對於測試器校正 4 本纸張尺度適用*國國家標準（CNS)A4規格（210 X 297公釐) ~ (請先閱讀背面之注意事項再填寫本頁)Bureau level signal path or channel. A transmission line 22 and a conductive trace formed on a device interface board (DIB) 24 define a signal path between the pin electronic circuit and the DUT, thereby maintaining a 50 ohm environment. Although the pin electronic circuit is positioned close to the DUT, the various signals transmitted along the transmission line and PCB traces between the pin electronic circuit and the DUT are susceptible to various forms of signal degradation. The aforementioned signal degradation is minimized. A semiconductor tester often performs regular corrections to ensure that the test results are reliable and repeatable to a high degree of precision and accuracy. One conventional calibradon scheme involves the use of "gold components" such as those described in U.S. Patent No. 6,032,107 granted to Hitchcock. Gold components are similar to the semiconductor components of the person being tested, their characteristics are conventional and therefore a "standard" or reference can be defined. By using gold components, the signal path due to the pin electronics and tester-to-DUT interface uncertainty can be detected and corrected. Although the conventional golden DUT calibration (GDC) method works well for its intended low accuracy applications, this method is an existing problem for high accuracy implementations. A typical problem with the conventional GDC method involves the use of regular test patterns to correct the tester channel. Formal test patterns are designed to stress a semiconductor device and try to identify multiple failing mechanisms (such as "stick-to" failures or cell-to-cell) Missing situation "(bleedmg)"). However, for the calibration of the tester, 4 paper sizes are applicable to the national standard (CNS) A4 specification (210 X 297 mm) ~ (Please read the precautions on the back before filling this page)
-------訂·-------I I 1220934 A7 · __ ____ 五、發明說明（j ) 程序而言，目標係欲測量該測試器之性能。結果，當試圖 運用金製元件與習用的測試程式以校正一個半導體測試器 時，準確度係因爲大量未隔離的邊緣（edge)參數變數而經 常受損。 仍爲所需而且迄今尙未可得者係一種校正方法，其運 用金製元件以準確且成本有效地校正一測試器波形之邊緣 參數。本發明之方法係可滿足此等需求。 [發明槪論] 本發明之ATE校正方法係提出一種高準確度與快速測 試器校正架構，其運用對於現存的測試器硬體之習用的金 製元件。結果，於此領域所已使用之半導體測試器硬體係 可僅僅藉著升級測試器軟體而易於升級至較高的準確度規 格。 欲實現上述的優點，本發明之一個形式係包含一種校 正半導體測試器之方法，該半導體測試器具有複數個通道 。該種方法係包括首先選擇至少一個金製元件與複數個失 敗機構，該金製元件具有已知電氣特性。該至少一個金製 元件係接著介面至複數個通道。跟著該介面步驟之後，該 等測試器通道係並行以特定邊緣(edge-specific)測試器波形 而特性化。該特定邊緣測試器波形係爲作用以隔離該複數 個失敗機構之一特定子集合，並且產生特定的特性化資料 。該特定邊緣特性化資料係接著與該已知電氣特性作比較 ，以偵測邊緣參數不一致性。在該比較步驟之後，該複數 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -------訂------- -!線！ A7 1220934 ______B7_ 五、發明說明（今） 個通道係調諧以使得邊緣參數不一致性爲最小化。 於另一個形式，本發明包含半導體測試器軟體，供操 作半導體測試器。該種測試器軟體包括一測試程式與一控 制碼程式庫，測試程式包括供測試一或多個半導體元件之 圖樣與控制資料。該測試器軟體更包括金製元件校正軟體 ，供校正複數個測試器通道。該金製元件校正軟體包括:一 金製DUT校正控制檔案，以供程式規劃校正控制命令;與 一金製DUT校正圖樣檔案，具有特定邊緣圖樣資料以供根 據該金製DUT校正(GDC)控制檔案而施加至金製DUT(待 測試元件）。 本發明之其他特點與優點係將由結合伴隨圖式所解讀 之以下詳細說明而爲顯明。 [圖式簡單說明] 參照以下之更爲詳細說明與伴隨圖式，本發明係將爲 較佳瞭解，其中： 第一圖係根據本發明一個形式之一種半導體測試系統 的方塊圖； 第二圖係第一圖所示之測試器介面的一槪括方塊圖； 第三圖係根據本發明一個實施例之一種程式結構的方 塊圖； 第四圖係說明所運用於本發明方法中之步驟的一個流 程圖;及 第五圖係第四圖所示之並行搜尋步驟的一個流程圖。 ☆國®家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線！ 1220934 A7 * _B7 _ 五、發明說明（ς) [主要符號說明] 10半導體測試器 12測試器控制器 14測試頭 16待測試元件(DUT) 18測試器介面 20接腳電子電路 22傳輸線路 24元件介面板 30整體測試器套裝軟體 32生產測試程式 34控制碼程式庫 36金製DUT校正(GDC)控制檔案 3 8 G D C圖樣檔案 4〇、42、44、46、48第四圖之流程圖的步驟 50、52、54、56、58、60、62、64、66、68 第五圖 之流程圖的步驟 [較佳實施例詳細說明] 本發明之方法係提出一種校正一個半導體測試器之方 式，諸如第一圖所示者，運用金製元件以校正至一高度的 準確度，同時使得校正執行時間爲最小化。槪括而言，此 舉係達成，藉著以並行(m parallel)方式而施加特定邊緣校 正測試圖樣至金製元件接腳，以隔離特定的失敗機構，其 7 本紙張尺度適用士國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 響· _______丁 ______象 1 . 矣 _ 1220934 A7 · _______B7__ 五、發明說明（^ ) 可由測試器所準確偵測。藉著隔離關於某些邊緣參數之特 疋的失敗機構’測試器係可微調以提供極高的準確度。再 者，由於該校正係以並行方式而執行於多個通道，校正執 行時間係大爲最小化。 參照第一與二圖，本發明之ATE校正方法係運用其形 式爲一個半導體測試器與“金製元件”之習用的硬體，如 同於此技藝中所瞭解之該等語辭。本發明人係已經發現一 種操作該測試器與金製元件之有利方式，透過以最小的校 正執行時間而增進準確度之獨特軟體。 參考第三圖，上述之習用的硬體係受控制及響應於一 整體測試器套裝軟體30。該整體套裝軟體之槪括架構包括: 一供控制標準生產元件測試之生產測試程式32、一供管理 控制作業之控制碼程式庫34、與校正軟體，其包括一金製 DUT校正（GDC)控制檔案36及一 GDC圖樣檔案38。該校 正軟體係結合其實施本發明之該種方法的步驟而更爲完整 描述於下文。 參照第四圖，該種ATE校正方法係一般爲開始於首先 裝載“金製元件”至個別的元件-介面-板（DIB，device-interface-board)插槽(未顯示)(於步驟40)。DIB與插槽係構 成該測試器介面之一部分，經常造成重大的訊號降級，其 係爲本發明所最小化。該測試器校正軟體係接著被通知金 製元件型式(於步驟42)，藉以自GDC校正圖樣檔案38 (第 三圖）而存取關於元件之適當的“金製（golden)”特性化檔 案。特別的是，GDC控制檔案36 (第三圖)係維持於特定校 (請先閱讀背面之注意事項再填寫本頁) 訂---------線！ 8 1220934 ______ _B7___ 五、發明說明（v.7 ) 正波形上的資訊，其係應運用以使得對於一給定的金製元 件之校正準確度爲最大化。 一旦該等金製元件與適當的測試程序（圖樣）係識別且 備妥，測試器通道係並行特性化(於步驟44)，藉著施加於 複數個測試器通道上之相同校正圖樣至相同對應的金製元 件接腳。更爲明確而言，對於其32個64接腳的金製元件 係裝載於個別的DUT插槽之情形，相同的校正圖樣係將並 行饋送至對於所有32個元件之相同的接腳。 對於一給定的接腳，數個校正圖樣係可施加至該元件 並且係捕捉自該元件，藉以單獨隔離及“調諧(tune)”特定 的測試器邊緣參數。舉例而言，不同的測試器邊緣參數可 包括對於多個驅動/比較(drive/compare)邊緣產生器之上升/ 下降邊緣。若多個訊號路徑係運用（以供多工處理），可能 的組合係可爲倍增。 參考第五圖，特性化步驟44係進而詳細包含一種並行 邊緣捜尋演算法，其係藉由自動儲存及運用先前偵測的搜 尋資訊而有利降低校正時間。對於在所有32個位置的一特 定邊緣參數之該種演算法包括首先選擇一個時間區間（於步 驟50)，該邊緣係期望爲位在其中。於該時間區間內，一 特定點係選擇（於步驟52)，以供取得該資料之第一取樣。 該等位置之一者係接著被識別作爲控制位置(於步驟54)。 作爲控制位置，通過/失敗之判定係針對該位置而作出（且 亦並行針對其他位置），且針對該位置而持續直到該邊緣被 找到爲止。一旦控制位置係識別，演算法係關照於測試器 9 各紙張適用☆關家標準(CNS)A4規格（21。X 297公爱）— ' ' (請先閱讀背面之注意事項再填寫本頁) • --訂·-------•線—' 1220934 A7 ' ___B7 _______ 五、發明說明（3 ) 中之一個記憶體（未顯示）以知悉對於該點之通過/失敗條件 是否已被偵測及儲存(於步驟56)。 若通過/失敗資訊並未偵測或儲存，則該演算法係指引 該測試器圖樣產生器以並行施加一特定邊緣波形至該等 DUT (於步驟58)，以允許於測試器中的一特定失敗機構之 隔離。響應於特定邊緣圖樣之在指定資料點的通過/失敗條 件係接著爲並行偵測(於步驟60)，且然後爲並行儲存至記 憶體(未顯示）(於步驟62)。 跟在該儲存步驟62之後，該邊緣是否已爲儲存之一判 定係作成於步驟64。若邊緣係找到，則該演算法係關照於 判定是否所有32個位置均爲特性化(於步驟66)。若並非所 有位置均爲特性化，則一個新的控制位置係選擇（於步驟 68)，且隨之以一邊緣偵測步驟64。 若該邊緣係並未由步驟64之判定而找出，則該演算法 係選擇一個新的資料點（於步驟52)，且重複前述的步驟直 到該邊緣係找到爲止。 當後續的位置係選擇，且對於一特定資料點（來自於步 驟56之判定)之通過/失敗資訊係已經儲存於記憶體中，則 先前使用的資訊係運用於捜尋，而並非爲重新產生於步驟 58 至 64 〇 參考回到第四圖，一旦該特性化步驟係完成，所測量 的資料係相較於已知的金製資料(於步驟46)，以判定個別 的偏移量。欲消除對於特定邊緣參數之偏移量，對應於該 等邊緣參數之測試器校正暫存器（未顯示）係調整（於步驟 10 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） ^ 一 (請先閱讀背面之注意事項再填寫本頁) n n n K ii It n 一°4a n n n n n I n I n ▲ 1220934 A7 ____B7___ 五、發明說明（y ) 48) °隨著一成功之測試器校正，測試器係接著備妥而開始 以大容量與高準確度之半導體元件的生產測試。 熟悉此技藝之人士將認可由本發明所提供之諸多的裨 益與優點。重要者係可達成之高準確度，乃藉著應用在校 正程序中之特定邊緣校正圖樣以隔離特定的電氣參數，其 係可接著爲調整至一高度的準確度。並行實施該程序係提 供附加的搏益，乃藉著使得校正執行時間爲最小化。另夕t ’由於本發明係運用如同軟體，習用的半導體測試器硬體 係可易於以最小的成本與人力而升級。 儘管本發明係已經關於其較佳實施例而特定顯示與說 明，熟悉此技藝之人士將可瞭解的是，係可在不偏離本發 明的精神與範疇下而作成於其之形式與細節的種種變化。 (請先閱讀背面之注意事項再填寫本頁) . --訂---------線| +、紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）------- Order · ------- I I 1220934 A7 · __ ____ V. Description of the invention (j) For the purpose of the procedure, the goal is to measure the performance of the tester. As a result, when attempting to calibrate a semiconductor tester using gold components and custom test programs, accuracy is often impaired due to the large number of unisolated edge parameter variables. Still needed and unavailable to date is a correction method that uses gold components to accurately and cost-effectively correct the edge parameters of a tester waveform. The method of the present invention meets these needs. [Invention theory] The ATE calibration method of the present invention proposes a high accuracy and fast tester calibration architecture, which uses conventional gold components for existing tester hardware. As a result, the semiconductor tester hardware used in this field can be easily upgraded to a higher accuracy specification simply by upgrading the tester software. To achieve the above advantages, one form of the present invention includes a method of calibrating a semiconductor tester having a plurality of channels. This method involves first selecting at least one gold component and a plurality of failure mechanisms, the gold component having known electrical characteristics. The at least one gold component is then interfaced to a plurality of channels. Following this interface step, the tester channels are characterized in parallel with edge-specific tester waveforms. The specific edge tester waveform is used to isolate a specific subset of the plurality of failed mechanisms and generate specific characterization data. The specific edge characterization data is then compared with the known electrical characteristics to detect inconsistencies in the edge parameters. After this comparison step, the plural 5 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ------- Order- -------! Line! A7 1220934 ______B7_ V. Description of the Invention (Today) The channels are tuned to minimize the inconsistency of the edge parameters. In another form, the present invention includes semiconductor tester software for operating a semiconductor tester. The tester software includes a test program and a control code library. The test program includes patterns and control data for testing one or more semiconductor components. The tester software also includes gold component calibration software for calibrating multiple tester channels. The gold component calibration software includes: a gold DUT calibration control file for program planning calibration control commands; and a gold DUT calibration pattern file with specific edge pattern data for control according to the gold DUT calibration (GDC) The file is applied to the gold DUT (component under test). Other features and advantages of the present invention will be apparent from the following detailed description, which is interpreted in conjunction with the accompanying drawings. [Brief Description of the Drawings] The present invention will be better understood with reference to the following more detailed description and accompanying drawings, wherein: The first drawing is a block diagram of a semiconductor test system according to one form of the present invention; the second drawing It is a block diagram of the tester interface shown in the first diagram; the third diagram is a block diagram of a program structure according to an embodiment of the present invention; the fourth diagram is a diagram illustrating the steps used in the method of the present invention A flowchart; and the fifth diagram is a flowchart of the parallel search step shown in the fourth diagram. ☆ National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order --------- Line! 1220934 A7 * _B7 _ V. Description of invention (ς) [Explanation of main symbols] 10 Semiconductor tester 12 Tester controller 14 Test head 16 DUT 18 Tester interface 20 pin electronic circuit 22 Transmission line 24 element Interface panel 30 Overall tester set software 32 Production test program 34 Control code library 36 Gold DUT calibration (GDC) control file 3 8 GDC pattern file 40, 42, 44, 46, 48 50, 52, 54, 56, 58, 60, 62, 64, 66, 68 The steps of the flow chart in the fifth figure [the detailed description of the preferred embodiment] The method of the present invention proposes a way to calibrate a semiconductor tester, For example, as shown in the first figure, a gold component is used to correct to a high degree of accuracy while minimizing the execution time of the correction. In a nutshell, this is achieved by applying a specific edge correction test pattern to the gold component pins in a m parallel manner to isolate specific failure mechanisms. The 7 paper standards are applicable to national standards. (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) * _______ 丁 ______ Elephant 1. 矣 _ 1220934 A7 · _______B7__ 5. Description of the invention (^) Accurately detected by the tester. By isolating the failing mechanism's unique feature on certain edge parameters, the tester can be fine-tuned to provide extremely high accuracy. Furthermore, since the correction is performed on multiple channels in parallel, the correction execution time is minimized. Referring to the first and second figures, the ATE correction method of the present invention uses conventional hardware in the form of a semiconductor tester and "gold components", as those terms are understood in the art. The inventors have found a unique way to operate the tester and gold components in a unique way to improve accuracy by minimizing the time required for calibration. Referring to the third figure, the conventional hardware system described above is controlled and responsive to an integrated tester software package 30. The overall architecture of the integrated software package includes: a production test program 32 for controlling standard production component tests, a control code library 34 for management and control operations, and calibration software, including a gold DUT calibration (GDC) control File 36 and a GDC pattern file 38. The correction soft system is described more fully below in conjunction with its steps for implementing the method of the invention. Referring to the fourth figure, this ATE calibration method generally starts by first loading "gold components" into individual component-interface-board (DIB, device-interface-board) slots (not shown) (at step 40) . The DIB and slot system form part of the tester interface, often causing significant signal degradation, which is minimized by the present invention. The tester calibration software system is then notified of the type of the gold component (at step 42) to access the appropriate "golden" characterization file for the component from the GDC calibration pattern file 38 (third figure). In particular, the GDC control file 36 (picture 3) is maintained at a specific school (please read the precautions on the back before filling this page) Order --------- line! 8 1220934 ______ _B7___ V. Description of the Invention (v.7) The information on the positive waveform should be used to maximize the accuracy of correction for a given gold component. Once the gold components are identified and prepared with the appropriate test procedures (patterns), the tester channels are characterised in parallel (at step 44) by applying the same correction pattern to the same correspondence on the multiple tester channels Gold component pins. More specifically, for the case where its 32 64-pin gold components are mounted in individual DUT slots, the same correction pattern will be fed in parallel to the same pins for all 32 components. For a given pin, several correction patterns can be applied to the component and captured from the component to isolate and "tune" specific tester edge parameters individually. For example, different tester edge parameters may include rising / falling edges for multiple drive / compare edge generators. If multiple signal paths are used (for multiplexing), the possible combinations are multiplied. Referring to the fifth figure, the characterization step 44 further includes a parallel edge search algorithm in detail, which advantageously reduces the correction time by automatically storing and using previously detected search information. This algorithm for a specific edge parameter at all 32 locations includes first selecting a time interval (at step 50), where the edge is expected to be located in it. Within that time interval, a specific point is selected (at step 52) for the first sampling of the data. One of these positions is then identified as the control position (at step 54). As a control position, the pass / fail determination is made for that position (and also for other positions in parallel), and continues for that position until the edge is found. Once the control position is identified, the algorithm is applied to each paper of the tester 9 ☆ Family Standard (CNS) A4 specification (21. X 297 public love) — '' (Please read the precautions on the back before filling this page) • --Order · ------- • Line— '1220934 A7' ___B7 _______ V. One of the memories (not shown) in the description of the invention (3) to know whether the pass / fail condition for this point has been passed Detect and store (at step 56). If the pass / fail information is not detected or stored, the algorithm directs the tester pattern generator to apply a specific edge waveform to the DUTs in parallel (at step 58) to allow a specific Isolation of failed institutions. The pass / fail conditions at the designated data point in response to a particular edge pattern are then detected in parallel (at step 60) and then stored in parallel to a memory (not shown) (at step 62). Following the storing step 62, a determination is made as to whether the edge is one of storing in step 64. If the edge system is found, the algorithm is concerned with determining whether all 32 positions are characterised (at step 66). If not all positions are characterised, a new control position is selected (at step 68), followed by an edge detection step 64. If the edge system is not found by the determination in step 64, the algorithm selects a new data point (at step 52) and repeats the previous steps until the edge system is found. When the subsequent position is selected and the pass / fail information for a specific data point (decision from step 56) has been stored in the memory, the previously used information is used for searching, not for regeneration In steps 58 to 64, the reference is returned to the fourth figure. Once the characterization step is completed, the measured data is compared with the known gold data (at step 46) to determine the individual offsets. To eliminate the offset for specific edge parameters, the tester calibration register (not shown) corresponding to these edge parameters is adjusted (at step 10, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 Mm) ^ One (please read the notes on the back before filling this page) nnn K ii It n 1 ° 4a nnnnn I n I n ▲ 1220934 A7 ____B7___ V. Description of Invention (y) 48) ° With the success of a The tester is calibrated. The tester is then ready to start production testing of semiconductor components with large capacity and high accuracy. Those skilled in the art will recognize the many benefits and advantages provided by the present invention. What is important is the high accuracy that can be achieved by using specific edge correction patterns in the calibration process to isolate specific electrical parameters, which can then be adjusted to a high degree of accuracy. Implementing the program in parallel provides additional benefits by minimizing the time required to perform the calibration. In addition, since the present invention uses software like software, the conventional semiconductor tester hardware can be easily upgraded with minimal cost and labor. Although the present invention has been specifically shown and described with respect to its preferred embodiments, those skilled in the art will appreciate that various forms and details can be made without departing from the spirit and scope of the present invention. Variety. (Please read the notes on the back before filling out this page). --Order --------- Line | +, Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm)