TW594918B - A method for fabricating a wet barrier layer - Google Patents
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- TW594918B TW594918B TW92118526A TW92118526A TW594918B TW 594918 B TW594918 B TW 594918B TW 92118526 A TW92118526 A TW 92118526A TW 92118526 A TW92118526 A TW 92118526A TW 594918 B TW594918 B TW 594918B
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594918 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製造方法,且特別是有 關於一種適用於插塞製程之濕潤阻障層的製造方法。 【先前技術】 今日電子技術進步的一個主要原因,就是藉由半導體技 術,將各種不同的電子元件’如電晶體、電容^及電 阻,以高集積度(high density)的方式實作於一個積體電 路(Integrated Circuit)中。 在半導體裝置中,這些不同的電子元件之間係透過導電内 連線加以連接。而各電子元件的各狀態區域,例如電晶體 的源極與汲極,則是透過垂直導線,也就是所謂的插塞連 接到導電内連線。 請參看第1圖,第1圖係繪示的習知接觸插塞結構。在基底 1 0 0有一摻雜區域1 0 2。此摻雜區域1 0 2可以為例如電晶體 的汲極或源極。在基底1 0 0之上有一層介電層103,介電層 10 3的材質可以為硼磷玻璃或是低介電材質。在介電層103 上則有導電内連線1 0 6。為了將摻雜區1 0 2的信號傳送到導 電内連線106,因此需要一垂直的導體,也就是金屬插塞 1 0 5。然而由於金屬插塞1 0 5的材質會擴散至基底1 0 0、介 電層1 0 3之内,因此會加上一濕潤阻障層1 0 4形成於基底 1 0 0、介電層1 0 3與插塞1 0 5之間。濕潤阻障層1 0 4的例子包594918 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a wet barrier layer suitable for a plug process. [Previous technology] One of the main reasons for the advancement of electronic technology today is the use of semiconductor technology to implement various electronic components such as transistors, capacitors, and resistors in a high-density manner. Body Circuit (Integrated Circuit). In semiconductor devices, these different electronic components are connected through conductive interconnects. Each state area of each electronic component, such as the source and drain of the transistor, is connected to the conductive interconnect via a vertical wire, a so-called plug. Please refer to FIG. 1. FIG. 1 illustrates a conventional contact plug structure. There is a doped region 102 on the substrate 100. This doped region 1 0 2 may be, for example, a drain or a source of a transistor. There is a dielectric layer 103 on the substrate 100. The material of the dielectric layer 103 can be borophospho glass or a low dielectric material. On the dielectric layer 103, there are conductive interconnects 106. In order to transmit the signal of the doped region 102 to the conductive interconnect 106, a vertical conductor is required, that is, the metal plug 105. However, since the material of the metal plug 105 is diffused into the substrate 100 and the dielectric layer 103, a wet barrier layer 104 is added to form the substrate 100 and the dielectric layer 1. Between 0 3 and plug 1 0 5. Wet barrier layer 1 0 4 example pack
第6頁 594918 五、發明說明(2) 括由鈦/氮化鈦形成的薄膜。 現今濕潤阻障層的製造方法,係以離子金屬電漿(I on Metal Plasma, IMP)製程或是準直管(Collimator)沉 積製程先沉積鈦金屬層於接觸窗之底部及側壁之上,接 著,再以化學氣相沉積製程形成一氮化鈦層於鈦金屬層之 上。習知使用準直管沉積製程所沉積鈦金屬,對整片晶圓 而言電阻值較離子金屬電漿製程所形成的鈦金屬的片電阻 為低,但是,準直管沉積製程所適用之開口的高寬比不能 太大,一般只適用於介層窗插塞的製程。至於對接觸窗插 塞的製程,因為接觸窗的高高寬比,所以準直管沉積製程 並不適用,而必須》使用離子金屬電漿製程來進行鈦金屬層 的沉積製程。但是,利用離子金屬電漿製程沉積鈦金屬層 製造接觸窗插塞片阻抗高(Sheet Resistance,Rs),並 不符合需求。 » 在半導體製程線寬越來越窄的情況下,如何降低導線的片 電阻及電路的阻抗變得越來越重要。特別是在半導體週邊 區域,當插塞的垂直高度較其他地方為大時,接觸電阻更 成為嚴重的問題,高接觸片電阻也會使整個電路的阻值大 幅提高。因此,如何解決半導體製程中插塞的接觸電阻, 尤其是週邊區域插塞的接觸電阻,將是影響半導體整體能 否向更高集積度與更小線寬前進的重要關鍵。 方 造 製 的 層 障 阻 潤 濕 種 1 供 提 在 是 就 的 § 3 的 容明 内發 明本 發此 t 因Page 6 594918 V. Description of the Invention (2) Includes thin films made of titanium / titanium nitride. At present, the manufacturing method of the wet barrier layer is based on an I on Metal Plasma (IMP) process or a collimator deposition process. A titanium metal layer is first deposited on the bottom and side walls of the contact window, and then Then, a titanium nitride layer is formed on the titanium metal layer by a chemical vapor deposition process. It is known that the titanium metal deposited using the collimated tube deposition process has a lower resistance value than the titanium metal formed by the ion metal plasma process for the entire wafer. However, the openings suitable for the collimated tube deposition process are suitable. The aspect ratio cannot be too large, and is generally only applicable to the process of the via window plug. As for the process of contact window plugs, because of the aspect ratio of the contact window, the process of collimating tube deposition is not applicable. Instead, an ion metal plasma process must be used to deposit the titanium metal layer. However, the use of an ionic metal plasma process to deposit a titanium metal layer to produce a contact window plug sheet with high sheet resistance (Rs) does not meet requirements. »In the case of narrower semiconductor process line widths, how to reduce the sheet resistance of the wires and the impedance of the circuit becomes more and more important. Especially in the semiconductor peripheral area, when the vertical height of the plug is larger than other places, the contact resistance becomes a serious problem, and the high contact resistance will also greatly increase the resistance of the entire circuit. Therefore, how to solve the contact resistance of the plugs in the semiconductor manufacturing process, especially the contact resistance of the plugs in the peripheral area, will be an important key that affects whether the semiconductor as a whole can advance to a higher concentration and a smaller line width. The barriers made by the barriers are wet and wet seeds. 1 The supply and release are in the contents of § 3, which is hereby issued.
第7頁 594918 五、發明說明 適用於製造低片 本發明的另一目 以形成插塞,可 五。 本發明的 用於高高 可以使整 根據本發明之上 適用於在 如電晶體 電阻值之插塞 的是在提供 以使插塞之 的是在提供 接觸插塞製 電路的電阻 述目的,提 摻雜區之基 或源極。在 包括硼磷玻 g (3) 再 寬比的 個元件 具有 的汲極 電層的材質至少 内以一微影蝕刻製程形成一 域。以離子金屬電漿製程在 一鈦金屬層。接下來,以一 形成的鈦金屬層進行處理, 材質層於鈦金屬層上而完成 用於形成材質層的材質係選 化金屬/鈦鎢合金之複合層 是氮化组。 最後,在接觸窗内填入導體 位於介電層上的導體材質而 本發明所揭露的方法亦適用 (Dual Damascene)製程。 依照本發明以一較佳實施例 一種濕潤阻障層的製造方,用 片電阻至少降低百分之二十 一種濕潤阻障層的製造方,適 程中,藉由降低插塞之片電阻 值降低。 出一種濕调阻障層的製造方, 底之上。此掺雜區域可以為例 基底另外具有一層介電層,介 璃或是低介電材質。在介電層 接觸窗開口以暴露出摻雜區 接觸窗開口的底部及側壁形成 原位(in-situ)電漿製程對已 再以化學氣相沉積製程形成一 介層窗濕潤阻障層的製程,適 自於氮化金屬、鈦鶴合金和氮 ,而氮化金屬可以為氮化鈦或 材質,並以一平坦化製程移除 完成接觸插塞的製程。當然, 於介層插塞製程和雙金屬鑲嵌 為例,提出一種接觸窗插塞的Page 7 594918 V. Description of the invention Applicable to the manufacture of low film Another purpose of the present invention to form a plug may be five. The purpose of the present invention is to provide a resistor according to the present invention that is suitable for use in a plug such as a transistor resistance value. The purpose of providing a plug is to provide a resistance of a contact plug circuit. The base or source of the doped region. A domain is formed by a photolithography process at least within the material of the drain layer of each element including the boron-phosphorus glass (3) and the aspect ratio. An ion metal plasma process is performed on a titanium metal layer. Next, a formed titanium metal layer is processed, and the material layer is completed on the titanium metal layer. The material layer used to form the material layer is a selected metal / titanium tungsten alloy composite layer which is a nitride group. Finally, the contact window is filled with the material of the conductor located on the dielectric layer, and the method disclosed in the present invention is also applicable to the Dual Damascene process. According to the present invention, in a preferred embodiment, a method for manufacturing a wet barrier layer uses a sheet resistor to reduce at least 21% of a method for manufacturing a wet barrier layer. In a suitable process, by reducing the chip resistance of a plug The value decreases. A manufacturing method of a moisture barrier layer is formed on the bottom. This doped region can be taken as an example. The substrate additionally has a dielectric layer, a glass or a low dielectric material. An in-situ plasma process is formed at the opening of the dielectric layer contact window to expose the bottom and sidewalls of the doped region contact window opening. The process of forming a dielectric barrier wet barrier layer by the chemical vapor deposition process It is suitable for metal nitride, titanium crane alloy and nitrogen, and the metal nitride can be titanium nitride or material, and the contact plug is completed by a flattening process. Of course, based on the interposer plug process and bimetal damascene as an example, a contact window plug
第8頁 594918 五、發明說明(4) 製造方法,並量測片電阻與習知做比較來證明本發明所提 供之插塞製程的功效。 【實施方式】Page 8 594918 V. Description of the invention (4) Manufacturing method, and measuring the resistance of the sheet and comparing it with the conventional one to prove the efficacy of the plugging process provided by the present invention. [Embodiment]
第2圖至第5圖係繪示依照本發明一較佳實施例的一種接觸 窗插塞製程之剖面示意圖。請參照第2圖,在一基底2 0 0上 有一傳導層202,傳導層20 2可以為一摻雜區域或是一導 線。傳導層2 0 2若是為摻雜區域,則可以為例如電晶體的 汲極或源極,而所欲形成的插塞則為接觸插塞。傳導層 2 0 2若是為導線,則所欲形成的插塞則為介層插塞。在基 底20 0之上有一層介電層204,介電層20 4的材質可以為硼 磷玻璃或是低介電材質。在介電層2 0 4内形成一接觸窗 2 0 6。形成接觸窗2 0 6的方法包括在介電層2 0 4上旋塗一光 阻層(未繪示於圖上),以一微影製程圖案化光阻層,以 圖案化光阻層為罩幕,蝕刻暴露出的介電層2 0 4而形成接 觸窗2 0 6,其中,接觸窗2 0 6暴露出部分摻雜區域2 0 2。最 後,移除光阻層。Figures 2 to 5 are schematic cross-sectional views of a contact window plug process according to a preferred embodiment of the present invention. Referring to FIG. 2, there is a conductive layer 202 on a substrate 200. The conductive layer 202 can be a doped region or a conductive line. If the conductive layer 2 0 2 is a doped region, it may be, for example, a drain or a source of a transistor, and a plug to be formed is a contact plug. If the conductive layer 2 0 2 is a wire, the plug to be formed is a via plug. There is a dielectric layer 204 on the substrate 200, and the material of the dielectric layer 204 can be borophospho glass or low-dielectric material. A contact window 206 is formed in the dielectric layer 204. The method for forming the contact window 206 includes spin-coating a photoresist layer (not shown) on the dielectric layer 204, patterning the photoresist layer by a lithography process, and using the patterned photoresist layer as The mask is etched to expose the exposed dielectric layer 204 to form a contact window 206, wherein the contact window 206 exposes a partially doped region 202. Finally, the photoresist layer is removed.
請接著參照第3圖,形成一鈦金屬層2 0 8於介電層2 0 4之上 及介層窗2 0 6之内。形成欽金屬層20 8的方法係藉由一離子 金屬電漿製程。接著,以一原位電漿2 1 0對鈦金屬層2 0 8進 行一後處理,原位電漿2 1 0所使用的反應氣體可以為氮 氣、氫氣或氮氣及氫氣之混和氣體。 請參照第4圖,形成一氮化鈦層2 1 2於鈦金屬層2 0 8之上, 594918 五、發明說明(5) 形成氮化鈦層2 1 2的方法包括一化學氣相沉積法,氮化鈦 層2 1 2和鈦金屬層2 0 8係作為一濕潤阻障層之用,以避免後 續形成導體層的材質滲透進介電層2 0 4之内。接著,沉積 一導體層2 1 4於氮化鈦層2 1 2之上並填滿介層窗2 0 6,形成 導體層2 1 4的材質可以為金屬材質,例如鎢金屬或鎢合 金,形成導體層21 4的方法包括一化學氣相沉積法。 最後,請參照第5圖,以一平坦化製程移除高於介電層2 0 4 的鈦金屬層、氮化鈦層及導體層而在介層窗20 6之内形成 一接觸插塞2 1 6。平坦化製程可以為一化學機械研磨製 程。 後續的製程並未繪示於圖上,僅簡單說明於下。在後續電 性連接不同層導線間的介層窗插塞製程或是後續的雙金屬 鑲嵌製程均依本實施例前述的製程形成濕潤阻障層。現以 幾個不同線寬的製程進行比較。在0. 1 5微米的製程中,以 離子金屬電漿製程形成的鈦金屬層的厚度為1 0 0埃而氮化 鈦層的厚度為5 0埃的情況下,在氮化鈦層形成之前對鈦金 屬層進行一原位電漿處理的例子與未進行原位電漿處理的 例子相較,片電阻前者較後者減少百分之三十五點二。在 0. 1 8微米的製程中,以離子金屬電漿製程形成的鈦金屬層 的厚度為1 6 0埃而氮化鈦層的厚度為7 0埃的情況下,在氮 化鈦層形成之前對鈦金屬層進行一原位電漿處理的例子與 未進行原位電漿處理的例子相較,片電阻前者較後者減少 百分之三十六點八。在0 · 2 2 / 0 . 2 5微米的製程中,以離子 金屬電漿製程形成的鈦金屬層的厚度為1 0 0埃而氮化鈦層Referring to FIG. 3, a titanium metal layer 208 is formed on the dielectric layer 204 and the dielectric window 206. The method for forming the Chin metal layer 20 8 is through an ion metal plasma process. Next, an in-situ plasma 2 10 is used to perform a post-treatment on the titanium metal layer 208. The reaction gas used in the in-situ plasma 2 10 may be nitrogen, hydrogen, or a mixed gas of nitrogen and hydrogen. Referring to FIG. 4, a titanium nitride layer 2 1 2 is formed on the titanium metal layer 208. 594918 V. Description of the invention (5) The method for forming the titanium nitride layer 2 1 2 includes a chemical vapor deposition method The titanium nitride layer 2 12 and the titanium metal layer 208 are used as a wet barrier layer to prevent the material of the subsequent conductor layer from penetrating into the dielectric layer 204. Next, a conductor layer 2 1 4 is deposited on the titanium nitride layer 2 1 2 and fills the interstitial window 2 06. The material for forming the conductor layer 2 1 4 can be a metal material, such as tungsten metal or a tungsten alloy. The method of the conductive layer 21 4 includes a chemical vapor deposition method. Finally, referring to FIG. 5, a planarization process is used to remove the titanium metal layer, the titanium nitride layer, and the conductor layer higher than the dielectric layer 204, and a contact plug 2 is formed within the dielectric window 206. 1 6. The planarization process may be a chemical mechanical polishing process. Subsequent processes are not shown on the diagram, but are simply explained below. A wet barrier layer is formed according to the aforementioned process in this embodiment during the subsequent process of plugging the interlayer window for electrically connecting different layers of wires or the subsequent bimetal inlay process. The comparison is made with several different line width processes. In a 0.15 micron process, the thickness of the titanium metal layer formed by the ion metal plasma process is 100 angstroms and the thickness of the titanium nitride layer is 50 angstroms before the titanium nitride layer is formed. Compared with the case where the in-situ plasma treatment is not performed on the titanium metal layer, the former is 35.5% less than the latter. In a 0.18 micron process, the thickness of the titanium metal layer formed by the ion metal plasma process is 160 angstroms and the thickness of the titanium nitride layer is 70 angstroms before the titanium nitride layer is formed. Compared with the example where the in-situ plasma treatment is performed on the titanium metal layer, the former is 36.6% less than the latter. In a 0.2 2 / 0.25 micron process, the thickness of the titanium metal layer formed by the ion metal plasma process is 100 angstroms and the titanium nitride layer is
第10頁 594918 五、發明說明(6) 的厚度為1 0 0埃的情況下,在氮化鈦層形成之前對鈦金屬 層進行一原位電漿處理的例子與未進行原位電漿處理的例 子相較,片電阻前者較後者減少百分之二十九點七。 就以上的實驗結果來看,即使是做最保守的估計,本發明 所揭露的濕潤阻障層的製造方法都至少可以降低片電阻至 少百分之二十五。 - 由上述本發明較佳實施例可知,應用本發明具有下列優 點。本發明所提供一種插塞的製造方法,可以降低插塞接 面的片電阻少百分之二十五。另外,運用本發明所揭露的 製程無須在不同的機台間移動晶圓片,運用一原位電漿對 4 離子金屬沉積製程所形成的鈦金屬層進行處理,可以使插 塞之濕潤阻障層的片電阻大幅下降。而且,離子金屬沉積 製程適用於高高寬比的結構的製程之上,因此,接觸插塞 的製程亦可運用本發明所揭露的製程來進行。 雖然本發明已以一較佳實施例揭露如上,然其並非用以限 定本發明,任何熟習此技藝者,在不脫離本發明之精神和 範圍内,當可作各種之更動與潤飾,因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。Page 10 594918 V. Description of the invention (6) In the case of a thickness of 100 angstroms, the titanium metal layer is subjected to an in-situ plasma treatment before the titanium nitride layer is formed and the in-situ plasma treatment is not performed. Compared to the example, the former is 29.7% less than the latter. From the above experimental results, even if the most conservative estimation is made, the method for manufacturing the wet barrier layer disclosed in the present invention can reduce the sheet resistance by at least 25%. -As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the following advantages. The invention provides a method for manufacturing a plug, which can reduce the sheet resistance of the plug interface by 25%. In addition, the process disclosed in the present invention does not need to move the wafer between different machines, and an in-situ plasma is used to process the titanium metal layer formed in the 4 ion metal deposition process, which can make the plug's wet barrier. The sheet resistance of the layer is greatly reduced. In addition, the ionic metal deposition process is suitable for processes with a high aspect ratio structure. Therefore, the process of contact plugs can also be performed using the process disclosed in the present invention. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
594918 圖式簡單說明 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 第1圖係繪示的習知接觸插塞結構;以及 - 第2圖至第5圖係繪示依照本發明一較佳實施例的一種接觸 窗插塞製程之剖面示意圖。 【元件代表符號簡單說明】 4 100、 2 0 0 : 基底 102: 摻 雜 區域 103、 .2 0 4: 介電層 104 濕 潤 阻障層 105 金 屬 插塞 106 導 電 内連線 202 傳 導 層 206 接 觸 窗 208 鈦 金 屬層 210 原 位 電漿 212 氮 化 鈦層 214 導 體 層 216 接 觸 插塞594918 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings for detailed description. As follows: FIG. 1 is a conventional contact plug structure shown in the drawing; and FIGS. 2 to 5 are schematic cross-sectional views showing a contact window plug manufacturing process according to a preferred embodiment of the present invention. [Simple description of element representative symbols] 4 100, 2 0 0: substrate 102: doped region 103, .2 0 4: dielectric layer 104 wet barrier layer 105 metal plug 106 conductive interconnect 202 conductive layer 206 contact window 208 Titanium metal layer 210 In-situ plasma 212 Titanium nitride layer 214 Conductor layer 216 Contact plug
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TW92118526A TW594918B (en) | 2003-07-07 | 2003-07-07 | A method for fabricating a wet barrier layer |
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