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TW594024B - Method for treating and testing semiconductor component - Google Patents

Method for treating and testing semiconductor component Download PDF

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Publication number
TW594024B
TW594024B TW91136226A TW91136226A TW594024B TW 594024 B TW594024 B TW 594024B TW 91136226 A TW91136226 A TW 91136226A TW 91136226 A TW91136226 A TW 91136226A TW 594024 B TW594024 B TW 594024B
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Taiwan
Prior art keywords
pad
semiconductor element
testing
bump
metal bump
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TW91136226A
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Chinese (zh)
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TW200409927A (en
Inventor
Yueh-Lung Lin
Chian-Chi Lin
Chih-Huang Chang
Yi-Lung Lin
Chun-Chi Lee
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Advanced Semiconductor Eng
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Priority to TW91136226A priority Critical patent/TW594024B/en
Publication of TW200409927A publication Critical patent/TW200409927A/en
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Publication of TW594024B publication Critical patent/TW594024B/en

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Disclosed is a method for treating and testing a semiconductor component. The method includes the steps of breaking the insulating layer on contact pads of a semiconductor component by wire-bonding and forming metal bumps on the contact pads wherein the metal bumps directly contact and electrically connect to the contact pads. Thereafter, interconnects of a prober are placed in electrical communication with the metal bumps thereby conducting a testing step.

Description

需要多 可分成 及燒機 可能以 一個相 在封裝 之前) 迫使製 的裝置 作之元 於每一 其中之 無法正 片或晶 多、發明說明α) 【發明所屬之技術領域】 本發明係有關於一種半 【先前技術】 半導體積體電路的製造 造、封裝以及測試。測試 參數性(parametric)以 呰方法中,該半導體元件 裂態測試。雖然封裝係為 是半導體製造業者仍經常 裝置具有合適性質和功能 元件的結構日趨複雜化, 前對晶圓型態或晶片型態 能降低封裝到無法正常操 晶片封裝構造的出現,由 在多晶片承載件上晶片的 有損壞而使整個封裝構造 地浪費製造成本,因此晶 要。 導體晶圓處理以及測試方法。 個製程 功能性 (burn- 晶圓、 對而言 之後( 才進行 造業者 進行測 件的可 半導體 一,卻 常操作 圓尺寸 ,包含設計、製 (functional )、 i η )的方法。在這 晶片或封裝構造的 較昂貴的步驟,但 也就是擔保半導體 測試。隨著半導體 必須在封裝製程之 試,如此一來,便 能。此外,隨著多 元件僅為多個 可能因這其中 而遭到淘汰,大大 的測試在此更為必Need to be divided and the burner may use one phase before packaging.) Forced devices are made in each of them, which cannot be positive or crystal. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to a kind of Semi-prior art: Manufacturing, packaging, and testing of semiconductor integrated circuits. Test Parametric: In this method, the semiconductor device is cracked. Although packaging systems are often used by semiconductor manufacturers, the structure of devices with suitable properties and functional components is becoming more and more complicated. The previous wafer type or wafer type can reduce packaging to the point where the chip package structure cannot be handled properly. The damage of the wafer on the carrier causes the entire package structure to waste manufacturing costs, so it is important. Conductor wafer processing and testing methods. Functionality of each process (burn-wafer, to the nearest (the manufacturer can only test the device before the semiconductor can be tested, but often operates a circular size, including design, functional, i η) method. Here the wafer Or the more expensive steps of package construction, but also to guarantee semiconductor testing. As semiconductors must be tested in the packaging process, this can be done. In addition, with multiple components, only multiple may be affected by this. Eliminated, large tests are more necessary here

一般而言,為了保護晶圓或是裸晶片内部的結構以 面的接墊,晶圓或是晶片的製造廠商會在晶圓或是晶及表 面形成一保護層(passivation layer),然後才運送曰贫片表 4廠商進行測試。這一層保護層具有絕緣性質且往彳主° ’則 蓋住整個接墊的表面。另外,該接墊表面若沒有保會覆 蓋’則容易形成一層不導電的氧化層。無論是保護居 9幾是Generally speaking, in order to protect the internal structure of the wafer or bare wafer with surface pads, the wafer or wafer manufacturer will form a passivation layer on the wafer or crystal and the surface before shipping. Table 4 shows that manufacturers are poor. This protective layer is insulating and covers the entire surface of the pad. In addition, if the surface of the pad is not covered, it is easy to form a non-conductive oxide layer. Whether it is a protected home 9

594024 五、發明說明(2) 氧化y都會使測試過程中所使用的探測器難以與待測的晶 圓f是晶片產生電性連接。s此測試廠商測試該晶圓晶片 ^别,需要先將其接墊表面的保護層或是氧化層刮除。通 :此一刮除步驟係利用探測器上的針狀連接接點進行之。 二照第la以及化圖,該半導體元件1〇〇之接墊11〇表面覆蓋 :保護層120,因此利用探測器13〇測試該半導體元件ι〇〇 力於連接接點140上促使針狀的連接接點140穿 ,保護層12G ’連接接點14〇才得以與接墊UG發生電性連 體元^ f的方法亦使用於測試接墊表面具有氧化層的半導 就晶!或是晶片的設計越精密日寺,其上的接墊分佈 ^达。,.,、了測試具有緊密分佈之接墊的晶圓或是晶 片垃:要將極細的針狀連接接點用於探測器上。但是針狀 =接點越細則其機械強度越弱。若要藉由極細的連 針透接塾上的保護層或是氧化層_ 升。 ·、’卜吊谷易扣壞,造成探測器的耗損率大幅上 【發明内容】 之ί ί:之1的係提供一種處理以及測試接墊具有絕緣層 方法,其:藉由一打線製程破壞半導體元件 層,使得接墊上的絕緣層不需要藉由施 幅^ ^。^ 接點來穿透,藉此使探測器的耗損率大 為了達成上述及其他之目#,本發明提供一種半導體元 五、發明說明(3) 件的處理以及測試方法。本方法的特徵在於藉由 程破壞半導體7C件表面接墊上的絕緣層,並且個 接與接墊接觸並且電性連接的凸塊, ^成個直 器之連接接點來穿透接塾上的絕緣層:因此 試步驟,探測器僅需使其連接接點與凸塊接觸,== 測半導體兀件執行測試步驟,而不需施力於連接接點上使 其穿透半導體元件接墊上之絕緣層(例如保護層或是氧化 物層),藉此保護連接接點使得探測器的耗損率大幅下 降。 本發明利用打線製程可以破壞多種覆蓋在半導體接墊上 的絕緣層,例如保護層或是接墊本身的金屬氧化物層等。 除此之外,在打線製程中還會形成與接墊電性連接的凸 塊,使得探測器的連接接點輕易與接墊產生電性連接。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯,下文特舉本發明較佳實施例,並配合所附圖示,Μ 細說明如下。 【實施方式】 第2 a - 2 c圖圖示根據本發明一實施例之處理並且測試一 晶片2 0 0的主要步驟。本發明使用之半導體晶片2 〇 〇 (參見 第2a圖)’其表面具有多個接墊21〇以及一具有絕緣性質 的保護層220覆蓋該晶片2〇〇以及該接墊21〇的整個表面。 參照第2a以及2b圖,本發明之特徵在於利用一打線製程 破壞接塾210上方的保護層22〇並且形成一凸塊23〇與該接 塾21 0直接電性連接。打線製程即為一種利用打線機將金 594024 五、發明說明(4)594024 V. Description of the invention (2) Oxidation of y will make it difficult for the detector used in the test process to make an electrical connection with the wafer f to be measured. s This test manufacturer tests the wafer wafer, and it is necessary to scrape off the protective layer or oxide layer on the surface of the pad first. General: This scraping step is performed by using a needle-shaped connection contact on the detector. According to the second la and the photo, the surface of the pad 11 of the semiconductor device 100 is covered with a protective layer 120, so the detector 130 is used to test the semiconductor device. The force on the connection contact 140 promotes the needle-like The connection contact 140 is penetrated, and the protective layer 12G 'connection contact 14o can be electrically connected to the pad UG. The method of f ^ is also used to test the semiconducting crystal with an oxide layer on the surface of the pad! Or the more precise the design of the chip is, the more pads are distributed. Test the wafer or wafer with closely spaced pads: Use very thin pin-shaped contacts for the detector. However, the needle-shaped = contact details have weaker mechanical strength. To pass through the protective layer or oxide layer on the diaphragm through a very thin pin. · "Budang Valley is easy to buckle, causing the loss rate of the detector to be greatly increased. [Abstract] The 1st of the 1st of the system provides a method for processing and testing the pads with an insulating layer, which: semiconductor devices are destroyed by a wire process Layer, so that the insulating layer on the pad does not need to be applied ^^. ^ The contact is penetrated, so that the loss rate of the detector is large. In order to achieve the above and other objectives #, the present invention provides a semiconductor element. 5. Description of the Invention (3) Processing and testing method of the device. The method is characterized in that the insulation layer on the surface pad of the semiconductor 7C device is destroyed by the process, and a bump that is in contact with the pad and is electrically connected is formed into a straight connection point to penetrate the pad. Insulation layer: Therefore, in the test step, the detector only needs to make its connection contacts in contact with the bumps. == Test the semiconductor element to perform the test step without applying force on the connection contacts to penetrate the semiconductor element pads. An insulating layer (such as a protective layer or an oxide layer), thereby protecting the connection contacts, greatly reduces the loss rate of the detector. In the present invention, a variety of insulating layers, such as a protective layer or a metal oxide layer of the pad itself, can be destroyed by using a wire bonding process. In addition, bumps that are electrically connected to the pads will be formed in the wire bonding process, so that the connection points of the detectors can easily be electrically connected to the pads. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention are given below, in conjunction with the accompanying drawings, and the detailed description is as follows. [Embodiment] Figures 2a-2c illustrate the main steps of processing and testing a wafer 2000 according to an embodiment of the present invention. The semiconductor wafer 200 (see FIG. 2a) used in the present invention has a plurality of pads 21 on its surface and a protective layer 220 having insulating properties covering the entire surface of the wafer 200 and the pads 210. Referring to FIGS. 2a and 2b, the present invention is characterized in that the protective layer 22o above the connector 210 is destroyed by a wire-forming process and a bump 23o is formed to be directly and electrically connected to the connector 210. The wire making process is a method of using a wire making machine to convert gold 594024. V. Description of the invention (4)

線(或銘線)連接至晶片接墊以及基板之導電線路 (conduct ive trace)(或導線架之導線)的方法。參照第 2 a圖’金線2 4 0係被垂直银入打線機的毛細鋼嘴 (capillary) 250。以一電子點火器(electr〇nic flame - off (EF0))(未示於圖中)加熱該金線24〇 (或是 銘線)使其成為液態。熔融的金屬因表面張力而形成一球 2 6 0 °然後使毛細鋼嘴2 5 〇下降並且將該球2 6 〇置於該晶片 2 0 0的接墊2 1 0上。此時進行熱超音波接合,利用熱以及超 音波將接墊210與球26 0之間的保護層220去除並且使接墊 與球260結合。當結合完成時,將毛細鋼嘴25〇升起並切斷 球260與毛細鋼嘴250中的金線(或是鋁線)之連接,藉此 在接墊210上形成一凸塊23〇。 然,,如第2b圖所示,以同樣的步驟,重複在晶片2〇〇 上的每一個接墊2 20上形成一個直接與該接墊21〇結合接觸A method for connecting wires (or inscription wires) to the chip pads and the conductive traces (or wires of the lead frame) of the substrate. Referring to Fig. 2a ', the gold wire 2 40 is a capillary 250 of a wire drawn into a wire punch by vertical silver. An electronic igniter (electronic flame-off (EF0)) (not shown) is used to heat the gold wire 24 (or the name wire) to make it liquid. The molten metal forms a ball 2 60 ° due to surface tension, and then the capillary steel nozzle 250 is lowered and the ball 2 600 is placed on the pad 2 0 of the wafer 2000. At this time, thermal ultrasonic bonding is performed, and the protective layer 220 between the pad 210 and the ball 260 is removed by using heat and ultrasonic waves, and the pad and the ball 260 are combined. When the bonding is completed, the capillary steel nozzle 250 is raised and cuts the connection between the ball 260 and the gold wire (or aluminum wire) in the capillary steel nozzle 250, thereby forming a bump 23 on the pad 210. However, as shown in FIG. 2b, in the same steps, each pad 2 20 on the wafer 200 is repeatedly formed to form a direct contact with the pad 21

、最後,參照第2c圖,要測試該晶片2〇〇時,將具有〜 連接接點280的探測器270直接置於該晶片2〇〇上。由於該 凸塊230與接墊21 〇有良好的電性連接,當連接接點28〇凸 塊230接觸時,探測器27〇便能經由凸塊23〇與接墊2ι〇電性 連接進而執行測試步驟。在測試步驟執行完成之後,將探 測器由半導體兀件表面移去。以上的處理與測試方法亦適 用於晶圓等其他半導體元件。 之後可以乾蝕刻或是濕蝕刻的方式將半導體晶片上的 凸塊(例如第2a —2c圖中之凸塊23〇 )移除。或是可直接在Finally, referring to FIG. 2c, when the wafer 200 is to be tested, a detector 270 having ~ connection points 280 is directly placed on the wafer 2000. Since the bump 230 has a good electrical connection with the pad 21 〇, when the connection contact 28 om the bump 230 is in contact, the detector 27 〇 can be electrically connected to the pad 2 om through the bump 23 〇 and then execute Test steps. After the test step is completed, the detector is removed from the surface of the semiconductor element. The above processing and testing methods are also applicable to other semiconductor components such as wafers. Thereafter, the bumps on the semiconductor wafer (such as the bumps 23 in Figures 2a-2c) can be removed by dry etching or wet etching. Or directly

第10頁 594024 五、發明說明(5) 泫凸塊上再執行一次打線製程,將該具凸塊之晶片電性連 接於一基板或是導線架上。 的主/要步驟。參照第3a圖,類似第一次打線製程,金線 240係被垂直餵入打線機的毛細鋼嘴(capilUry)25〇。以 第3a-3d圖係圖示,根據本發明一實施例,將具凸塊之 曰曰片藉由第二次打線製程而電性連接至一基板或是導線架 一電子點火器(未示於圖中)加熱該金線24〇 (或是鋁線 )使其成為液態。熔融的金屬因表面張力而形成一球 31 〇。參照第3 b圖,然後使毛細鋼嘴2 5 〇下降並且使該球 3^〇與該晶片30 0接墊210上的凸塊23〇接觸。此時進行熱超 音波接合,利用熱以及超音波使凸塊23〇與球31〇融合,並 形成凸塊320。參照第3c圖,當融合完成時,將毛細鋼嘴 250升起並且向另一目標33Q (例如基板的導電接墊或是導 線架之導線内端)移動形成一與該凸塊32〇連接之金屬弧 線。參照第3d圖,毛細鋼嘴250會於該另一目標33〇下降形 成第二焊接點(Weld)340以形成一完整的接線連接於# 300與目標330之間。然後再升起毛細鋼嘴250以切斷 鋼嘴250中的金屬線與第二焊接點34〇的連接。 ,4 a j d圖係圖示,根據本發明另一實施例,將具凸塊 ϊ i = ΐ由第二次打線製程而電性誇接至一基板或是導線 " 步驟。參照第4a圖,類似第一次打線製程,金線 係被垂直餵入打線機的毛細鋼嘴(capillary) 250。以 )伟I ^火器(未示於圖中)加熱該金線240 (或是鋁線 /、、為液態。熔融的金屬因表面張力而形成一球Page 10 594024 V. Description of the invention (5) A wire bonding process is performed again on the bump, and the wafer with the bump is electrically connected to a substrate or a lead frame. The main / main steps. Referring to Fig. 3a, similar to the first wire making process, the gold wire 240 is fed vertically into the capilUry of the wire making machine 25. 3a-3d, according to an embodiment of the present invention, a chip with a bump is electrically connected to a substrate or a lead frame and an electronic igniter (not shown) through a second wire bonding process. (In the figure) the gold wire (or aluminum wire) is heated to make it liquid. The molten metal forms a ball due to surface tension. Referring to FIG. 3B, the capillary steel nozzle 250 is lowered and the ball 3 ^ 〇 is brought into contact with the bump 23 on the wafer 300 pad 210. At this time, thermal ultrasonic bonding is performed, and the bumps 23 and the balls 31 are fused by heat and ultrasound to form the bumps 320. Referring to FIG. 3c, when the fusion is completed, the capillary steel nozzle 250 is raised and moved to another target 33Q (such as the conductive pad of the substrate or the inner end of the lead of the lead frame) to form a connection with the bump 32. Metal arc. Referring to FIG. 3D, the capillary steel nozzle 250 will drop at the other target 33 to form a second welding point (Weld) 340 to form a complete wiring connection between # 300 and the target 330. Then, the capillary steel nozzle 250 is raised again to cut off the connection between the metal wire in the steel nozzle 250 and the second welding point 34o. The 4 a j d diagram is an illustration. According to another embodiment of the present invention, the bump ϊ i = ΐ is electrically connected to a substrate or a wire by the second wire bonding process. Referring to Fig. 4a, similar to the first wire making process, the gold wire is fed vertically into the capillary 250 of the wire making machine. The fire wire (not shown) is used to heat the gold wire 240 (or aluminum wire /, and is liquid. The molten metal forms a ball due to surface tension.

第11頁 594024 五、發明說明(6) 310。參照第4b圖,然後使毛細鋼嘴25〇下降並且利用熱以 及超音波使該球3 1 0與目標3 3 0 (例如基板的導電接塾或是 導線架之導線内端)接合並形成凸塊41〇。參照第4c圖, 當接合完成時’將毛細鋼嘴250升起並且向晶片3〇〇接墊 210上的凸塊230移動形成一與該凸塊41〇連接之金屬孤 線。參照第4 d圖,毛細鋼嘴2 5 0會向晶片3 〇 〇接墊2 1 〇上的 凸塊230下降形成第二焊接點^61(〇34〇以形成一完整的接 線連接於晶片300與目標330之間。然後再升起毛細鋼嘴 250以切斷毛細鋼嘴25 0中的金屬線與第二焊接點34〇的連 接。根據本實施例之方法具有降低打線孤高之優點。 一本發明之特徵在於在測試製程之前,先以打線的方式破 裘待測的半導體元件的接塾上的絕緣層,並且形成一金属 凸塊直接與接墊電係連接。這個方法亦適合用於破壞接點 表,=導電的氧化物層。如此一來,在測試步驟中,探測 器只需以其連接接點與凸塊接觸便能順利測試該半導體元 件。因此,不需要對探測器施加額外的力 透接墊上的絕緣層,藉此能保護探測器以及其::識 點,降低探測器的耗損率。 -ίί本發明已以前述較佳實施例揭示,然、其並非用以限 ί鬥肉明二任何熟習此技藝者,在不脫離本發明之精神和 圍杏視可t各種之更動與修改。因此本發明之保護範 ㈤田視後附之申請專利範圍所界定者為準。Page 11 594024 V. Description of the invention (6) 310. Referring to FIG. 4b, the capillary steel nozzle 25 is lowered, and the ball 3 1 0 and the target 3 3 0 (such as the conductive connection of the substrate or the inner end of the lead of the lead frame) are joined by heat and ultrasonic waves to form a protrusion. Block 41o. Referring to FIG. 4c, when the joining is completed ', the capillary steel nozzle 250 is raised and moved toward the bump 230 on the wafer 300 pad 210 to form a metal isolated line connected to the bump 41. Referring to FIG. 4d, the capillary steel nozzle 250 will descend to the bump 230 on the wafer 3 00 pad 2 1 0 to form a second solder joint ^ 61 (0340) to form a complete wiring connection to the wafer 300 And the target 330. Then the capillary steel nozzle 250 is raised again to cut off the connection between the metal wire in the capillary steel nozzle 250 and the second welding point 340. The method according to this embodiment has the advantage of reducing the solitary height of the wire. The invention is characterized in that before the testing process, the insulation layer on the connection of the semiconductor element to be tested is broken by wire bonding, and a metal bump is directly connected to the electrical connection of the pad. This method is also suitable for Destroy the contact table, = conductive oxide layer. In this way, in the test step, the detector only needs to contact the bump with its connection contact to successfully test the semiconductor element. Therefore, no need to apply to the detector The extra force penetrates the insulating layer on the pad, thereby protecting the detector and its: identifying points and reducing the loss rate of the detector.-The present invention has been disclosed in the foregoing preferred embodiment, but it is not intended to limit it. ί Dou Ming Ming any cooked Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is defined by the scope of the appended patents.

第12頁 594024 圖式簡單說明 【圖式簡單說明】 第1 a-1 b圖:以剖視圖圖示根據一習用技術測試一半導 體元件的主要步驟; 第2a-2c圖:以剖視圖圖示根據本發明一實施例之方法 處理並且測試一半導體元件的主要步驟; 第3a-3d圖:以剖視圖圖示根據本發明一實施例之將一 具凸塊半導體元件打線連接至一基板或是導線架的方法的 主要步驟;以及 第4a-4d圖:以剖視圖圖示根據本發明另一實施例之將 一具凸塊半導體元件打線連接至一基板或是導線架的方法 的主要步驟。 【圖號說明】 100 半導體元件 110 接墊 120 保護層 130 探測器 140 連接接點 200 半導體晶 210 接墊 220 保護層 230 凸塊 240 金線 250 毛細鋼嘴 260 球 270 探測器 280 連接接點 300 晶片 310 球 320 凸塊 330 目標 340 焊接點 410 凸塊Page 12 594024 Brief description of the drawings [Simplified description of the drawings] Figures 1 a-1 b: cross-sectional views illustrating the main steps of testing a semiconductor device according to a conventional technique; Figures 2a-2c: cross-sectional views illustrating The main steps of a method for processing and testing a semiconductor device according to an embodiment of the invention; FIGS. 3a to 3d: cross-sectional views of a semiconductor device with a bump connected to a substrate or a lead frame according to an embodiment of the present invention; The main steps of the method; and FIGS. 4a-4d: cross-sectional views illustrating the main steps of a method for connecting a bumped semiconductor element to a substrate or a lead frame according to another embodiment of the present invention. [Illustration of number] 100 semiconductor element 110 pad 120 protective layer 130 detector 140 connection contact 200 semiconductor crystal 210 pad 220 protective layer 230 bump 240 gold wire 250 capillary steel nozzle 260 ball 270 detector 280 connection contact 300 Wafer 310 Ball 320 Bump 330 Target 340 Solder joint 410 Bump

第13頁Page 13

Claims (1)

594024594024 1、 、一種用以處理以及測試一半導體元件的方法,其中該 半導體元件包含複數個接墊設於其上以及一絕緣層設於該 接墊的表面上,該方法包含下列步驟·· 以打線的方式破壞在該接墊上之絕緣層使得一個第一金. 屬凸塊形成於每一接墊上並且直接接觸該接墊; 將一具有複數個連接接點的探測器移至該半導體元件上 使得每一連接接點電性連接一接墊上之第一金屬凸塊;以 及 經由該探測器的連接接點測試該半導體元件。 ( 2、 依申請專利範圍第1項之用以處理以及測試一半導體元 件的方法’另包含在對該半導體元件執行測試步驟之後, 將該探測器從該半導體元件移開,以及將該第一金屬凸塊 從該半導體元件移除。 3、依申請專利範圍第2項之用以處理以及測試一半導體{元 件的方法,其中凸塊移除步驟係由乾蝕刻達成。1. A method for processing and testing a semiconductor element, wherein the semiconductor element includes a plurality of pads provided thereon and an insulating layer is provided on a surface of the pad, the method includes the following steps: ... The insulating layer on the pad is destroyed in a manner such that a first metal is formed. A metal bump is formed on each pad and directly contacts the pad; a detector having a plurality of connection contacts is moved to the semiconductor element such that Each connection contact is electrically connected to the first metal bump on a contact pad; and the semiconductor element is tested through the connection contact of the detector. (2. The method for processing and testing a semiconductor element according to item 1 of the scope of the patent application, further comprising, after performing the test step on the semiconductor element, removing the detector from the semiconductor element, and the first The metal bump is removed from the semiconductor device. 3. The method for processing and testing a semiconductor device according to item 2 of the scope of patent application, wherein the step of removing the bump is achieved by dry etching. 4、 依申請專利範圍第2項之用以處理以及測試一半導體元 件的方法,其中凸塊移除步驟係由濕蝕刻達成。 5、 依申請專利範圍第丨項之用以處理以及測試一事導體元 件的方法,另包含在對該半導體元件執行測試步驟之後, 將該探測器從該半導體元件移開;以及執行〆打線製程以4. The method for processing and testing a semiconductor device according to item 2 of the scope of patent application, wherein the bump removal step is achieved by wet etching. 5. The method for processing and testing a conductive element in accordance with item 丨 of the scope of the patent application, further comprising removing the detector from the semiconductor element after performing a test step on the semiconductor element; and performing a wire bonding process to 594024 六、申請專利範圍 形成-第二金屬凸塊將該第〜金屬凸塊包含於其中以及一 連接線連接於該第二金屬凸魂與一基板或是導線架之間。 6、 依申請專利範圍第1項之用以處理以及測試一半導體元 件的方法,其中該'絕緣層係^該半導體元件表面之保護層 (passivation layer) ° 7、 依申請專利範圍第1項之用以處理以及測試一半導體元 件的方法,其中該絕緣層係為該接墊表面之金屬氧化物。 8、 一種將一半導體元件電性連接至一基板或是導線架的 方法,其中該半導體元件包含複數個接墊設於其上以及一 第一金屬凸塊形成於每一接墊上並且直接接觸該接墊,該 方法包含執行一打線製程以形成一第二金屬凸塊將該第一 金屬凸塊包含於其中以及一連接線連接於該第二金屬凸塊 與一基板或是導線架之間。594024 6. Scope of patent application Formation-The second metal bump includes the first metal bump therein and a connecting line is connected between the second metal bump and a substrate or a lead frame. 6. The method for processing and testing a semiconductor device according to item 1 of the scope of the patent application, wherein the 'insulation layer is a passivation layer on the surface of the semiconductor device ° 7. According to the method of item 1 of the scope of patent application A method for processing and testing a semiconductor device, wherein the insulating layer is a metal oxide on the surface of the pad. 8. A method for electrically connecting a semiconductor element to a substrate or a lead frame, wherein the semiconductor element includes a plurality of pads disposed thereon and a first metal bump is formed on each pad and directly contacts the pad The method includes performing a wire bonding process to form a second metal bump, including the first metal bump therein, and a connection line connected between the second metal bump and a substrate or a lead frame. 第15頁Page 15
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