TW588455B - Flash memory cell and fabricating method thereof - Google Patents

Abstract

A flash memory cell and a method for fabricating the same are described. The flash memory cell comprises a substrate, a select gate, a floating gate, a gate dielectric layer, a high-voltage doped region and a source region. The substrate has a first opening thereon and a second opening in the first opening. The select gate is on a sidewall of the first opening, and the floating gate is on a sidewall of the second opening. The gate dielectric layer is between the select/floating gate and the substrate. The high-voltage doped region is in the substrate under the second opening, and the source region is in the substrate beside the first opening. In the fabricating method of the flash memory cell, the select gate and the floating gate are simultaneously formed on the sidewalls of the first opening and the second opening, respectively.

Description

588,455 V. described invention (1) Field of the invention belongs The present invention relates to the structure and manufacturing method of a semiconductor device, and more particularly to a flash memory cell (F 1 ash M em 〇ry C e 1 1) the structure and manufacturing method. Preoperative technology to stack the extreme gate facing the floating pole brake system controlled by the Department of Cellular memory referred flash fast type typical crystalline / source multiplexing of a side like twenty-one their mass and materials in the pole structure gate junction facing float and its control electrode to the drain electrode configuration for operation of the shutter system referred flash memory cells used to read quickly see the gate electrode in this system as in the control, based on the time taken positive electrode side pressing plus floating gate is set high applied, in In the middle system, the gate is set to float, and the neutron method is used to make the lower gate of the circuit and add the gate to the gate. When the gate is floated, it is taken as the gate. The value of the gate is read. when the memory cell electrode facing the other gate referred applicator floats, •, all the rows may be electrically conductive Derivation memory cell will not have channel that is the channel that is, the other side through the pressure applicator will often spend production over time = 0 flash quickly removed. Wiping off the judgment, and then whether to pass the gate to be set to even out all floating 3t3t, Fang Shizai weight lower row electrode opposing strict multi-gate over the floating more like this is now the deaeration i.e., wiping, of like charge are electrically through the existing legitimate e) band; AS er flow of electrical leakage and Γ-- ve, green: 0 mind memory gate electrode producing a heavy he points out scrambling seed from which the dry extract know Xi Yan e) the title at Q t dagger S ^ n ~ decision (0 solution state is shaped. pass for conducting operations were taken Sell Sell = port who will extracellular the gate £ i.e. channel, b pass} another) e ^ 6 t & tat a G May G Li Si t C had iet plel into ss shaped floating oxides such as Λ wiping gate selection and had selected in degrees, due to a spacer group floating electrode shaped w side M i extremely r * layer, opposite of this

11041twf.ptd Page 6588455 V. invention is described in (2) except when the lower channel so that the phenomenon of continuous conduction, which side of the select gate electrode of memory cells to exert control channel on / off effect. Such selection gates are mostly composed of polycrystalline silicon and are often defined together with the control gate. Although the conventional separation gate design can effectively avoid the problems caused by excessive erasure, because the selection of the gate system is formed after the formation of the floating gate, the process of the separation gate requires two steps of polycrystalline silicon deposition. It takes more time. SUMMARY OF THE INVENTION An object of the present invention, i.e. to provide a flash memory cell (F 1 ash M em 〇ry C e 1 1) of the structure having a separate gate in the design, in order to avoid floating gate of the over-erase phenomenon The various problems caused, and it only needs to perform the polycrystalline silicon deposition step once in manufacturing. Another object of the present invention is to provide a method for manufacturing a flash memory cell, which requires only one step of polycrystalline silicon deposition during the manufacturing process of the separation gate to save time and cost. The flash memory cell of the present invention includes a substrate, a selection gate, a floating gate, a gate dielectric layer, a high-voltage doped region, and a source region. Wherein the substrate has a first opening, and the bottom of the substrate is provided with a second opening more first opening, the second opening is less than the width of this first opening, a second opening and a depth starting from the substrate surface is larger than the first opening . The selection gate is located on the side wall of the first opening, the floating gate is located on the side wall of the second opening, and the gate dielectric layer is located between the selection gate and the substrate and between the floating gate and the substrate. The high-voltage doped region is located in the substrate at the bottom of the second opening, and the source region is

11041 twf. Ptd Page 7588455 V. invention is described outside of the substrate in the first opening (3). Among them, the high-voltage doped region can serve as both the control gate and the drain region. The above-mentioned flash memory cell of the present invention may further include an insulating layer and a contact window, wherein the insulating layer is located above the substrate and covers the selection gate and the floating gate, and the contact window penetrates the insulating layer and connects to the high voltage. The doped regions are electrically connected. The contact window is used to provide a high voltage to the high-voltage doped region. The manufacturing method of the flash memory cell of the present invention is as follows: firstly providing a substrate, and then forming a first opening and a second opening in the substrate, wherein the second opening is formed in the substrate at the bottom of the first opening, and the second opening The width is smaller than the first opening, and the depth of the second opening from the substrate surface is greater than the first opening. Next, a high-voltage doped region is formed in the substrate at the bottom of the second opening, and a gate dielectric layer is formed on the substrate surfaces of the first and second openings. Then, a first conductor gap wall is formed on the side wall of the first opening as the selection gate; and a second conductor gap wall is formed on the side wall of the second opening as the floating gate. Next, a source region is formed in the substrate outside the first opening. In the method of manufacturing a flash memory cell of the present invention, the more can be formed after the source region is formed on a base insulating layer, which covers the selection gate lines and the floating gate, and then formed through the insulating layer electrically doped region connected to the high voltage contact windows, which a high voltage line for providing a high voltage on the doped regions. As mentioned above, the selection gate and floating gate of the flash memory cell of the present invention are in the form of a gap wall, and are formed on the sides of the first opening at the same time.

11041twf.ptd page 8 588 455 V. invention described opening of the wall and the second side wall (4), so that during production split gate structure only once a conductive material (e.g., a polycrystalline Si) deposition step. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Embodiments The following describes the preferred embodiments of the present invention. The flash memory scheme of the embodiment is supplemented by Figures 1 to 6, but the description of this preferred embodiment and Figures 1 to 6 are not intended to limit the scope of the present invention. Referring to FIG. 1, a substrate 100 is first provided, which is divided into a peripheral circuit area 102 and a memory cell area 104. Next, the pad oxide layer 108 and hard mask layer 110 are sequentially formed on the substrate 100, wherein the method of forming a pad oxide layer, for example, thermal oxidation (Thermal Oxidation), and the hard mask material layer 110 of the screen, for example, silicon nitride which is formed, for example, a method in S i Η 2 C 1 2 / N Η 3 is a low-pressure chemical vapor deposition reaction gases (LPCVD). Next, a patterned photoresist layer 114 is formed on the hard mask layer 110, and the photoresist layer 114 is used as a mask to etch away the exposed hard mask layer 1 1 0 and continue to etch the pad oxide layer 1 0 8 downward. And a substrate 100 to form a first opening 1 1 8 in the substrate 100 of the memory cell region 104. During the etching of the first opening 1 1 8, the formation conditions of the polymer can be controlled so that the first opening 1 1 8 has a rounded bottom corner, the purpose of which will be described later. Referring to FIG 2, followed by removal of the residual photoresist layer 114, and then memorized in the cell region 104 of the mask layer 110 to form a gap with the sidewall of the first opening 118

11041twf.ptd five page 9 588 455, description of the invention (5) the wall 122, which is made, for example, silicon oxide, and which is formed to the side, for example: chemical vapor deposition method, first on the substrate 100 is formed a conformal A silicon oxide layer (not shown), and then anisotropically reverts to this conformal oxide layer. Next, using the mask layer 1 10 and the partition wall 12 2 as masks, the exposed substrate 100 is etched to form a second opening 1 2 6 in the substrate 100. As shown in Fig. 2, the width of the second opening 126 is smaller than that of the first opening 118, and the depth of the second opening 1 2 6 from the surface of the substrate 100 is greater than that of the first opening 1 1 8. Then, the mask layer 1 1 0 and the partition wall 12 2 are used as the mask for ion implantation, and a high-voltage doped region 1 3 0 is formed in the substrate 1 0 0 below the second opening 1 2 6. As the control gate and drain regions. As will be described later, this high-voltage doped region 130 will be subjected to a high voltage during the stylization / erasing process of the memory cell, hence the name. Further, although the method of the present embodiment of the first opening 118 and second opening 126 formed in the manner described above based, but not limited thereto are formed. For example, formation of this second opening may be similar to the dual inlaid opening (D ua 1 D a in ascene 0 pening) manner, i.e., a depth less than the first predetermined value a second opening, and then a photoresist layer defining a first opening Then, the substrate is etched to form a first opening, and at the same time, the depth of the second opening reaches a predetermined value. Referring to FIG 3, followed by removal of the pad oxide layer 108, the mask layer 110, and spacer 122, which is preferably a wet etching method, so as not to damage the surface of the substrate 100. Then forming a gate dielectric layer 134 and the conductive layer 138 on the substrate 100, wherein gate dielectric layer 134 made of for example silicon dioxide, formed by thermal oxidation method, for example; the conductor layer 138 of for example, made of polysilicon, for example, a method of forming a low pressure chemical vapor deposition of silicon to methane (S i Η 4) of the reaction gases (LPCVD).

11041 twf. Ptd page 10588455 V. invention is described in (6) Referring to FIG. 4, then in the polycrystalline silicon layer 102 is formed in the peripheral circuit region 142, and defining the periphery of the anti-reflection layer 138 photoresist layer pattern element of the gate 146. Then, the polycrystalline silicon layer 1 3 8 is anisotropically etched to form two selection gates 1 3 a on both side walls of the first opening 1 1 8 and two side walls of the second opening 1 2 6 are simultaneously formed. A plurality of floating gates 1 3 8 b are formed on the peripheral circuit area 102 at the same time as gates 1 3 8 c of the peripheral elements. That is, two memory cells are formed in the first opening 1 1 8 and the second opening 1 2 6. In addition, since the first opening 1 1 8 and the second opening 1 2 6 both have rounded bottom corners, the portions of the gate 1 3 8 a and the floating gate 1 3 8 b that are close to the base 1 0 0 are not selected. Form corners without problems such as leakage caused by excessively high electric fields. Referring to FIG 5, followed by a source extension / drain region (S / D e X t e n s i ο η) ion implantation to form the electrode 138 on both sides of c gate source / drain extension region 150. Then, an insulating gap wall 1 5 4 b is formed on the side wall of the gate 1 3 8 c, and an insulating gap wall 1 5 4 a is formed on the side wall of the selected gate 1 3 8 a and the floating gate 1 3 8 b. This insulating gap The material of the wall 1 5 4 a / b is, for example, silicon nitride, and the formation method is, for example, forming a conformal silicon nitride layer on the substrate, and then performing anisotropic etching. Next, select gates 1 3 8 a, floating gates 1 3 8 b, and gates 1 3 8 c of peripheral components as masks, and perform ion implantation to form two source regions 1 5 8 a and Source / drain regions of peripheral elements 1 5 8 b. Referring to FIG. 6, and then the insulating layer 160 is formed, for example, a material which is oxidized to plasma chemical vapor deposition (P E C V D) is formed on the silicon substrate 100. Then, a contact window 1 6 4 is formed which penetrates the insulating layer 160 and the gate dielectric layer 1 3 4 and is electrically connected to the high voltage doped region 1 3 0, and is formed on the insulating layer 1 60

. 11041twf ptd 11588455 Page V. invention is described in (7) - such that the wire 168. During the formation of the contact window 64 in Shu, Xi nitrogen fossil material to protect the insulating spacers 154a floating gate 138b, so that its window 164 in contact with the short circuit. In this flash memory cells for feeding stylized / erase operation ', 130 high electrical voltage required strict high doped region 168 can be provided by a wire 164 and the contact window. Further, while the present embodiment to embodiment based electrical contact window 64 Shu memory cell connected to a high voltage above the doped regions 130, to provide high voltage required for the operation, but if the high voltage line doping region 130 is formed $ buried conductors of energy, i.e., the contact window 164 need not be formed over each memory cell, as long as the contact window can be formed at the end of the line voltage g of the doped regions 130. Please refer to FIG. 6, a flash memory cell of the present invention in the high voltage region 130 may be doped at the same time as the control gate and drain regions. Specifically, in this stylized operation of the flash memory cell, when a high voltage is applied to the high-voltage doped region 30 at the bottom of the second opening 126, the gate 138b is placed on the side of the second opening 126. That is, a sufficient voltage is induced to cause the channels in the pelvic sidewall substrate 100 to conduct. At this time, as the selection gate Shu side 3 8a provision of open channels in the substrate, and applying a low voltage to the source region 58a Shu, f shell electrons from the source region 1 5 8 a flow of the high-voltage region doped〗 3 billion, and there are eighteen in injected into the floating gate electrode 138b, as shown, this method is the transverse arrow ° / on injection, a longitudinal channel can be changed as hot electron injection method (channel hot Eleetr C heteroatom voltage region Η EI). On the other hand, a high voltage is applied during an erase operation, so that the electronic material Fowler-Nordheim tunneling in the floating gate move to the arrow shown in FIG. 3 the high voltage doped region. /

588,455 V. invention is described in (8) described above, preferred embodiments of the present invention select gate flash memory cell according to the floating gate electrode based material is deposited on the conductor - the etch-back manner, while the first openings are formed in the the opening of the side wall and a second side wall, in the production process so split gate structure only once a conductive material (e.g., a polycrystalline Si) deposition steps. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

11041twf. Ptd 13588455 Page Brief Description of the drawings FIG 1~6 illustrates a sectional view of the flow of manufacturing the flash memory according to the preferred embodiment of the present invention, wherein FIG. 6 shows a first embodiment of a flash preferred embodiment of the present invention Memory cell structure. FIG Flag Formula 100 substrate 102 described peripheral circuit region 1,041,108 hexyl memory cell region pad oxide layer 110 hard mask layer 114, a photoresist layer 118 of the first opening 126 of the second spacer Ό 122 apart doped regions voltage V 130 South 134 gate dielectric layer the conductor layer 138 1 3 8 a, 1 3 8 b, 1 3 8 c: select gate, a floating gate, a gate 142: anti-reflection layer 146: resist layer 150 : source / drain extension region 1 5 4 a / b: an insulating spacer 1 5 8 a · source regions 1 5 8 b · source / > and region

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Claims (1)

588455 VI A range patent flash memory cell, comprising: a substrate, on which - a first opening, the first opening and the bottom of the substrate is provided in a further second opening of the second opening a width smaller than the first opening and the depth of the second opening starting from the surface of the substrate is greater than the first opening; a select gate, a sidewall of the first opening; a floating gate, located at the second opening the side walls; a gate dielectric layer, located between the selection gate and the substrate and the floating gate electrode between the substrate; a high voltage doped region, located at the bottom portion of the second substrate opening; and A source region is located in the substrate outside the first opening. 2. The flash memory cell according to item 1 of the scope of patent application, wherein the first opening and the second opening have rounded bottom corners. 3. The flash memory cell described in item 1 of the scope of patent application, wherein the material of the selection gate and the floating gate includes polycrystalline silicon. 4. The flash memory cell according to item 1 of the patent application scope, wherein the gate dielectric layer includes a gate oxide layer. 5. The flash memory cell of the application of paragraph 1 patentable scope, wherein the high voltage line at the same time as a doped region drain region and a control gate. 6. The flash memory cell of the application of paragraph 1 patentable scope, which is located further comprises the selection gate and the floating gate one sidewall insulating spacers. 7. Patent application range of item 1 of the flash memory cell, further comprising an insulating layer with a contact window, wherein . 11041 twf ptd page 16588455 six, patented scope of the insulating layer positioned over the substrate, and covering the select gate and said floating gate; and the contact window system through the insulating layer and is doped with the high-voltage Miscellaneous areas are electrically connected. 8. The flash memory cell of the application of paragraph 7 patentable scope, further comprising an insulator positioned between the sidewall of the floating gate is in contact with the window spacer. 9. The flash memory cell of the application of patentable scope of item 8, wherein the insulating material comprises silicon nitride of the spacers. . I 0 - A method for producing a kind of flash memory cells, comprising the steps of: providing a substrate; forming in the substrate a first opening and a second opening, wherein the second opening is formed to the first line of the bottom of the opening in the substrate, the opening of a second width smaller than the first opening, starting from the surface of the substrate and the depth of the second opening greater than the first opening; forming a high voltage to the base of the second dopant at the bottom of the opening heteroaryl region, a first opening formed on the surface of the second substrate and the opening of a gate dielectric layer; forming a first conductive spacer on the first sidewall of the opening, to serve as a select gate, while in A sidewall of the second opening forms a second conductor gap wall as a floating gate; and a source region is formed in the substrate outside the first opening. II. Where manufacturing a flash memory cell of the first patent range 0 17588455 11041twf ptd page six, the scope of patented method, wherein the method comprises the steps of first opening formed: one forming a patterned mask layer on the substrate having the pattern of the first opening; in this the mask layer as a mask to etch the substrate, a manufacturing method to form the first opening 〇1 v 2. If the application of the flash memory cell of a first scope of the patent, wherein the first opening has a rounded bottom corner. 3. The method according to Claim 1 for manufacturing the flash memory cell of a first range of patents, wherein the opening of the second method comprises the steps of: forming a spacer on a sidewall of the first opening and the cover layer of the curtain ; and in the mask layer and the spacers as a mask to etch the substrate to form a second opening. 14. The method for manufacturing a flash memory cell according to item 13 of the scope of patent application, wherein the second opening has a rounded bottom corner. 5. The method according to Claim 1 for manufacturing a flash memory cell of the range of the first three patents, a method wherein a high voltage comprises forming a doped region in the substrate of the second bottom opening: In the mask layer and the spacers as a mask, ion implantation of the substrate. 16. The method for manufacturing a flash memory cell according to item 10 of the scope of patent application, wherein the method of forming the gate dielectric layer on the surface of the substrate in the first opening and the second opening includes thermal oxidation law. 1 7. The method for manufacturing a flash memory cell as described in item 10 of the scope of patent application, wherein the method of forming the first and the second conductor gaps simultaneously . 11041 twf ptd six pages 18588455, patent applications include: forming a conformal conductive layer on the substrate; and anisotropically etching the conformal conductive layer to a first opening in the sidewall of the first conductor is formed spacer, while the second conductor is formed on the sidewall of the second opening of the spacer. 8. The method according to Claim 1 for manufacturing a flash memory cell of the first item of the scope of patent 17, wherein the conductive material comprises a conformal layer of polycrystalline silicon. . 19 The method of manufacturing a flash memory cell of the first patent application 0, more comprising the steps of: forming an insulating layer on the substrate, the insulating layer covering the select gate line and the floating gate electrodes; and forming an insulating layer through one of the contact window, electrically connected to the high voltage: push heteroaryl region. 20 as a first patent range nine manufacturing method of the flash memory cell, further comprising prior to forming the insulating layer, forming an insulating gap electrode and side walls of the floating gate to the gate of the selection step, the system for protecting the insulating spacers of the floating gate during the formation of the contact window in. 11041twf. Ptd page 19