TW578298B - DRAM having trench capacitor and the manufacturing method thereof - Google Patents

Abstract

The present invention provides a DRAM having trench capacitor, whose first electrode plate is installed at the rim of the lower portion in the island-like semiconductor structure on the substrate. The second electrode plate is installed inside the surface of the lower portion in the island-like semiconductor structure and the substrate surface outside the island-like semiconductor structure. The dielectric layer of capacitor is installed between the second electrode plate and the first electrode plate. In addition, the transistors controlling the trench capacitor is installed on the island-like semiconductor structure. The transistor has a first source/drain; a second source/drain and a gate electrode. Furthermore, the buried strap is disposed between the second source/drain and the first electrode plate, and the conductive plug is disposed between the first source/drain and the bit line. The present invention also provides the manufacturing method of DRAM having trench capacitor.

Description

578298 V. Description of the Invention (l) [Field of the Invention] The present invention relates to a structure of a dynamic random access memory (J) ynami C Random Access Memory (DRAM for short) and a method of manufacturing the same ', and particularly to a device having a Structure of trench capacitor (Trench capacitor) dynamic random access memory and manufacturing method thereof. [Background of the Invention] In the technology of a single crystal integrated circuit, a capacitor is a common component. In DfAM chips, a large number of capacitors are required, and each capacitor must be combined with a Field Effect Transistor (FET). ^ ΐ The increase in the required memory capacitance must increase the capacitor per unit area = packaging density. However, the traditional design method of the flat capacitor will occupy too much surface area of the chip. Another technique for designing capacitors in deep trenches of silicon crystals is to obtain a larger capacitance density and future trends. However, trench valleyrs need deep and narrow trenches with aspect ratios that are not high, and their aspect ratios usually exceed 40: i. The trench electrodes i: i ϋ are deposited on the deep and narrow trench sidewalls as described above. And fill in the mixed polycrystalline stone layer pride as the lower electrode plate. & Upper electrode plate. The doped silicon trench wall is the same: a trench with an aspect ratio greater than 4: 1 is the apparent ratio. When the height-to-width ratio of deep trenches exceeds 10: 1, it is: more difficult. The technology of combining the upper part of the deep trench will make the reactants diffuse to the bottom of the deep trench; usually. The result of this: = 0593-7966TW (N); 91009TW; amy.ptd 578298

The force u is buried and filled, and the hole is the required groove. Abbreviation Title Deep groove If a hole is created in the filling of the deep groove. Such a hole would seriously cause the resistance value of the bur ied plate (BP). Once deep trench ^ is inserted into silicon, the holes in it will not disappear with the additional process. In fact, the cavities will become larger and larger with different tempering cycles. In particular, the case of filling amorphous silicon with deep trenches will More serious. 1 In addition, as the number of memory cells integrated into a single chip increases, the size of components continues to shrink. However, the reduction in the size of the device will cause the misalignment of the patterns of the deep trench (DT) and the active AA. The question derived in this way is that because the resistance of the buried strap (BS) is related to the overlap of the groove and the active area, the inaccurate overlap of the deep trench and the active area will cause a serious resistance value of the embedded strap. Change. In order to make the above-mentioned questions and problems more comprehensible, the following explanations are made with drawings. Figure 1 is a top view of a conventional semiconductor device with many trench capacitors. The memory cell on the left shows the misalignment of the deep trench and the active area, while the right side shows the normal layout. Fig. 2 is a η-11 cross-sectional view of Fig. 1, which shows a schematic diagram of a memory unit. Fig. 3 is a sectional view taken along the line III-III in Fig. I. The S-memory cell in FIG. 2 includes a trench capacitor 10 in a deep trench DT, a shallow trench isolation region STI to define an active region AA, a bit line contact window CB 'gate electrode G (word line The portion corresponding to the active area AA), the gate oxide layer 16, and the IH source / drain electrodes 12 and 14. In addition, a buried strap (Bs) connecting the deep trench capacitor node to the source / drain H of the transistor is also included. Traditionally, transistors are usually

578298 V. Description of the invention (3) = side of the trench DT, and such a memory cell will occupy a relatively large substrate as shown in FIG. 3, when the deep trench DT and the active region ^, the deep trench DT and the active region ^ The heavy Nie Danhe and the inter-gate system are relatively different on the 22nd, and the overlap on the other side is 24. [Objective and Summary of the Invention] The object of the present invention is to provide a method for manufacturing a trench capacitor. Forget about the problem caused by the high aspect ratio encountered by the first hole. In addition, another object of the present invention is to provide a process with six DRAMs. By using the same master ^ 1 and deep trench (DT) , Can reduce one: two active area (AA) free from the problem of misalignment between the active area and the ice trench. And the problem of misalignment between the electrode and the active area. Avoiding the gate electrode In addition, the purpose of the present invention is to provide a trench capacitor # @ i 元, so that the size of the memory cell can be further reduced The lower face of the random access conductor structure: the perimeter is first: the electrode plate is arranged in the lower part of the surface of the island-like half body structure on the base. The good electrode plate is arranged in the island-like semi-conductive surface. A capacitor dielectric resides between the substrates of the IM substrate. A transistor 嗖 w °; the second electrode plate and the first-source electrode of the first electrode plate, and the electrode, the first body, and the D structure 'this transistor has one coin and one source / none A pole and a gate band are provided at the second source / drain & One is buried between the anode and the first electrode plate. A conductive plug 578298 V. Description of the invention (4) It is disposed between the first source / drain and the bit line, and the drain to the bit line. It is used to connect the first source electrode, to access the periphery of the memory including the t portion, and each storage capacitor includes a bi-shaped first electrode plate, a capacitor dielectric layer, and a female-tubular first electrode. Brother one electrode plate. ^ ^ i-plate β is placed on the side wall of the lower part of the mother-island semiconductor structure. The mother-capacitor dielectric layer arrangement is called: ::: inside the body structure, and extends to the island-shaped semiconducting = the island-shaped semiconducting electrode plates are adjacent to each other ": within the base of the ' The island-shaped semiconductor structure has an electric sun and solar body at the pole, a first-code electrode / electric sun and sun body including a first source / drain, a first source / drain, and a gate electrode. # 番 识 极板。 And embed a buried band in each second source electrode ... Set a conductive plug 1 between each -th-source = corresponding lines to make each other electrical A method for manufacturing a trench-selective w-body is invented and provided. The method of dynamic random access memory is summarized as follows. A deep trench f is defined in the substrate to form an island-shaped semiconductor structure moving region. Next, a burrow was formed in Xiangzhuang's main road to defend the basket in a sentence-like manner. It was called a horse-like host, and it formed a pit into the surface of the lower part of the π 4 + conductor, σ, and the surface of the bottom of the deep trench. A capacitor coil and an electric # plate are formed on the second electrode plate of the Dan. And it is embedded in the first layer "electrical layer." Then, the island-shaped semiconductor junction 966TWF (N); 91009T1V; amy. Ptd V. Description of the invention (5) = ί peripheral device dielectric layer surface formation-compliance pipe !! = = plate. Then 'formed on the island-like semiconductor structure-electricity: gate ] The body f has a first source electrode and a second source electrode / drain electrode as follows: Ϊ :; continued between the second source electrode and the-electrode plate after -U To form a conductive plug to connect the -source / drain to the [Example] structure with a trench capacitor (DRm: a dynamic random access memory with trench capacitor) The structure, = island body: Second, the container, the crystal system, Fengdao Junshe :: The structure storage capacitor is set on this island to the smoke :::: the peripheral edge of the surface. The following will be matched with the illustration and 5f DRAM 2Upper: Detailed description of construction. Among them, FIG. 4F is a top view of the trench capacitor type, and FIG. 5F is a VV cross-sectional view of FIG. 4F. As shown in FIG. 4F and FIG. 〇, for example, the semiconductor soil-the best is a silicon substrate), the upper part (that is, the surface layer) has an island-shaped semiconductor structure arranged in a matrix 106. / The radio and television crystal 1 " is arranged above the island-like semiconductor structure 1G6, and is stored, and the mc is arranged on the periphery of the lower part of the island-like semiconductor structure 1G6. — The storage capacitors ^ each include a tubular first electrode plate 114, an electric valley ... The layer 112 and the second electrode plate 110. Among them, the tube-shaped first electrode: The plate 114 is disposed on the side wall of the lower part of the island-shaped semiconductor structure 106, and the material is 5. Description of the invention (6) It may be a doped complex Silicon. The capacitor dielectric layer 112 is disposed between the tube electrode plate 114 and the second electrode plate 11G, and the material f may be oxygen.] Silicon ⑽) laminated, silicon oxide-silicon nitride_stone oxide (He is similar to this Those of nature. The second electrode plate J 丨 〇θ or 1: 6 ′ and the base structure plates 110 extending between the island-shaped semiconductor junctions are adjacent to each other and are electrically connected to each other to form a common plate. The pattern of this second region is grid_shaped. The plate 110 is doped. Each transistor τ includes a first source / drain 123, a pole / non-pole m * —the gate electrode G ′, where the second source / no second electrode is the tubular first electrode. The plates 114 are electrically connected through the embedded band and the top-to-bottom source / negative electrode 123 and the corresponding bit view. Which corresponds to the island-shaped semiconductor junction _: two-line Uord llne) WL is used as the closed-electrode g of the transistor τ, and the adjacent tubular first electrode plate U4 of the storage capacitor c is placed away from the structure i16a. The pattern of the isolation structure 1163 is in a lattice shape (',] =, Γά). This isolation structure 1163 is located near the second source / non-electrode 124, which is lower than the top of the tubular _ electrode plate 114, and installs one in other areas (1 d = sin near the first source / drain). (123 end) of the isolation structure ιΐ6 & the same degree of the top of the tubular first electrode plate 114. -75 ± The second electrode plate 1 of the storage valley device C 1G is separated from the first source / drain 123 and the second source / drain 124 of the transistor T ′ by a conductivity between each other Interfere with each other. In addition, the above-mentioned storage capacitor ^ 578298 V. Description of the invention (7) 1: The first electrode plate 114 is also separated from the first source / drain of the transistor T by a distance of 23 to ensure that the conductivity between each other will not be Phase interference. Manufacturing Method of DRAM with Trench Capacitor The following is a detailed description of an embodiment of a manufacturing method of a structure of a DRAM with trench capacitor according to the present invention with reference to FIGS. 4A to 4F and FIGS. 5A to 5F. 4A to 4F are top views, and 5A to 5F are V-V sectional views of 4A to 4F. As shown in FIG. 4A and FIG. 5A, a samarium substrate 100 is provided, for example, a stone XI. At the bottom, a mask layer is formed on the substrate 100. The mask layer 102 is, for example, a samarium oxide layer and a nitride. The evening layer is composed of a matrix pattern.

In order to expose the deep trench area, it can be used to simultaneously define the active area (AA) and the trench area (DT). Next, a post-etching process is performed to transfer the pattern of this mask layer 102 to the substrate, so that a deep trench is formed in the substrate 100. The upper part of the substrate 100 (ie, the surface layer) is a matrix island semiconductor. The structure 106 is, for example, a silicon island, and the island-shaped semiconductor structure 106 is an active region. Next, as shown in FIG. 4B and FIG. 5B, a buried electrode plate (Bp) 1 and a compliant capacitor dielectric layer ϋ 2 are formed on the lower portion of the deep trench 104 and an island-shaped semiconductor structure is formed. The lower portion of 106 is formed with a compliant tubular electrode plate 114. Among them, the buried electrode plate 110 is a? -Type doped region, which is located inside the island-shaped semiconductor structure 106 and at the bottom of the deep trench 104. The buried electrode plate 11 The bottom doped regions are adjacent to each other and are electrically connected to each other to form a common electrode plate. The tubular electrode plate 4 is disposed around the island-shaped semiconductor structure 106, and is not disposed at the bottom of the deep trench. because

Page 10 578298 V. Description of the invention (8) The formed trench capacitor C surrounds the periphery of the island-shaped semiconductor structure ι06 surface portion. 22. The formation of the above-mentioned buried electrode plate 110 is, for example, forming an N + -type doped dielectric layer on the surface of the deep trench 104, such as 111 on arsenic-silicon glass. SlllCate glass (referred to as ASG), and then fill a deep trench with a photoresist material of a predetermined depth, and then remove the doped dielectric layer covered by the unresisted material by wet etching, and then doped the ^ layer through a thermal process. The dopants in the metal tend to penetrate into the substrate 100, and an N + doped region is formed on the "face" of the substrate in the deep trench 104 as a buried electrode plate 110, and then the photoresist material is removed. Then Form a layer of compliance = electric valley dielectric layer 112 and conductive layer on the entire surface of the substrate 100, and use etch back to remove the upper surface of the conductive layer to turn it into a tubular electrode plate 114 as shown in the figure. The material of the valley dielectric layer 112 is, for example, a laminated structure of oxide-nitride (ON) or silicon oxide-nitride-oxide (abbreviated as silicon oxide-nitride-oxide). 0N0) laminated structure. The material of the tubular electrode plate 114 is, for example, doped polycrystalline spar. Then, as shown in FIG. 4C and FIG. 5C, an insulating layer is deposited, and the material is, for example, silicon oxide. Remove the extra insulating layer above the mask layer 102 to form a trench spacer in the deep trench 104 11-6 from the structure, and then remove the mask layer 102. Then, as shown in FIGS. 4D and 5D, a gate is formed on the upper surface of the substrate 100 (ie, the upper surface of the island-shaped semiconductor structure 106). The oxide layer 12 is formed on the entire substrate 100, and the conductive layer is defined as a word line WL, and the word line WL corresponds to an island-shaped semiconductor structure.

Page 11 〇593-7966TW (N); 910〇9T ^; amy.ptd 578298 5. The area of the invention description (9) is used as the gate electrode G, and the word line WL is an insulating layer 1 22 Wrapped. Thereafter, a first source / drain 23 and a second source / drain 124 are formed in an area of the island-shaped semiconductor structure not covered by the gate electrode g. Then, as shown in FIG. 4E and FIG. 5E, a buried band (bs) 1 2 6 is formed between the second source / drain 124 and the tubular electrode plate 114, so that the tubular electrode plate 114 and its corresponding transistor are formed. The second source / drain of τ24 is electrically connected. The formation of the embedding band 1 2 6 is, for example, forming a layer of a photoresist to define the pattern of the embedding band, and then using the photoresist as a mask, performing a money back engraving of the trench isolation structure 116 to form an exposed tubular electrode plate 114 The trench isolation at the top is 11 6 a. Continue to deposit a conductive layer, such as doped polycrystalline silicon, and etch back the conductive layer to form a buried connection between the second source / drain 24 and the tubular electrode plate 114. Into the band 126. Then, as shown in FIG. 4F and FIG. 5F, an f insulating layer 130, such as a borophosphosilicate glass layer, is formed on the entire substrate 100, and a contact 6 is formed in the opening 132 to expose the source electrode 124. A conductive plug 134, such as a tungsten plug, is formed in the contact window opening 132 to connect the source 124 and the bit line BL to be formed. — In summary, the manufacturing process of the trench capacitor of the present invention can reduce the definition of the active area (AA) #mask, because in the towel of the present invention, the active area is defined at the same time as the -mask, and the active area can be avoided. The problem of misalignment between Hegou 2 and now is to avoid misalignment between the gate electrode and the active area. In addition, the size of the memory cell of the trench capacitor of the present invention can be further reduced because the deep trenches formed in the substrate are simultaneously used to shape

Noodles page 12

578298 V. Description of the Invention (ίο) The definition of trench capacitors and deep trenches. Furthermore, the structure of the present invention is an etched island-like pattern, so there are no problems. Incidentally, although the photomask, but the difficulty and complexity of this optical path, although the present invention has limited the present invention, within any and range, when it can be used as the scope of the attached application 2: Isolation structure 'and the crystal system configuration On a horse-like semiconductor structure. When deep trenches, it is not etching the area outside the traditional hole structure, which means that the money engraving grid has the very high height and width encountered by traditional holes == to be extra—the channel is buried, (bs): accuracy The requirements are lower, so it will not increase the system as above, but it is not used to "familiar with the skill of the dagger", and it does not depart from these changes and decoration, so the spirit is too much, please define the scope of the patent.

578298 Schematic description [Schematic description] Figure 1 is a top view of a conventional semiconductor device with a trench capacitor. Fig. 2 is a cross-sectional view taken along the line 11-11 in Fig. 1 and shows a schematic diagram of a memory unit. Figure 3 is a sectional view taken along the line 111-111 in Figure 1. Figures 4A to 4F are top views showing the manufacturing process of a DRAM with a trench capacitor according to the present invention. 5A to 5F are V-V sectional views of FIGS. 4A to 4F. [Symbol description] Background of the invention Deep trench: DT active area: AA Shallow trench isolation area: STI bit line contact window: CB word line: WL ·

Idle electrode · G-groove capacitor: 1 0 Gate oxide layer: 1 6 N + source / drain: 12, 14 Buried band: BS overlap between deep trench and active region: 22, 24 Example section Base: 100

0593-7966TWF (N); 91009T ^; amy.ptd Page 14 578298 Brief description of the cover layer: 102 Deep trench: 104 Island-like semiconductor structure: 1 0 6 Embedded electrode plate: 11 0 Capacitor dielectric layer : 112 Tubular electrode plate: 11 4 Trench capacitor: C Trench isolation structure: 1 1 6, 11 6 a Gate oxide layer: 120 Word line: WL inter-electrode · G First source / drain: 123 Second source / drain: 124 Embedded band: 1 2 6 Insulating layer: 1 3 0 Contact window opening: 1 3 2 Conductive plug: 134.

Bit line: BL

0593-7966TWF (N); 91009TW; amy.ptd Page 15

Claims (1)

578298 Patent application scope 1. A dynamic random access memory with a trench capacitor-a substrate, the upper part of the substrate has an island: a dagger.-A first electrode plate, disposed on the island-shaped semiconductor: guide structure Peripheral; the surface of the lower part of the coincident thousand-conductor structure == an electrode plate, which is arranged in the lower part of the surface of the island-shaped semiconductor structure and in the surface of the substrate outside the island-shaped semiconductor structure · the plate; the capacitor dielectric layer '... The second electrode plate and the first electrode-transistor are disposed on the island-shaped semiconductor structure, wherein the transistor, a first source / drain, a second source / drain, and a gate electrode And a buried band is disposed between the second source / non-electrode and the first electrode plate. 2. The dynamic random access memory with a trench capacitor as described in item 1 of the scope of the patent application, further comprising an isolation structure covering the first electrode plate. 3. The dynamic random access memory with a trench capacitor as described in item 2 of the scope of the patent application, wherein the height of the isolation structure near the second source / drain side is lower than the first electrode plate The height of the isolation structure near the first source / drain is higher than the top of the first electrode plate. 4. The dynamic random access memory with a trench capacitor according to item 1 of the scope of the patent application, wherein the first electrode plate is a doped polycrystalline silicon layer, and the second electrode plate is an N + type doped Area. 5. Dynamics of trench capacitors as described in item 1 of the patent application 0593-7966TWF (N); 91009TlV; amy.ptd page 16 578298 6. Patent application scope random access memory, where the material of the buried band is doped polycrystalline silicon layer 0 6 The dynamic random access memory with a trench capacitor according to item 1, wherein the first electrode plate is tubular. 7. The dynamic random access memory with a trench capacitor as described in item 1 of the scope of patent application, further comprising a conductive plug for connecting the first source / drain to a bit line. 8 · A dynamic random access memory with a trench capacitor, suitable for a plurality of memory cells, where each memory cell includes a transistor and a capacitor, including: a semiconductor substrate with a plurality of island-like semiconductor structures; Each storage capacitor under a portion of an electrical structure is disposed at the periphery of each island-shaped semiconductor structure, and each storage capacitor includes a tubular first container dielectric layer and a second electrode plate; a mother plate and a tubular first electrode A plate is arranged on each island-shaped semiconductor junction, each capacitor dielectric layer is placed between each tubular first electrode and the second electrode plate; and the second electrode plates are arranged in the island-shaped semiconductor structures. Extending into the substrate between the island-like semiconductor structures, so that the first and second electrode plates are adjacent to each other and electrically connected to each other; an electric transistor is disposed on each island-like semiconductor structure , Each body includes a first source / drain, a second source / drain, and a gate = power; 578298 6. Scope of application for patent D. Isolation structure is arranged between the tubular first electrode plates; tubular tapes are arranged on each second source / drain and each-& shaped first electrode plate Between; and-pin electrical plugs, which are respectively used to connect each -th source / drain to the corresponding bit line. Access 9 notes, please ask: Item 8: The dynamic randomness of trench capacitors described above is far away, and the first electrode plates are adjacent to each other and are electrically connected to each other. Access 1々. Accompany the dynamic random access memory device with trench capacitor as described in item 8 of the India-India Gansli project, where the isolation structure is in a grid shape.醏 Fu Shangshang: The dynamic percentage of trench capacitors described in item 8 of the Green Patent Scope: "The isolation structure is close to each second source / isolation agency i = degree is lower than At the top of the corresponding tubular first electrode plate, the height of the chip 2 near each of the first pole / non-pole side is higher than the top of the corresponding first electrode plate. Lu Jiu 19 The dynamics of a trench capacitor as described in item 8 of the patent scope: potential ^ ^ α where the first electrode plate is a doped polycrystalline silicon layer, and the first electrode plate is an N + type doped Miscellaneous area. Lu She 19 The dynamics of a trench capacitor as described in item 8 of the second patent application: machine access s memory, where the material of the buried band is a doped polycrystalline silicon layer. Seven 4 = / The method for manufacturing a dynamic random access memory with a trench capacitor includes: providing a substrate; 0593-7966TWF (N); 91009TlV; ainy.ptd page 18 578298 6. The scope of the application for a patent forms a deep trench in the substrate, and the structure; an island-shaped semiconductor junction is defined by the meaning = $ the lower part of the island-shaped semiconductor structure An embedded second electrode plate is formed on the surface of the semiconductor substrate and the surface of the trench; a capacitor dielectric layer is formed on the embedded second electrode plate at the bottom of the trench; eight ^ two are adjacent to the bottom of the island-shaped semiconductor structure; ~ 丄, FU i — the surface of the capacitor dielectric layer on the periphery of the blade forms a compliant tubular first electrode plate; 1 an isolation structure is formed on the periphery of the island-shaped semiconductor structure to cover the electrode plate; A transistor is formed on the semiconductor structure, the transistor has a first source / drain, a second source / drain, and a gate electrode; and the second source / drain and the first electrode An embedded band is formed between an electrode plate. 15. The method for manufacturing a dynamic random access memory with a trench capacitor according to item 14 of the scope of the patent application, wherein the deep trench is formed in the substrate to define the step of the island-shaped semiconductor structure, The surface of the substrate further includes a mask layer for forming a deep mask on the substrate to form the deep trench. The mask layer forms the isolation structure around the island-shaped semiconductor structure to cover the first layer. Remove the electrode plate. 16 · The method for manufacturing a dynamic random access memory with a trench capacitor according to item 1 & of the scope of patent application, wherein the method for forming the tubular first electrode plate includes: on the capacitor dielectric layer Forming / compliant conductive layer; and etching back the conductive layer 4 0593-7966TWF (N); 91009TW; amy.ptd Page 19 578298 VI. Patent application scope 1 7 · The grooved electrical device and the dynamic random access memory described in item 4 of the patent application scope The manufacturing method of the body, wherein the method of embedding the tape includes: etching the isolation structure corresponding to the second source / drain side to expose the top of the tubular first electrode plate; depositing a conductive layer; And etch back the conductive layer. 18. The method for manufacturing a dynamic random access memory with a trench capacitor as described in item 14 of the scope of patent application, further comprising forming a conductive plug to connect the first source / drain to a bit line . 19. The method for manufacturing a dynamic random access memory with a trench capacitor as described in item 8 of the scope of the patent application, wherein the method of forming the conductive plug includes: forming an insulating layer to cover the buried tape, The isolation structure and the body; Ba forms a bit line contact window in the insulating layer to expose the first source / drain region; and fills the bit line contact window with a conductive material. 0593-7966TWF (N); 9100OT; amy.p t d p.20