TW575843B - Automatic collection method and device of single step interrupt debug message in bus cycle of computer system - Google Patents

Description

575843 V. Description of the invention (1) Detailed description: 1. Field of the invention: The present invention relates to a computer's debug PCI bus cycle single-step interrupt debugging. Y ,,,, 'Specifically refers to a 2. Background description: Dynamic collection device and method. Check the general computer system architecture, including the device, input device, output device, memory CPU, disk drive through the bus to achieve connections and data / more physical components, these components for the development of a computer-related product Z 2 Control functions. (debug) is often unavoidable, and it is also related, and in terms of debugging. The logic circuit analyzer is a technically-determined option, but it is limited by the logic circuit analyzer's debugging analysis limit. Therefore, how to effectively set the logic circuit is quite important for debugging time.纟 _% @ 彳 效 剪 PCI ® ^ # (Peripheral component Interc〇nn B s) A bus architecture commonly used by Muyu computer devices. The debugging of the PCI bus has been disclosed in the patent application previously filed by the inventors that the PCI bus cycle can be advanced into the month Λ. Step-by-step debugging techniques. With this one-step interrupt debugging setup, auxiliary early technicians can use the buses such as the address (Address), data (j) ata, and command displayed by the one-step interrupt debugging device. Cycle cycle (Bus Cycle) debugging related information as the logic circuit analyzer trigger setting

575843 V. Reference conditions of the description of invention (2) However, when step-by-step interruption and single-step interruption, it is also easy to manually key to the key due to the keystroke. In view of the single-step interruption and short-term computer-related, in order to gradually use the aforementioned The square device needs to use the artificial device to press the jump phenomenon or the flow cycle one by one. This error message is sent from the product's division and approximation mode to the manual display error. The single step is due to hand-related errors in searching for errors. There are still some pitfalls in debugging, such as the single-step gradual retrieval, interpretation, and recording of related debugging information, which is not only costly. In addition, the single-step interruption debugging device needs to interrupt the switch on the debugging device, which means that the muscles are fatigued and the continuous keystrokes are caused, resulting in the loss of information. In particular, a bus cycle set technology for a computer system is proposed in order to effectively reduce the process in an automated manner. Summary of the invention: Because of this, the t φ Ώ error technology of the present invention, # interrupt the brain by a single step: the system also removes the π 1 steep 'the letter between the 置 and the 逖 鳊 console' " ' Two: 乂 Make the debugging operation of the computer to be tested in an automated way to: During the entire debugging process ... Manually step down: 3 recordings of people '% can increase the efficiency of the debugging operation, but also signal loss : 2 mistakes: and debugging of electronic products that avoid key bounces during manual operation. J Chenghun is assisted by the present invention, which can effectively shorten the computer phase of the invention. $ 2 Single-step interruption and removal * Purpose: to provide a computer system bus Periodic placement and -far: automatic blue set method 'a single step interruption of the debugging equipment & mouth of the debugging information collection device to collect a to-be-checked electricity page 5 5. Invention description (3) Brain on debugging The confluence captured during the cycle is interrupted by a single step of the debugging device and the debugging message: the month, the error-related information, and the handshake of the box number continue to be generated. In the case of each subsequent bus cycle = change, The moving buffer memory. Xun Xinyong recorded in the remote console's Benming Ming another purpose is to provide-a single-step interrupt debugging information automatic collection device, the system's bus cycle interrupt debugging device and a remote console, in the remote ;! The device includes a single-step error information collecting device, which is connected to two channels through a signal and includes a debug device. A single-step interrupt debugging device can be produced ^ In this single-step interrupt debugging device for remote debugging consoles, the STE / -0C # signal is sent to a control logic generating circuit to generate a message collecting device for interrupt debugging Device. The signal is pulled and sent to a single step y, which achieves the above-mentioned purpose of the present invention. The Tai Road Rn includes a two-step interrupt debugging device in the specific embodiment of 二, ：, ：: f and the bit. Group enable signal latch control ΐ: Let ί lock control circuit 4 4 number control circuit, a buffer],-display logic of the main control signal (1 ^ 卯 #) to generate the logic = bee circuit, a required exchange number (IRDY #) Generate a logic circuit only-the master device is ready to count "'to record the computer to be tested in addition to-the number of cycles and the number of cycles; a level off counter, used to compare the current The counter is used to compare the number of cycles; = the number of turns off; a ratio. The counter of the remote control console's error message collection counter includes a control logic to produce 575843. 5. Description of the invention (4) The circuit can be generated. A switch mode is generated; the number sent by an interrupt device to the remote debug device is received when the remote debug device has received the pseudo-signal and the analog signal number counter is not equal. Signal to notify that continuous crawling has been broken by cycle count Testing computer, the MASTER—0C # master console generated by the example of the present invention and the attached drawing request signal; at least the debug phase sent by the debug phase master console and the debug lock sent by the master console are completed. The step-by-step debugging number is counted by the number of switching times and the number of times of closing. The single-step debugging information is collected and the remaining signals locked and the number of times of switching off are collected. And send it to the single-step interrupt debugging circuit to receive the single-step interrupt debugging signal and generate an interrupt request letter and a buffer according to it to temporarily store the single-step interrupt off message. Message Search — 0C # The message is divided into error devices one by one. The error-correcting device of the counting counter is fetched from the bus counter and is incorrectly related to its setting. Ten instructions such as the device number are collected. The device will continue to count the single-cycle counts to "borrow." After receiving the single-step interruption, the single-step interruption will be removed, and a switch-mode disconnection debugging device will be generated in the debugging-related information device. According to the count once, when the comparison result of the cycle comparator enables the MASTER_0C # step to interrupt the debugging device to continue the debugging message; and when the values are equal, the single-step middle row control is returned to the automatic collection. From the following Description of the preferred implementation: A single step in the first embodiment of the preferred embodiment shown in FIG. 1 is to display a computer 1 to be tested and the present invention.

Page 7 575843 V. Description of Invention (5) Intention. A typical computer 1 to be tested includes a central processing unit, a memory 12, a PCI bridge 13 (PCI Bridge), a PCI device 14, a PCI / ISA bridge 15 (PCI / ISA Bridge), and an ISA device 16. . The central processing unit 11 and the memory 12 are connected to the system bus 1 71. The system bus 1 71 is connected to a PC I bus 172 (Peripheral Component Interconnect) through the PCI bridge 13. The PCI bus 1 72 is a bus regulation proposed by the PC ISIG Association. It is mainly used as a high-speed talent bus 173 (Industrial Standard bus 173) in conjunction with rapid government processing such as in a Pentium-class microprocessor system. Can be configured with several ISA slots 16

Transfer function. Various PCI devices 1 4 (such as interface devices such as a local area network interface card, a video card, and an input / output interface card) can be connected to the PCI bus 172. The PCI bus 172 is connected to a jSA through a PCI / ISA bridge 15

Architecture), in the ISA 'for plugging various ISA devices, the single-step interrupt debugging device 2 of the present invention is connected to the PPI bus 72, and the remote console 3 includes-debug message == Device 30, the debug message 1 set, device 30 is connected to the i connection line 4 (for example, the eight J connection to the early step interruption division 2 through the signal line or the jig thimble method), the signal connection line 4 is used to transmit the debugging μ′a, the error device 2, and the debugging message_set 3. The two are the relevant control signals required for early interruption (Handshaking). The distance = 22 = ^ is The control host or terminal of the debugging system. The control port 3 of the control port 2 shows the single-step interrupt debugging installation diagram in Figure 1. It mainly includes a bit address and a command latching circuit. A data

575843

V. Description of the invention (6) ί: ί Zhineng ### Lock control circuit 22,-display device 23, one engineer two circuits 24, one buffer control logic circuit ", a request for the bus master control signal ( REQ #) generates a logic circuit 26, a master device ready signal 1 ^^ #) generates a logic circuit 27, a signal for instructing to retrieve the debugging information signal (master—0C #), a generation circuit 28, and a connector 29. " The connector 2 9 of the single-step debugging device 2 is connected to the debugging information collecting device 3 of the main console 3 via the signal connection line 4 for the address: data, control, and MASTER —0C # and other signals are transmitted to the debugging information wide-set device 30. The single-step interrupt debugging device 2 can be inserted into the PC I bus slot of the computer to be tested. In the standard pc { In the bus specifications, their pins can be divided into system support pins, address and data pins, interface control 彳 § numbers, bus arbitration signals, and error notification letters according to their functions. Pin functions related to the present invention And the definition is briefly as follows: PCICLK (Clock, PCI system clock): provides PCI bus clock No. AD0 ~ AD31 (Address Bus): 32-bit PC I bus address / data signal. C / BE3 # ~ C / BE0 # (C〇mmand / Byte Enable, command / bit Yuanzhi 旎 仏) · Multiplexed output command and byte enable signal. In the address phase, if it is activated, it indicates that the corresponding byte will involve data transfer; in the data phase, it is used as a command. Thousands of bus types. &Amp; FRAME # (Frame, data transfer frame signal) is started by the bus control, indicating the start of data transfer, and continues the entire action. ° 575843, invention description (7) between IRDY # (Initiat 〇r Ready, the master device is ready), started by the FX controller “indicates that the established data has been placed on the FX 2” or 疋 is ready to read data from the FX. TRDY # (Target Ready 'the target device is ready), activated by the selected device, indicating that the data has been placed on the bus, or that the device is ready to read data from the bus. Α DEVSEL # (Device Select ): Started by the selected device, I know the bus controller It already knows its own device location. REQ # (ReQuest, requires bus mastership): Started by a device that wants to be a bus controller to request a system bus from the bus arbiter. GNT # (Grant, Approved to surrender the master control of the bus): Started by the bus arbiter and informed the devices that require the use of the system bus to access the bus. The address and command latch control circuit 2 in Figure 2 includes one Address and command latch control logic circuit 211 (Address / Command Latch Logic), one address and command latch register 212 (Address / common Latch FIFO Register), one address and command buffer 213 (Address / Command Buffer). The address and command latch control logic circuit 21 1 can generate a bit address and command latch control signal to the address and command latch temporarily according to the decoded signal sent by the cycle number decoder 243 in the count control circuit 24. Register 212 to store the address bus AD [31..〇]

Page 10 575843

The command (c0_d) in C / BE # [3..0] is locked in the register 212. When the box in the PCI bus :: Tiger FRAME # 王 低 恶 starts, until GNT # is two: Λaddress Λ commands are sequentially locked to the address and command latch register 21 ". This Address and order lock: Register 212 is a first-in-first-out register (F0). Address and order buffer buffer 213 is also a first-in-first-out buffer (FIF〇), which is the address and address. And the command latch register 2 丨 2 and the address and command display unit 2 3 2 of the shell buffer interface, the operation of which is controlled by a buffer control signal generated by a buffer control logic circuit 25. Data The byte enable signal latch control circuit 22 includes a data and byte enable signal latch control logic circuit 221 (Data / BE # Latch

Log i c), a data and byte enable signal latch register 222 (Data / BE # Latch FIFO Register), a data and byte enable signal buffer 223 (Data / BE # Buff e r). The data and the byte enable signal latch control logic circuit 2 2 1 can generate a latch control signal to the data and bit according to the signal sent by the cycle number decoder 2 4 3 in the count control circuit 2 4. The tuple enable signal is latched in the register 2 2 2 to transfer the data in the data bus AD [31 ·· 0] and the bits in C / BE # [3 ·· 0] to The Byte Enable Signa 1 signal is latched into the data and the byte enable signal latch register 2 2 2. The data (Data) and C / BE appearing in the AD [31..0] bus when the IRDY # and TRDY # in the PC I bus are low and start until GNT # is high. The byte enable signal BE # in # [3 .. 0] will be locked to the data and the byte

Page 11 575843 V. Description of the invention (9) In the latch register 222. The data and the byte enable signal plug, 222 is a first-in-first-out register (FIF). Data and bytes. The ^ buffer 223 is also a first-in-first-out buffer (FIF), which is used as the group ί and bit. The enable signal latch register 222 is displayed with the data and the bit mountain energy signal. The data buffer interface between units 232, "The action is also controlled by the buffer control signal generated by the buffer control logic circuit 25: the staff display device 23 includes a single address and a command display unit 231 and one;; ΓΛ 能Signal display unit 23 2. Among them, the address and command Erwu 231 is connected to the address and command latch order buffer 213, which is used to display the data of the second key to be debugged and the byte enable signal display unit 232: In: [Shell and byte enable signal latch control circuit

The Si energy signal buffer 223 is used to display the state of the latched lean material and the byte enable signal of the period to be debugged. The control circuit 24 includes a counter reset circuit (e: R: set Circuit), a cycle number counter, 42 Cycle Number Dec, and a cycle number decoder.2 e

Number Decoder), an operation switch 244, a 2: 5 (De-b.—a),-switch times; compare l§ 247 (Comparator). Among them, the tune recounts the period of low hit 46, which is used to track the recording cycle; device ... in GNT # number). The number of cycles can be decoded from week # ^^ = counting from 〇

) / 5843 ----—.— V. Description of the invention (10) Γ :: Set the circuit 241 to 3 when the output of the comparator 247 is low. The value is 0. The count of the counter 242 and the number of switching counters 246 ^ ^ 245 ^ ^ ^ ^ ^ ^ The number of counters 246 printed in the bucket M is determined by the number of times the switch M # & 9Ar and 彔 switches. The switch signal can be rebounded: Λ except that the switch contact is temporarily unstable during operation = the number of counters 246 can also receive the switch analog signal sent by the remote control from 3 Erkiyi 30-a few aTE The j device 246 can be used to track and record the operation of the switch 244; the number of occurrences of the switching signal SW-EMULATE. i — The number of persons or the comparator 247 can be used to compare the price in the cycle number count 芎 242 t The same daily machine and the cycle instruction in the cycle number counter 242 * Not * / 〇 If the phase is 247, a low energy will be generated at its output If the taste is wrong, the comparator keeps the output signal at a high level. Then, if the output signal W is output, the buffer control logic circuit 25 is used to generate a buffer control signal for the one-byte enable signal BE #. The circuit 25 of order, command, and editing will enable the data and bytes after the first control cycle BE3 is latched, and enable the data and bytes = 〇) = between the data and open. Then, in the following other cycles (the cycle is wide, and the door is closed, the operation switch or the switch analog signal is received from 223) j = 'Whenever the data and the byte enable signal buffer ^ are opened, the door is opened ^; Win. , That is, page 13 575843

Requires bus master control signal (REQ #) generating logic circuit 26 to generate a bus master control request signal during a debug cycle

Master-REQ # (Bus Master ’s Request Signal) to the remote master station 3. At cycle 0, the circuit will pull the bus master control request signal Master-REQ # low to a low state, and when the comparator 247 outputs a low state comparison result signal CMP (ie, the number of switch presses and the latch When the number of cycles is the same and the number of cycles is not 0), the Master-REQ # signal is pulled high to a high energy level. The heart-end master device ready signal (IRDY #) generating logic circuit 27 can generate a debugging event IRDY # signal (MASTER-IRDY #) during the bus master cycle (Bus Master Cycle). When the bus is in idle state (ie, when FRAME # and IRDY # are both high) and AGNT # is low, the output of the Master-REQ # is pulled low to a low state, and when comparing = = In the low state, the output of Master-REQ # can be pulled up to a high level. The notification captures the debug information signal (MASTER — 0c #) to generate a circuit to receive the MASTER — IRDY #, and after the buffer control logic circuit “^^ buffer control signal” can generate a notification j M — —OC # To the remote console 3, used to inform the remote; = wrong to obtain the PCI bus cycle data in the device 2. Except Figure 3 shows the address and command latch control and command display unit 23 in Figure 2 1. Buffer A step-by-step logic circuit diagram of the circuit connection between the device control logic circuit 25. It shows the address and the command latch 212 includes several data latches 〇〜 资 'clock of the latch ™ is connected to the address =

Page 14 575843 V. Description of the invention (12) The round 2 and 1 of the road ψ and the command buffer cry t 2. The Ξ! 1 signal A—LATCH0 ~ A—LATCHn. The address control terminal 0C # system also includes several buffers 0 to buffer η, which turns out to cry 仏 ', and the 4r fast output control transmission nrn # η bucket produced by the buffer control logic circuit 25 The generated buffer is then controlled by 5 / η #, and the wheels of each buffer are reconnected to the address and command display unit 231. Output, circuit 22 = :: data in Fig. F and the byte enable signal latch control circuit logic logic = signal display unit 232, buffer control __ Further circuit diagram of the circuit connection. Its display time is 0 ί 11! E ^ ^ ^ 2 2 t ^ ^ tt ^ t ^ Received: r 'The clock of each data latch is connected to the signal lock control logic of the frame and the enable group respectively. The yoke control signal D —LATCH0 ~ D_LATCHn by the circuit 221. ::, punch_ also includes several buffers. 'Ease 2: 2: 0C # is controlled by the output control signal OCO # ~ 0cn # generated by the buffer control logic circuit, respectively. The rotation of each buffer is then connected to the data and the byte enable signal. Display unit 2 3 2. FIG. 5 is a schematic diagram showing a system connection between the remote main console 3 and the Pei device 30 of the debugging information collecting system of the present invention. The remote main console 3 may adopt a typical computer architecture, which includes a central processing unit 31, a memory 32, a debug chapter buffer 321, a PCI bridge 33, and a PC: [device 34, pci / ISA bridge Heart 3 5, ISA device 36. The central processing unit 31 and the memory 32 are connected to the system bus 3 7 1. The system bus 3 7 1 is connected to a PC I bus 3 7 2 through the pc I bridge 3 3. Various kinds of PCI devices 34 can be connected to the PCI bus 3 72. The PCI bus 372 is connected to an ISA bus 575843 through the PCI / ISA bridge 35. 5. Description of the invention (13) Row 3 7 3. Various I S A devices 36 can be connected to the I S A bus 3 7 3. The debug message buffer 3 2 1 is used to store all the debug related information of each bus cycle that has been collected. The debugging information collecting device 30 is a PCI bus 371 connected to the remote console 3, and is connected to the single-step interrupt debugging device 2 through a connector 300 and a signal connection line 4. FIG. 6 is a circuit block diagram of the debugging information collecting device 30 in FIG. 5, which mainly includes an interrupt request signal generating circuit 301, an input / output address buffer 302 (1/0 Address Buffer), and an input. A data round buffer 303 (1/0 Data Buffer), an input / output control signal buffer 304 (1/0 Control Signal Buffer), and a control logic circuit generating circuit 305. The control logic circuit generating circuit 3 0 5 is connected to the PC I bus 3 72 via signal lines such as PCICLK, FRAME #, R = #, TRDY #, DEVSEL #, etc., and can generate a cancel interrupt request signal INT_DST to the interrupt request. The signal is generated, the path is 1, and a control signal is read to read 0-c0ntr0l, the material is read RD —DATA, the one-bit read RD — ADDRESS to the input / output buffer 30 2 , Input / output data buffer 303, and input / output digitized buffer 304. $ 7 shows the timing buffers of the related signals when the single-step interrupt debugging device, the computer to be tested, and the graphics console execute the single-step interrupt debugging device according to the present invention. After the debug device has gone through two PCI bus cycles, ΐ / working power is taken as an example). Hyun at the same time with the aforementioned circuit diagram

Page 16 575843 V. Description of the invention (14) The control flow of the explanation is explained later. Period of Ψ Ψ 中断 Interrupt debugging device 2 in the PCI bus week 1 to be viewed 1 Λ ΛΙ ^ ^ s # ^ ^ # req # ^ ^ ^ ^^ ^ ^ ^ /: Test computer 1 handed over the subsequent bus_, -Computer 1 generation 1 bus arbiter (urblter) responds to the sink ί :: Signal GNT # Before the signal is acknowledged, the single-step interrupt debugging device 2 2ΐ ί The address of the bus cycle ⑽ ... the number of V periods for data and data: 2 = wide) and other signal states are locked, and the benefit is 242 5 The number of times the bus cycle has gone through (increased by 1; ° wide r: m bus arbiter responds to °) After the signal, the single-step interruption & quot After the end of the last bus cycle experienced, #: a # / 亚 maintain it at a low potential. At this time, " 7 'on the PCI bus and single-step interrupt debugging device 2 will enable MASTER_OC # 信 kii signal is transmitted to the remote control console 3's debugging information ghost collection device 3 0 through the signal connection line 4. * "Dangsui end console 3's debugging information collection device 30 detects the single step I = After the MASTER-〇c # signal sent by the debug device 2, the debug message is searched, and it is set to 3 through the interrupt request signal generating circuit 3 〇 ^ triggers a hardware Broken print request kINTA # to the remote console 3iPCI bus 371 to request the central processing unit 3 of the remote and centrally controlled σ 3 to process the interrupt request. The interrupt is executed by the interrupt program software The debugging information collection device 3 will cause the central processing unit 31 to issue a series of input / output (1/0) read and memory write (Mem〇ry Write) instructions, and collect the device 3 through the debugging information. of

Page 17 575843 V. Description of the invention (15) Control logic circuit generating circuit 3 0 5 generates control signals to read RD —CONTROL, data are taken RD —DATA, and address reads rd_ADDRESS to separately input / output address Buffer 3 〇2, input / output data buffer 3 0 3, and input / output control signal buffer 3 04 output gates are opened one by one to make the debug messages sent by the single-step interrupt debugging device 2 one by one It is sent to the central processing unit 31 via the PCI bus 371 and written into the debug message buffer 3 2 1 of the memory 32.

After the debug messages have been written into the debug message buffer 3 2 1, the interrupt processing program will cause the control logic circuit of the debug message collecting device 30 to generate a circuit 3 0 5 to send a cancel interrupt request signal ^ Ding Yi! ^ D, to notify the interrupt request 4 Lu No. generating circuit 3 0 1 to cancel the interrupt request, the control logic circuit generates circuit 3 0 5 and generates a switch analog signal sw_EMULATE, and this signal is sent back to the single-step interrupt via the signal connection line 4 Debugging device 2. Since the switch analog signal SW_EMULATE is actually equivalent to the switching of the switch, the one-step interrupt debugging device 2's switching times counter 246 will automatically count up once it detects the falling edge of the SW__EMULATE signal.

At this time, if the cycle number counter 243 in Figure 2 is not equal to the count value of the number of closed times 2 4 6, the single-step interrupt debugging device 2 will again enable the MASTER — 0C # signal to notify the debugging message. The collecting device 30 continues to capture the debugging information of the remaining bus cycle that has been locked by the single-step interrupt debugging device 2. The MASTER — 0C # signal can be described by the following representative formula: MASTER_〇C #: i :: (〇CO # & OCl # &, e & 〇Cn #) + Mast6r IRDY # where OCO # 、 〇Cl # 、 〇〇Cn # represents single-step interruption and debugging: Put on the output control signals of each buffer, and MASTER_IRDY # represents a single step

V. Description of the invention (16) stands for and between, '+' stands for the IRDY # signal or brake generated by the debug device. Zhao < I Early Step Interruption Debugging Device 2 The cycle count count 242 and the switch count counter 246 are pretty good. The main U4Z and switch-personal debugging information have been collected. σσ, the enabled status of the locked bus weekly exhaustion # and IRDY # signals, I will be interrupted and debugged as soon as possible ^ will end the detection of computer 1, resume normal PC industrial exchange, and return control of \ Give it to MASTERJEQ #, MASTER IRDY #. And by constructing each subsequent PGI;! In the case of changing from, the memory buffer of the automatic console. The remote / ^ record is stored in the remote bank, and is stored in the data storage device via the U port software program in the memory buffer (all the debugging-related information from / ^ $ to 6), which can be analyzed and counted. (Ii) Take the industrial utilization value of the degree provided by the present invention as further error correction. However, the above method and device for debugging and debugging does have a highly preferred embodiment description. Any description of the embodiments described in this section is only for the description of the embodiments of the present invention, and those skilled in the art should be able to follow other aspects of the present invention. Various improvements and changes made in the embodiments of the present invention. However, these changes in accordance with the spirit of the invention and the following ^ f are still within the scope of the present invention. Brief description of the drawing (1) Brief description of the round form: Fig. 1 shows a battery to be inspected

And the remote console. "Self-invented single-step application of the age of the invention. Figure II is a schematic diagram showing the system connection of the invention's single-two. * Misfit J Figure III :; display position and hit order removal = control set : Electricity ::: factory, further logic electricity :: Control logic circuits are shown in Figure 4 series. The second circuit is shown in Figure 4. The circuit and data and byte enable signals are used to pick up and lock the control logic circuits. The display system and the buffer control system are shown in the fifth series. Further schematic circuit diagrams of the present invention are shown. The schematic diagram of the system connection; the system and the debugging information are collected. Figure six series are shown in figure five. Figure seven series are shown in the present invention: Collect the block diagram of the circuit of the device; when performing single-step interrupt debugging, each of the == Figure 8 Ming latches and P in the single-step interrupt debugging device: the timing relationship between the number k and the MASTERJC # and SW —EMULATE signals Fig. 2) Description of drawing number: I Computer to be tested II Central processing unit 12 Memory 13 PCI bridge 575843 Brief description of the diagram 14 PCI device 15 PCI / ISA bridge 16 ISA device 171 System bus 172 PCI bus 173 ISA Bus 2 single step interruption Device 21 address and command latch control circuit 211 address and command latch control logic circuit 212 address and command latch register 213 address and command buffer 22 data and byte enable signal latch control circuit 221 Data and byte enable signal latch control logic circuit 222 Data and byte enable signal latch register 223 Data and byte enable signal buffer 23 Display device 2 31 Address and command display unit 2 3 2 Data and byte enable signal display unit 24 Count control circuit 241 Counter reset circuit 242 Cycle number counter 243 Cycle number decoder 244 Operation switch 245 Bounce circuit

Page 575 843

246 247 Switch times counter comparator 25 26 27 28 29 Buffer, control logic circuit f 5 ^ The current control signal (REQ #) of the busbar generates a logic circuit only :, the ready signal (IRDY #) generates the logic circuit 22 Take the debug message signal (MASTER_OC #) to generate the circuit connector 1 3 Remote master console 30 Debug message collection device 3 0 0 Connector 3 0 _ Seek signal generation circuit 3 0 2 Input / round out address buffer Device 3 0 3 input / rounder, stand-alone, flat-panel output buffer 3 0 4 input / rounder, such as r-zhuang 丨 α out & system k buffer 305 control logic circuit generating circuit 31 central processing unit 32 Memory 3 21 Debug message buffer 3 3 PCI bridge 34 PCI device 35 PCI / ISA bridge 36 ISA device 3 71 System bus 372 PCI bus

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Page 23

Claims (1)

575843 575843 6. Scope of patent application If the count values of the cycle counter and the switch counter are equal, ^ step interrupts the acquisition of the end signal of the debugging device and returns the bus control to the computer to be tested. 2. The bus cycle of the computer system as described in the item of the scope of the patent application, step-by-step automatic interruption of debugging information, where the bus is the% bus. … 3. The method for automatically collecting the bus cycle interruption and debugging information of the computer system as described in item 〖Scope of the patent application, further including the single-step T-loading: capture, the cycle of the computer bus to be tested :: : The steps for displaying information on a display device separately. The next day's newsletter 4 · If the first step of the patent application scope is interrupted, the debugging information will be automatically searched ^ The bus cycle of the brain system is set to the detected power ^ ^, where the single-step interrupt debugging includes The bus cycle address 1 and the bus cycle's debugging related messages, lean materials, commands, etc. ~ 5. If the patent application Fangu Item # = Automatic debugging information \ The bus cycle of the computer system described above is placed in the method of obtaining the main computer of the computer to be tested, where the single-step interrupt debugging includes the following: Steps: 彳 萑, and retrieve debugging-related information ^ to the bus you want to view " set a request to the bus master; occasionally, single-step interruption debugging equipment verification number REQ # to the computer to be tested 575843 --------- 6. Scope of patent application _________ When the computer to be tested responds to the interruption step and the debugging device recognizes the arbitration permission signal signal, the signal status of the single material, command, etc. Second, = of each bus cycle The address and data will be fully locked when the computer to be tested is returned. Single-step interrupt debugging device Right = After the non-arbitration permission signal signal is recognized, after that, the action on the bus gg is taken after the completion of a bus cycle. Error device pause; MASTER — OC #. This §11 tells you to retrieve the debugging information signal. 6. If the patent application scope is in step # 1, the debugging information is automatically collected. The bus cycle of the computer system is set to capture the single-step interrupt debugging device. The error message collection event is processed through interruption, which includes the following two = when debugging related messages: The error message collection device generates one or two 'buses to control A ^ ^ to the remote master Control request; the central processing unit requires debugging; flfl The information collection device is controlled by the staking; ^ Tiger reading, data reading 2 i address 2 channels to generate input / output address buffers, rounds, and temples, respectively, With the output of the minute / output control signal buffer, r / one-by-one lean gate buffer, and turn-in, the single-step interrupt debugging device is sent / opened; after the debugging messages have been received: Λ information is received one by one · The road sends a request to cancel the interrupt; = The control logic circuit generates a "tiger" to notify the release of the interrupt = Electricity Page 26 6. Patent application scope; ㈣ Debugging: Γ moved two to take a single step to debug in Sri Lanka The device is locked; "container" includes the debug phase Writes post distal end; 2, error message buffer. Deletion of the self-feel in the mouth • ^ 2 #The electric step interruption debugging message described in item 7 of the patent scope is automatically ¥ 隼 square, 1 、, and 胤. Master and system "in the material storage device" as a step-by-step debugging: 9. A computer system device, used to search the cycle of the cycle to debug a single-step interruption except the master control that can be inspected, and capture One informs the fetching error device that includes a cycle count, a bus count, a pass count, a comparator, and a bus that uses the wrong set of relevant information to be checked. The bus fetches the bus debugging information including : Counter for the number of cycles; counter for comparing the single-step interruption debugging information of the cycle, automatic detection and detection of the computer during the debugging cycle = 'The device includes: connected to the computer to be tested The bus, in the mid-term, obtains the debugging related information of the bus of the computer to be tested > cycle, and can generate the signal MASTER — oc #, the single-step interruption has been recorded, and the computer to be tested has no error during the debugging cycle. Record the number of customs clearance; Off cycle counter 575843 A remote console, including a connection cable connected to the single-step interruption to receive the single-step interruption debugging equipment MASTER — 0C # signal, and the single set of t The signal transmission and debugging information collecting device further includes a control logic generating circuit, which can produce a single-step interrupt debugging device; an interrupt request signal generating circuit, which sends the MASTER_OC # signal number sent to the remote console; at least one A buffer for temporarily storing the debugging-related information; when the debugging-related information sent by the MASTERJC # error device sent by the error-checking device of the remote console has been received, the The Guanla K number is sent back to the single-step interruption except for the analog signal according to §Hai switch. From the open time, when the cycle number counter and the closed car parent are not equal, the MASTER — 0C # signal can be notified to the step. The central office debugging device continues to capture the error message collection device. Through the signal error device, the relevant debugging information sent by the signal connection line is set and the relevant controls required to interrupt the debugging device and the debugging information are interrupted. The signal includes: generating a switch analog signal, and sending the analog signal to receive the single-step interrupt debugging device, and generating an interrupt request letter based on the set device sent by the single-step interrupt debugging device to receive the order After the step-by-step interruption signal, the single-step interruption and removal of interest is captured one by one, and an error opening device is generated in the debugging related debugging information collection device. The single-step interruption debugging device closes the counter and counts up the count of the number of closes. The value is compared, and the single-step interruption of the debugging device causes the debugging message collection device to continue to be locked by the remaining bus cycle of the single latch. Page 28 575843 VI. Patent application scope _A :: error message; and when the number of cycles counts; when the ten values are equal, the bus control of the bus counter of the single-step interruption debugging counter is returned to the computer to be tested Signal acquisition, and I 〇 · As described in item 9 of the scope of the patent application for automatic step interrupt debugging information collection device, I =, the first bus cycle single bus. "A. The bus is PCI II. • The device for automatically collecting error messages as described in item 9 of the scope of patent application, where ^ = first = the bus cycle is a single device connected to the PC I to be tested. Bus, 忒 one-step interruption debugging device to collect Pei Zhi is connected to the remote console and the debugging information self-breaking and debugging device and the automatic debugging of the debugging information ^ busbar, single step medium Connect the cables. The time is between 1 and 2 · The computer step interruption and debugging information automatic collection device described in item 9 of the scope of the patent application, the single cycle of the complex i I includes: The address and command latch control circuit can be used in the wrong bus cycle and command latch register of the computer to be tested; The tuple enable signal latching control bus bus cycle can lock the data of the computer to be tested to a data and byte enable signal enable signal I% lock register in the case of debugging. Page 29 /, 'Patent application scope a counting control circuit,-^ cycle number counter week ::, week: numerator, used to decode to the address and order the decoded signal depends on latch control Circuit; industrial circuit and data and byte enable signal pin: to generate a buffer control signal to: No. lock control circuit and data and byte enable; device and-data and bit two stop and command pin Lock-in-requirement right signal (REQ #) generates logic electricity: used to produce one = clothing exchange ~ row master control signal (REQ #); seat period t ^ = provision of female signal generation logic circuit, can be on the bus Generated during the master # is j period-master, prepare the signal IRDY #; L-row of the master control cycle to get the debug message signal generation circuit, to use the "" MASTER_0C # to the remote console's debug message = 13 .. Bus cycle of the computer system as described in item 12 of the scope of patent application: v Automatic interruption collection device for interrupted debugging information, where the address and command, the address in the control circuit and the command latch register It is a first-in-first-out register, and the data and the byte enable signal latch control circuit The secondary data and byte enable signal latch register is also a first-in-first-out register. Cycle 1 4 · The bus of the computer system as described in item 12 of the scope of patent application 1 Page 30 575843 VI. Patent application scope Single step interrupt debugging information automatic collection device, wherein the single step interrupt debugging device further includes a display device for displaying the debugging captured by the single step interrupt debugging device Related information, the display device includes: a bit address and a command display unit, connected to the address and the command latch control circuit, and the command buffer, used to display the latched address of the cycle to be debugged And command status; a data and byte enable signal display unit, connected to the data and byte enable signal buffer in the data and byte enable signal latch control circuit, for displaying the error to be debugged Status of the latched data and byte enable signal of the cycle. 1 5. The automatic collection device for single-step interruption and debugging information of the bus cycle of the computer system as described in item 12 of the scope of the patent application, wherein the counting control circuit includes a counter reset circuit for interrupting the single-stepping interruption. When the comparator output of the wrong device is low, the count values used to reset the cycle counter and the switch counter are zero. Page 31