TW575756B - Thin film transistor matrix with repairable bus line and method of manufacturing the same - Google Patents

Description

J /) / 56 A7 B7 V. Description of the invention (1

Ben Jing, the method of manufacturing thin-film transistor matrix-a kind of repairable separation or jealousy, especially "" matrix and its manufacturing method. In other words, the film is a thin film transistor (TFT) matrix type liquid crystal personal computer and TV wall. There are two types of coffee to be used on the knee: the gate is located at the bottom of the interlayer electrode, and the gate is located at the activation layer. A top gate type with an insulating film sandwiched between the semiconductor layers. The source and / or electrodes are usually formed on the semiconductor layer on both sides of the gate, and the source and the > and a metal layer with a very high doping concentration and a contact semiconductor layer are stacked. Source / non-polar-connected to the data bus, and the other-a pixel electrode. In this configuration, the source / drain connected to the data bus is called the sum 'and the source connected to the pixel electrode, and the drain is called the source. The data bus is called the drain bus. The TFT-matrix liquid crystal display panel has a drain bus line and a gate bus line formed on the substrate of the moon, the yin, and the yin to cross each other. The drain bus is connected to the drain of the TFT, and the gate bus is connected to its gate. The suspension, and the pole busbar and the drain are composed of the same conductive layer. Gate busbars and gates usually consist of the same conductive layer. The glass substrate used for the liquid crystal panel has a large area, so that foreign matter will inevitably fall on it during the manufacturing process. If there is a foreign substance on the glass substrate during the formation of the conductive layer, the conductive layer will not be directly deposited on the glass substrate, but on the foreign substance. When foreign matter is cleaned up, pinholes will form on the conductive layer. 4 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). 575756 A7 B7. 5. Description of the invention (2 10 15 20 The gate bus line or the non-polar bus line is about to be broken, then the LCD panel will have a wire failure. If pinholes exist on the source / drain electrode, the pixel electrode, or the thunder bus line, the thunder and pole may be differentiated. Pixel failures are formed. These failures, especially line failures ^ Liquid display panel is a fatal defect. As mentioned above, it is difficult to report foreign matter in the LCD panel manufacturing process to prevent foreign matter from forming a liquid crystal display panel. Fatal defect. Therefore, our time = provide-a kind of liquid crystal display panel structure and manufacturing method. The liquid crystal display panel has the ability to repair the faulty bus bar formed by the foreign matter falling on the broken glass substrate during the manufacturing of the liquid crystal display. The purpose of the invention is to provide a diaphragm-type transistor matrix capable of repairing fault sinks. Another object of the present invention is to provide a method of manufacturing repairable fault sinks. Method for streamlined thin-film transistor matrix. According to one aspect of the present invention, a thin-film transistor matrix can be provided, including: a plurality of thin-film transistors with an insulating base U㈣ type arranged on a base substrate, and each thin-film transistor A pixel electrode having an interrogation electrode, a source electrode, and a non-electrode electrode formed on the insulating substrate, and the electrode is connected to the source of each of the triode transistors; a plurality of interpolar electrodes are arranged in the column direction of the insulating substrate as a whole. Each bus bar is connected to the third bus line consisting of the first gold layer and the first semiconductor layer below; the majority of the non-polar bus bars arranged in the direction of the insulating base, each bus bar A digital film consisting of a second metal layer and a second semiconductor layer below which is connected to the drain electrode, is a physical paper, a paper ruler, and a wealth meter. (A) Specification A5 Specification (3 A7

Second stack. i According to the two-body matrix method of the present invention, the γ-solid viewpoint provides a method for manufacturing a thin-film transistor. The μ crystal transistor matrix has a plurality of post-secondary “I” early-types arranged in a matrix type on an insulating substrate. Pole and non-pole, the electricity said F fish ^ Yue Yue body 'Each transistor has a pole, source

The pixel electrode Γ of the source electrode is connected to a plurality of thin film transistor current drain lines, and a plurality of gate sinks arranged as a whole in the row direction L !. The plurality of drain bus lines configured as a whole include the following steps: forming a first semiconductor layer on the insulating substrate, forming a first metal layer on the conductor layer, and patterning the first metal layer and a semiconductor layer to form a thin film The closed electrode and the conductive layer of the transistor are located under the metal layer. Even if the pinhole is formed in the metal layer, the semiconductor layer is still located under the pinhole. A metal layer may be selectively formed on the semiconductor layer. Even if a crack or interruption occurs in the patterned metal layer, the cracked portion can be repaired. > By repairing faulty busbars, the process yield of the thin film matrix can be increased. This also prevents a fatal failure for the liquid crystal display device. Figures 1A to 1D are equivalent circuit diagrams of the thin-film transistor matrix of the present invention and cross-sectional views of busbar crossing regions. Figures 2A to 2F show the main processes of a liquid crystal display panel using a bottom gate TF butyl body in cross-sectional views. FIG. 3 is a plan view of the TFT substrate after the process of FIG. 2D. Figures 4A to 4D show the process of repairing faults in the metal layer in cross-sections. 0 6 This paper size applies to Chinese National Standard (CNS) A4 specifications (2) 0X297 mm. 575756 A7 B7 V. Description of the invention (4 Figures 5A to 5IJ) Figures show the 5th and 5th early flows in the repaired metal layer in cross-sections Figures 6A to 6D show the flow of faults in the repaired metal layer in cross-section. 15 The following describes the invention with reference to the drawings Of an embodiment. Figures 1A and 1B are schematic and equivalent circuit diagrams of the thin film transistor matrix of the present invention, and Figures 1C and 1C are cross-sectional views of a gate busbar and a drain busbar. As shown in FIG. 1A, the thin film transistor array has a plurality of gate bus lines GL1, GL2, GL3, ..., and a plurality of drain bus lines 1 ^ 1, DL2, DL3, ..., which are each other. Crossed and usually formed on a transparent substrate. The TFT transistor is formed at each intersection of the gate bus line GL and the non-polar bus line DL. The gate of the TFT is connected to the gate bus line GL, and the drain electrode is connected to the drain bus line DL. The source of the TFT is connected to the pixel electrode PX and one electrode of the storage capacitor SC formed by the pixel electrode PX. The other electrode of the storage capacitor sc is connected to the storage capacitor bus bars cai, CA2 parallel to the non-polar bus bar DL (please read the precautions on the back before filling this page)

20 The storage capacitor bus line CA is used to connect the other electrode of the storage capacitor SC to a power source having a predetermined voltage, and is preferably parallel to the drain bus line DL or the gate bus line gl. Fig. 1B shows a structure in which the storage capacitor bus bars CB1, CB2, ... are parallel to the gate bus bars GL1, GL2, .... The other parts in the figure are the same as those in Figure 1A. This paper size applies the Chinese National Standard (CNS) M specification (2) 0 > < 297 mm) 7 575756 A7 B7 V. Description of the invention (5 In any of the structures described, the gate busbar GL and The interlayer of the TFT is formed by the same conductive layer. The drain bus lines D1 and TFt are formed by the same conductive layer. The intersection area between the drain bus line DL and the gate bus line GL It is insulated by the gate insulation film. Figure 1C is a cross-sectional view of the parent fork area of the drain bus line of the bottom gate type thin film transistor / IL bus. For the bottom gate type thin film transistor, In other words, the gate and the gate busbar GL are first formed on the transparent insulating substrate 1 made of a glass substrate. 10 15 20 (Please read the precautions on the back before filling this page) In this example, ' The gate and gate bus lines GL are formed by a semiconductor layer 2 and a metal bus layer 3 with a high doping concentration. The gate insulating film 4 covers the gate bus lines GL with a back cover. The bulk layer 5 is formed on the gate insulating film 4, and the high impurity concentration contacts the semiconductor layer 8 and the metal sink The wiring layer 9 is formed on the semiconductor layer 5. The shape of the layers 5, 8, and 9 is the same as the source / drain and drain bus lines. In the channel region of the TFT, an insulating film is formed on the activated semiconductor layer 5 to produce Corrosion resistance, so the contact semiconductor layer 8 and the metal bus layer 9 will be removed, leaving only the activated semiconductor layer to form a channel. The semiconductor layer 2 in the gate bus line GL is not necessary to form a closed bus line. However, the formation of this semiconductor layer under the metal busbar layer 3 makes it possible to repair faults such as separation of the metal busbars of the gate busbars. The activated semiconductor layer 5 below the drain busbars DL is based on the following Figure 1D shows the structure of the cross-section area of the busbars of the top-type thin-film transistor. On the transparent insulating substrate! The contact with the semiconductor layer 8 and the gold paper size are subject to Chinese national standards ( OTS) A4 specifications (2) 〇X297 public dream) 575756

A7 B7 V. Description of Invention (6)

The bus bar layer 9 is superimposed and forms the shape of a bus bar. The stack that contacts the semiconductor layer and belongs to the busbar layer 9 provides the function of a non-polar busbar sinker. In the thin-film electrical region, a body layer such as Di Qing's activated semiconductor layer 5 is deposited under the contact semiconductor layer 8. A barrier layer is provided on the active semiconductor layer constituting the channel, and the busbar layer 9 and the contact semiconductor layer 8 above the insulating film are removed. Therefore, the active semiconductor layer passes through the gate insulating film and The gate formed on the samarium insulating film is opposite to the parent fork region. A semiconductor layer 2 and a metal busbar layer 3 with a high doping density are formed on the gate insulating film 4. The layers 2 and 3 constitute a gate busbar. Gate bus bar 0B is covered with an insulating protective film 13. Similar to FIG. 1C, the semiconductor layer 2 of 'gate bus bar_' is not necessary to form a gate bus line. However, the metal bus bar layer 3 Depositing the semiconductor layers 2 and 8 under 9 can make the faults such as detachment formed in the metal busbar layer 3 9 can be repaired by using the semiconductor layers 2 and 8. The bottom gate type thin film transistor in FIG. 1C Such an example is provided. Figures 2A to 2F show the process of the thin-film transistor matrix and the liquid crystal display panel using the thin-film transistor matrix in a cross-sectional view. As shown in Figure 2A, a transparent glass substrate is used. Insulating substrate} on Η-type impurity doped large "2 + -type silicon layer using plasma enhanced chemical vapor deposition (PE-CVD) to a thickness of approximately 50nm. The silicon layer 2 may be amorphous or polycrystalline. The following description uses an amorphous silicon layer. Yang 9 This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (2] × 297 Gongchu) 575756 A7 B7 V. Description of the invention (7 10 15 20… If a polycrystalline stone layer is used, an amorphous layer must be formed first Laser annealing transforms it into a polycrystalline silicon layer. A metal layer can be selectively formed on the silicon layer 2. The thickness of the stone layer 2 can be as expected. In On the surface of Shixi layer 2, the gate is made of Cr. The thickness of the electrode metal layer can be spray-coated. In addition to Cr, the material of the electrode metal layer 3 is: Ti 'Mo, Ta or its alloy. The semiconductor layer 2 and the gate metal layer (metal m streamline layer) 3 are difficult to be manufactured continuously using the same-manufacturing system. Therefore, these two processes must be completed in two processes by using the manufacturing system, In addition, a light-blocking layer is applied on the gate metal layer 3 and exposed and developed to form a blocking pattern PR1. The shape of the blocking pattern pR1 defines a gate, an inter-electrode busbar, and a storage capacitor busbar. Using the blocking pattern pRi as a photomask, the gate metal layer 3 and the semiconductor 2 will be etched to leave the patterned semiconductor layer 2a and the patterned gate metal layer 3a. After the etching, the barrier pattern PR! Is removed. After the barrier pattern PR1 is removed, the patterned busbar layer is removed. Clean. S As shown in FIG. 2B, the activated semiconductor layer 5 is formed with the channel protection film 6 & pE_C VD method, and covers the patterned gate metal layer 3a and the semiconductor layer 2a. It is composed of a SiN layer having a thickness of about 400 nm, the active semiconductor layer 5 is composed of an amorphous silicon (a_Si) layer having a thickness of approximately 5 nm, and the channel protection layer 6 is composed of a SiN layer having a thickness of approximately 20 nm. The film is coated on the channel protection film 6. After exposure and development, the paper size is adapted to the Chinese National Standard (CNS) A4 specification (2) 〇 > < 297 Gongchu) 10 (Please read the precautions on the back before filling (This page)

575756 A7 B7 V. Description of the invention (8 into a barrier pattern PR2. The barrier pattern pR2 is deposited on the area where the thin crystal # is formed. Using the barrier pattern PR2 as a photomask, the channel protection film 6 can be engraved with money. For example, Dry etching can be done with 0 2 gas (flow rate range of 170 to 230 s_, such as 20 sccmmsF6 gas (flow rate of 175 to 2 仏 _, such as 200 SCCm), provided that the remaining system is maintained at about 8 Pa. The pressure and high-frequency power of 600W are used. After the dry etching, the channel protective film 6a (shown in Figure 2C) exists only in the channel area. After the dry sealing, the barrier pattern PR2 is removed and the substrate surface is cleaned. 10 15 20 Figure 2D is a cross-sectional view of a thin-film transistor that has undergone the aforementioned process. A gate electrode G (2a, 3 is a small and patterned activated semiconductor layer 5a is formed on the gate insulating film 4 on a transparent insulating substrate. A channel protective film is deposited. In the central region of the activated semiconductor layer 5a, the patterned contact semiconductor layer 8 &, the source metal layer 9a and the drain metal layer 9b are located on both sides and edges of the channel protection film. Fig. 3 is a thin film of Fig. 2D Fabric of transistor matrix The plan view of the bureau '. The gate bus line GL and the storage capacitor bus line CB are arranged in the horizontal direction in FIG. 3, and the drain bus line DL extending in the vertical direction in FIG. 3 is separated by a gate insulating film. It is formed above the gate bus line 〇B and the storage capacitor bus line CB. The thin film transistor TFT and the channel protection film 6 are exposed in the central area, and the source metal layer such as the drain metal layer and the drain metal layer are located in the middle area. On both sides, the cross-sectional views of Figures 2A to 2F are taken again along line segment 1 of Figure 3. As shown in Figure 2E, an insulating protective film of a thickness of about 300 nnu〇SiN is formed on a substrate with PE-CVD method. Membrane transistor gate busbar certificate This paper size is applicable to China National Standard (CNS) A4 specification (210X297 Gongchu) 11 575756 A7

575756 A7 V. Description of the invention (10)-McCaw's 3-The case where the gate bus GL is not connected to the drain bus DL due to foreign matter mixed into the bus will be explained, and 4A to 4D will be described with reference to cross-sectional views taken along line segments γ_γ and z_z in FIG. 3. 5 Figures 4A to 4D are cross-sections of the gate busbars taken along the line segment γ_γ and cross-sections of non-polar busbars taken out of the line segment Z-Z. Fig. 4A shows the case where the gate electrode caused by the foreign matter falling on the busbar is disconnected from the metal layer 3a of the busbar and the metal layer 3a of the drain busbar is not connected. The metal layer 3a is covered with a gate insulating film and an insulating protective film. 10. The metal layer 9b of the drain bus bar is covered with an insulating protection film 13. In these bus lines, semiconductor layers 仏 and 仏 of high doping concentration are formed under the metal layers 3a and 9b. If the metal layer is cut off, the resistance of the financial confluence busbar will be greatly increased. Therefore, the disconnection of the busbar is electrically easy to be measured. The TFT detector can identify the address of each bus line. An optical camera mounted on the D15 detector can optically observe the surface of the substrate to determine the discontinuous position. After the fault location is confirmed, the fault will be repaired. As shown in FIG. 4B, the barrier layer is coated on the surface of the substrate, and is subjected to exposure and development to form a barrier pattern PR4. The barrier pattern PR4 has an opening in the inspection corresponding to each of the failure regions 20. With the barrier pattern pR4 as a bare grass, the insulating protective film 13 and the gate insulating film 4 exposed in the opening will be etched. For example, this etching process can be performed in a dry etching system, with a yield of: cc_02 gas and a tritium gas with a flow rate of café gas in a two-chamber chamber with a high-frequency power of about 8Pa and 600W for two minutes. Just fine. This paper scale applies Chinese national standard (〇 / s) A4 regulation (2) 〇 > < 297 Gongchu) 575756 A7 _______ _B7 V. Description of the invention (11) Figure 4C shows the barrier pattern pR4 and the substrate are dry. Cleaned up after etching. In the fault area, the pole insulation film 4 and the upper insulating protection film Η are removed and the fault metal layer 仏 and% are exposed. The exposed TFT substrate is sent to a tungsten selective CVD system. 5 As shown in Fig. 41), W is selectively generated on the surface of the silicon layer having the disadvantage of exposure. For example, the WCVD generation conditions are substrate temperature of 200 ° C, WF6 gas flow rate of 5 sccm, siH gas flow rate of 2% ^, H2 gas flow rate of 80 sccm, and CVI) system pressure of 0.002 Torr. Under these conditions, w is selectively formed on the surface of the silicon layer instead of 10 on the surface of the insulating layer and the metal layer. In this way, the rupture area of the gate bus line has the W layer 18a, and the rupture area of the drain bus line has the W layer 18b. The broken gate and drain buses are thus repaired. In the above description, even if the faults of the drain and gate busbars are detected and repaired after the structural element of TF-butylsulfonium is formed, these faults can be repaired in the middle stage of the manufacturing process. Figures 5A to 5D show the process of detecting and repairing the fault after the gate bus (including the gate and capacitor electrodes) is formed. The cross-sectional views of persons 5 to 5D are taken along the line γ-γ of FIG. 3. As shown in FIG. 5A, the n + -type bu & layer 2 is formed on the glass substrate 1, and after 20, the surface of the substrate is cleaned. After the cleaning process, the substrate may be attached to the substrate during the process of moving it into the spray reduction coating system. FIG. 5B shows a gate metal layer formed on the surface of the n + -type sense layer 2 with a foreign substance 2 0 attached thereto. In the region where the foreign object 20 exists, the gate metal layer 3 is deposited on the foreign object 20 instead of the 0-type layer 2. Therefore, the pinholes are formed on the paper in accordance with the Chinese National Standard (⑽) A4 specification (2.j × X297mm) 14 (Please read the precautions on the back before filling this page), \ > Sip 575756 A7

This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 15 575756 A7 ____B7_ V. Description of the invention (13)-Surface. When the source metal layer 9 is formed, the metal layer is deposited on the foreign objects 22 and 25 in the region where the foreign object exists, instead of being deposited on the contact surface of the semiconductor layer 8. Pinholes 23 and 26 are thus created on the source / drain metal layer 9 5. When the substrate is cleaned after the source / electrode metal layer 9 is formed, the foreign matter 22 and 25 are removed and the pinholes are exposed. Figure 6C shows the pinholes 23 and 26 appearing after the substrate is cleaned. The photoresist layer is coated on the surface of the substrate and subjected to exposure and development processes to form a barrier pattern. The above photoresist pattern is a photomask, and the source / drain metal layer 9, the contact 10 semiconductor layer 8 and the activated semiconductor layer 5 are etched. As shown in FIG. 6D, after etching and removing the barrier pattern and cleaning the surface of the substrate, the source metal layer 9a, the contact semiconductor layer, and the activated semiconductor layer 5a are all patterned in the TFT region. The source metal layer% has Pinhole 23, and the drain busbar has pinhole 26. The busbar layer is inspected at this time, 15 and it is assumed here that the unconnected drain busbar is detected. After that, the TFT substrate is sent to W Selective CVD system to selectively generate W. Since W is selectively generated on the surface of the exposed semiconductor layer, pinholes 23 and 26 are embedded with W layers 27 and 28. As shown in Figure 6E, after fault repair, The surface of the tinted substrate is covered with an insulating layer 20. The pixel electrode contact hole is formed through the layer 13, and an IT0 film is formed, patterned by photolithography, and then etched to form an ιτ〇 electrode 14. Afterwards, the orientation film is formed on the surface of the kTFT substrate and subjected to orientation treatment to form a complete TFT substrate. Although the above description is based on the TFT substrate of the bottom gate type, familiar with this technology paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 ] 〇χ297 公 楚) 16 tr (please Read the notes on the back and fill in this page) 575756 kl ____ B7__ V. Description of the invention (14) · The person skilled in the art should _ 'Top gate type TFT substrate can be repaired in the same way. In the above description, it is selected by w In addition to W, the metals that can be selectively generated include, Ta, Ti 5, Cr, Ni, Cu, A; l. These metals can replace w to repair the fault. In a reflective LCD, the substrate may not be transparent, and an insulating substrate may be used. The invention has been described through preferred embodiments. The invention is not limited to the foregoing embodiments. For those skilled in the art, the invention Various corrections, improvements, and combinations can be applied. Component reference table 25 9 ... metal bus layer 9a ... source metal layer 9b ... drain metal layer 13 ... insulation protection film 14 ... pixel electrode 30 15 ... orientation film Tungsten layer 18b ... Mu layer 鹉 8c ... Crane layer 20 ... Foreign matter 35 21 ... Pinhole 22 ... Foreign matter The size of this paper applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the back first · Attention Refill this page} 1 ... Insulating substrate 2 ... Semiconductor layer 15 2a ... Gate 3 a ... Gate 3 ... Metal busbar layer 4 ... Gate insulating film 5 ... Activated semiconductor layer 20 5a ... Activated Semiconductor layer 6 ... channel protection layer 6a ... channel protection film 8 ... contact semiconductor layer 8a ... contact semiconductor layer-order 丨 Φ! 17 575756 A7 B7 V. Description of the invention (15) 2 3 ... Needle L t 25 ... Foreign matter 2 6 ... pinhole 27 ... tungsten layer 5 28 ... tungsten layer 51 ... insulating base 52 ... common electrode 53 ... black matrix 54 ... orientation film 10 55 ... color filter 6 0 ... liquid crystal layer --- ------—— · --------------------... Order ---------------- 0 (Please (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 18

Claims (1)

简 简 嶋 ㈣ 料 面 ㈣ 92.1G13 • A thin film transistor matrix with repairable busbars, which includes an insulating substrate; several thin film transistors are arranged on the insulating substrate in a matrix pattern of columns and rows, each The thin film transistor has a gate, a source, and a drain; a pixel electrode formed on the insulating substrate and connected to the sources of the thin film transistors; a plurality of gate bus lines along the insulation The substrate is arranged in a column direction, and each bus line is connected to the gate and includes a substantially entire length of the gate bus line. The first metal layer and a first metal layer are arranged directly under a first metal layer. A first stack consisting of a semiconductor layer; and a plurality of drain busbars arranged along a row of the insulating substrate, each busbar being connected to the drain and including a busbar substantially along the drain The entire length of the wire is directly arranged under a second metal layer, and a second stack consisting of the second metal layer and a second semiconductor layer 2. The thin film transistor matrix as described in item i of the patent application scope, wherein Should never Substrate is a transparent insulating substrate. 3. The thin film transistor matrix according to item 1 of the scope of the patent application, wherein the gate includes the first stack same as the gate bus, and the source and the drain include and the drain The second stack has the same bus lines. A4 ^ T7 "0_X297 mm" applicable to this paper size 19 575756 A8 B8 C8 D8 15 20, patent application scope 4. The thin film transistor matrix as described in item 3 of the patent application, the first metal layer has a first Partial defect, the first one here: The third metal layer does not exist or is only partially present. Embedded… Partial defect 5. ^ Thin film transistor matrix described in item 3 of the patent application 'where the second : The metal layer has a second local defect 'here the second metal layer and the fourth metal layer. And the second local defect is buried in the 6 · the first metal of the thin film transistor matrix described in the patent application scope item 4 The layer is composed of a material selected from the group consisting of Cr, Ta, Mo, w, L and the alloy of the above materials. 7. The thin film transistor matrix as described in item 4 of the scope of patent application, The third metal layer is composed of a material selected from the group consisting of w, Mo, Ta, Ti, Cr, Ni ^: A1. 8. The thin film as described in item 5 of the scope of patent application Transistor matrix, pot-cut second metal layer is made from one to 0, ^ or one of the above materials A single layer composed of selected materials in the group consisting of alloys or made of a laminate including an A1 layer. 9. The thin-film electricity described in item 5 of the May patent application Crystal matrix, in which the fourth metal layer is composed of a material selected from the group consisting of W, Mo, Ta, Ti, Cr, I, and。 A1. 10. As item i of the scope of patent application The thin-film transistor matrix further includes a plurality of storage capacitor busbars, parallel to the gate busbars. The paper size is applicable to China National Standard (CNS) specifications (2) 0X297 Gongchu. Pinchen configuration / 、 The patent claims the storage capacitor under the two pixel electrodes and on the transparent insulating substrate, the storage: the wiring is composed of the first stack; and "two edge film, covering the storage capacitor bus lines and It is disposed under the pixel electrode on the transparent insulating substrate. The application of the thin film transistor matrix described in the item No.!, Which is more enveloping wire is suitable for "Bulldozer" Xiao Ding, the sink of the drain Below the one or two pixel electrodes of the power discharge and on the transparent insulating substrate, the storage wiring is composed of the second stack; and an insulating film covers the storage capacitor bus lines and is disposed on the transparent insulating substrate. Above the pixel electrode. 12 = The thin-film transistor matrix described in item 1 of the scope of the patent application, wherein the first and the first semiconductor layers are composed of Shi Xi. 13. A method for manufacturing a thin-film transistor matrix with repairable busbars, the thin-film transistor matrix having a plurality of thin-film transistors arranged in a matrix on an insulator, each thin-film transistor having a pole , A source, and a drain, the thin-film transistor matrix has a pixel electrode connected to the source of a thin-film transistor such as tritium, a plurality of gate busbars arranged along a column, and a plurality of rows along a row The drain busbars arranged in the overall direction include the following steps: forming a first semiconductor layer on the substrate, and forming a first metal layer on the first semiconductor layer; and A metal layer and the first semiconductor layer are patterned to form the gate and the gate bus of the thin film transistor, wherein 575756 A8 B8 * C8 " '----------- D8________ 6. Scope of patent application: A semiconductor layer is substantially directly disposed under the first metal layer along the entire length of the gate bus bar. 14. The method of fabricating a tritium film transistor matrix with repairable busbars as described in item 13 of the scope of the patent application, wherein the insulating substrate is a transparent insulating substrate. 1 5. The method for manufacturing a thin film transistor matrix with repairable busbars as described in item 3 of the patent claim, wherein the first semiconductor layer is a wonderful layer. 10 16. The method for manufacturing a thin-film transistor matrix with repairable busbars as described in claim 13 of the patent scope, further comprising the following steps: forming a second semiconductor layer on the insulating substrate; and Forming a second metal layer on the semiconductor layer; and patterning the second metal layer and the second semiconductor layer to form the drain and the drain bus line of the rhenium film transistor. 15 17. The method for manufacturing a thin-film transistor matrix with repairable busbars as described in item 13 of the Shenqiao patent scope, wherein the patterned first metal layer has a first defect, and the first metal layer here It does not exist or only partially exists, and the method further includes the step of selectively forming a third metal layer on the first semiconductor layer patterned and exposed by the first defect. 18. The method for manufacturing a thin film transistor matrix with repairable busbars as described in item (1) of the scope of patent application, wherein the patterned second metal layer has a second defect, where the second metal layer does not exist Or it only exists partially, and the method further includes the step of selectively patterning and exposing the second layer by the second defect 20 and the patent application scope. Said on the formation. One brother four metals 19 = method of manufacturing a transistor matrix with repairable bus bar film as described in item 16 of the scope of patent application, wherein the patterned first and-metal layers have defects' here should The related first or first-metal layer does not exist or only partially exists, and the method further includes forming a second insulating film on the patterned first and second metal layers, respectively. 10 Defects Removing the first and second insulating films in the region; removing the first and second insulating films in the region having the defects; and selectively exposing the defective region and the second semiconductor layer A third metal layer is grown. 15 20. The method for manufacturing a thin-film transistor matrix having repairable bus lines according to item 16 of the scope of the patent application, wherein the second semiconductor layer is a stone layer. 21 · —A method for manufacturing a thin-film transistor matrix with repairable bus lines, the thin-film transistor matrix having a plurality of thin-film transistors arranged in a column or row matrix pattern on an insulating substrate, each thin-film transistor having a A gate electrode, a source electrode, and a drain electrode, the thin film transistor matrix has a pixel electrode connected to the source electrodes of the thin film transistors, a plurality of gate busbars arranged along a column, and a plurality of The drain busbars arranged in one row direction, the method includes the following steps: 20 575756 AB c D 々 巳 am amam- main, one: forming a patterned first metal layer on an insulating substrate to form a pattern The closed wiring; j «the electrode forms a semiconductor layer on the insulating substrate; forms a second metal layer on the semiconductor layer; patterning a stack composed of the second metal layer and the semiconductor layer In order to form the drain electrodes and the drain bus lines, the patterned first metal layer has a defect, where the second metal layer does not exist or only partially exists; and ο is exposed to the defect Selectively growing a third metal layer on the semiconductor layer. 24 This paper size applies to China National Standard (CNS) A4 (2 10X297 mm)