TW563186B - Surface treatment method of low dielectric constant material - Google Patents
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563186 五、發明說明Ο) 發明領! 鍤极明係有關於半導體製程技術,且特別是有關於 佳的可信賴产,方法’其可提高崩潰電壓而有較 ^ 、度並且可降低介電常數。 技術背j; t者積體電路曰趨精密與複雜化 =面上製作足夠的金屬内連線,目前大多;;5:: =層立(:構方式,以完成各個元件的連;=屬 金屬内連線之八=ter-MetaiDielectrics)來作為隔離各 電層的材料包在習知技藝中用來作為金屬間介 討匕括有·電漿氧化矽(PE-OX ; Plasma ^ anCed 〇Xlde)、電漿四乙氧基矽玻璃(PE-TE0S ; S:二hanced tetraethyl orthosilicate glass)、 產^ 數之介電材(如Dow—coring公司生 p,年來,為配合兀件尺寸縮小化的發展以及提高元件 =速度的需求’具有低電阻常數和高電子遷移阻抗的銅 孟屬,已逐漸被應用來作為金屬内連線的材質,取代以往 的鋁金屬製程技術。其中配合銅金屬的鑲嵌式(Cu damascene)内連線技術不僅可達到内連線的縮小化,同時 也解決了金屬銅蝕刻不易的問題,因此已成為現今多重内 連線主要的發展趨勢。另一方面,為了將金屬間介電層的 電奋儘可忐的降低,目前已使用如氟摻雜氧化層(F SQ )、 氫摻雜氧化層(HSQ,hydrogen silses_qui〇xane)、甲基 563186 五、發明說明(2) 摻雜氧化層(MSQ; methyl si lsesquioxane)等低介電常數 的材料來作為金屬間介電層,以減少串音(cr〇ss talk)與 RC時間延遲。 ” 一般習知在基底或半導體元件上的低介電常數材料介 電層之上,會以氨氣(NH3)之電漿處理程序,以除去後續 步驟可能產生的氧化銅(Cu0),然而此種處理同時會使低 介電常數材料受到氨氣電漿之損傷,甚至 差 的問題發生。 曰啕W者刀季乂差 上述之氨氣電漿 面發生損傷的問題, 發明概# 有鐘於此,本發 數材料之表面處理方 漿處理程序之效果, 間介電層的崩潰電壓 產品可靠度(rel iabi dependent dielectr 常數材料介電層之介 為達上述目的, 面處理方法,其步驟 一半導體基底上而形 處理程序。上述電漿 高密度電漿化學氣相 本發明之另一型 處理程序使低介電常數材料介電層表 亟待提出有效的改善之道。 明的主要目的就是提供—種低介電常 法,上述方法不但可達到習知氨氣電 除去氧化銅,使雜質減少而提高金屬 (breakdown v〇ltage),因此縮短與 1 1 ty)相關的依時性介電崩潰 ic breakdown),還具有降低低 電常數的優點。 本發明提供一種低介電常數材料之表 =要包括:沈積一低介電常數材二 介電層;以及施行-氫氣之電喂 處理程序係以電聚化學氣相沈積=’ 沈積法施行。 、或 態為-種低介電常數材料之表面處理563186 V. Description of invention 〇) Invention collar! Xijiming is related to semiconductor process technology, and in particular, to good and reliable production. The method ′ can increase the breakdown voltage while reducing the dielectric constant. Technology back; integrated circuits are becoming more sophisticated and complicated = enough metal interconnects are made on the surface, most of them are currently; 5 :: = layered (: structured to complete the connection of various components; = belong to Eight metal interconnects = ter-MetaiDielectrics) as a material package for isolating the electrical layers. It is used in the art as an intermetallic intermediary. Plasma ^ anCed 〇Xlde ), Plasma tetraethoxy silicate glass (PE-TE0S; S: two-hanced tetraethyl orthosilicate glass), a number of dielectric materials (such as the Dow-coring company produced p, over the years, in order to match the size of the components The need for development and improvement of component = speed '. Copper genus with low resistance constant and high electron migration resistance has gradually been used as the material of metal interconnects, replacing the previous aluminum metal process technology. Among them, copper metal inlay Cu (Damascene) interconnect technology can not only reduce the size of interconnects, but also solve the problem of difficult copper metal etching, so it has become the main development trend of multiple interconnects today. On the other hand, Dielectric layer The electrical energy can be reduced as much as possible. At present, such as fluorine doped oxide layer (F SQ), hydrogen doped oxide layer (HSQ, hydrogen silses_quioxane), methyl group 563186 5. Invention description (2) Doped oxidation Layer (MSQ; methyl si lsesquioxane) and other low dielectric constant materials as the intermetal dielectric layer to reduce cross talk (cross talk) and RC time delay. "Generally known low on the substrate or semiconductor components On top of the dielectric layer of the dielectric constant material, a plasma treatment process of ammonia gas (NH3) will be used to remove copper oxide (Cu0) that may be generated in subsequent steps. However, this treatment will also expose the low dielectric constant material to ammonia. The damage of gas plasma is even worse. The problem of damage caused by the above-mentioned ammonia gas plasma surface is worse than the above. The invention is summarized here. The surface treatment of this material The effect of the program, the reliability of the breakdown voltage product of the interlayer dielectric layer (rel iabi dependent dielectr constant material, the dielectric layer of the dielectric layer, in order to achieve the above purpose, surface processing method, the step of a semiconductor substrate shape processing program. High Density Plasma Chemical Vapor Phase Another type of processing procedure of the present invention makes an effective improvement of the dielectric layer surface of low dielectric constant materials urgent. The main purpose of Ming is to provide a low dielectric constant method. The conventional ammonia gas is used to remove copper oxide, reduce impurities and improve metal (breakdown voltage), so shorten the time-dependent dielectric breakdown (ic breakdown) related to 1 1 ty), and also have the advantage of lowering the electrical constant . The present invention provides a table of a low dielectric constant material. It should include: depositing a low dielectric constant material and a second dielectric layer; and performing an electric feeding of hydrogen. The processing procedure is performed by electropolymer chemical vapor deposition = 'deposition method. , Or state-surface treatment of a low dielectric constant material
563186 五 發明說明(3) _______— 方法,其特徵在於藉由上 —~~ 提高崩潰電壓,得到可a二電漿處理程序而除去氧化銅, 驟:沈積一低介電常數二ς高的產品,該製程包括下列步 電層;定義一開口於介電=於了半導體基底上而形成一介 上,並填滿上述開口;w曰中;沈積一銅金屬層於介電層 外之銅金屬層;以及施一上f,械研磨法去除上述開口以 介電層或銅金屬層表面氫氣之電漿處理程序,以除去 數。 <虱化銅,並降低介電層之介電常563186 Description of the five inventions (3) _______ — method, which is characterized by increasing the breakdown voltage to obtain a plasma treatment program to remove copper oxide. Step: deposit a low dielectric constant Product, the process includes the following step layer; defines an opening in the dielectric = forms a dielectric on the semiconductor substrate and fills the opening; w is medium; deposits a copper metal layer on the copper metal outside the dielectric layer Layer; and a plasma treatment process for removing hydrogen from the surface of the dielectric layer or the copper metal layer by mechanical grinding to remove the openings. < Lice copper and reduce the dielectric constant of the dielectric layer
本貫施例係根據太絡日日 屬内連線製程上,鑲嵌結構的… 熟悉此技藝者亦可應用在雙鑲嵌製程上。 <- 請參照第U圖,其顯示本實施例之起始步驟。標號 0的部为,可能包含數層金屬内連線與數個電性上相〜互 連,的半導體元件,如M0S電晶體、電阻、邏輯元件等, 為簡化圖式起見,金屬間介電層102以下的半導體基底與 積體電路元件僅以標號1 〇 〇代表之。This example is based on the Tailuo Japanese daily interconnection process, and the mosaic structure ... Those who are familiar with this technique can also apply it to the dual mosaic process. <-Please refer to FIG. U, which shows the initial steps of this embodiment. The part numbered 0 is a semiconductor element that may include several layers of metal interconnects and several electrical phases, such as M0S transistors, resistors, logic elements, etc. In order to simplify the diagram, the intermetallic Semiconductor substrates and integrated circuit elements below the electrical layer 102 are represented by the reference numeral 100 only.
介電層102代表一低介電層常數之介電材料,通常是 摻碳或摻氫之氧化矽(S i OC : Η )類介電材料,例如氫摻雜氧 化層(HSQ; hydrogen sil ses-qu i oxane )、曱基4參雜氧化 層(MSQ; methyl silsesquioxane)、氫摻雜聚氧化層 (H-PSSQ; hydrio polysilsesqu i o xane )、甲基摻雜聚氧 化層(M-PSSQ; methyl polysilsesquioxane)、苯基摻雜 聚氧化層(P-PSSQ; phenyl polysilsesquioxane)、摻氟The dielectric layer 102 represents a low-dielectric-layer-constant dielectric material, usually a carbon-doped or hydrogen-doped silicon oxide (S i OC: Η) -type dielectric material, such as a hydrogen-doped oxide layer (HSQ; hydrogen sil ses). -qu i oxane), methyl-based 4-doped oxide layer (MSQ; methyl silsesquioxane), hydrogen-doped poly oxide layer (H-PSSQ; hydrio polysilsesqu io xane), methyl-doped poly oxide layer (M-PSSQ; methyl polysilsesquioxane), phenyl polysilsesquioxane (P-PSSQ), fluorine-doped
0503-8135TWf ; TSMC2002-0261 ; Chiumeow.ptd 第 6 頁0503-8135TWf; TSMC2002-0261; Chiumeow.ptd page 6
563186 五、發明說明(4) 聚對二甲苯醚(FLARE; Allied Signal 或Microwave563186 V. Description of the invention (4) Parylene (FLARE; Allied Signal or Microwave
Materials產製)、芳香族碳氫化合物(Siu; Dqw Chemical產製)、乾凝膠(xer〇gei)、超微孔玻璃 (Nanoglass)、及聚芳烯醚-2(PAE—2)等。上述材料的介電 常數一般在3左右,但範圍可介於丨〜4之間。此介電層可以 化學氣相沈積(CVD),或是以旋塗(spin c〇ating)的9方式 沈積在基底上,然後經過固化(curing)形成如圖中所/之 介電膜。 請參照第1 B圖,接著依照傳統鑲嵌式製程,先利用微 影與#刻程序在介電層1 〇2中定義出金屬内連線的介芦 窗。 曰 請參照第1C圖,再度以微影與蝕刻程序定義出金屬内 連線之溝槽,然後進行全面性的沈積,以在内連線溝槽與 介層窗的底部與側壁形成一金屬阻障層丨〇 4。此阻障層i 〇 4 可幫助後續金屬的附著並防止其擴散,對銅而言,適當的 擴散阻障層材料包括:鈕(Ta),氮化鈕(TaN),氮化鐫 (WN ) ’或是習知製程中常用的氮化鈦(T i N )等。(Manufactured by Materials), aromatic hydrocarbons (manufactured by Siu; manufactured by Dqw Chemical), xerogei, nanoglass, polyarylene ether-2 (PAE-2), and the like. The dielectric constant of the above materials is generally around 3, but the range can be between 1-4. This dielectric layer can be deposited by chemical vapor deposition (CVD) or spin coating in 9 ways on a substrate, and then cured to form a dielectric film as shown in the figure. Please refer to FIG. 1B. Then, according to the traditional mosaic process, first use the lithography and #lithography procedures to define the dielectric interconnects in the dielectric layer 1 102. Please refer to Figure 1C, define the metal interconnect trenches again by lithography and etching procedures, and then perform a comprehensive deposition to form a metal resistance between the interconnect trenches and the bottom and sidewalls of the via window. Barrier layer 丨 〇4. This barrier layer 〇4 can help the subsequent metal adhesion and prevent its diffusion. For copper, suitable diffusion barrier layer materials include: button (Ta), nitride button (TaN), hafnium nitride (WN) 'Or titanium nitride (T i N) commonly used in conventional processes.
請參照第1 D圖,接著,以化學氣相沈積法(CVD)、物 理氣相沈積法(PVD),或電鍍沈積法(Eiectr〇plating)在 阻障層1 0 4上沈積鋼金屬層1 0 6,並使其填滿前述之内連線 溝槽與介層窗。較佳者,可利用離子化金屬電漿(I MP)先 在基底上沈積一層厚約3〇〇〜15〇〇埃的晶種層,然後再以電 鍵法完成銅導電層的沈積。通常阻障層與晶種層的沈積程 序可在多腔反應室(Cluster chamber)的不同腔中依序完Please refer to FIG. 1D. Next, a steel metal layer 1 is deposited on the barrier layer 104 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating (Eiectrplating). 0 6 and make it fill the aforementioned interconnecting trenches and vias. Preferably, an ionized metal plasma (I MP) can be used to first deposit a seed layer having a thickness of about 3,000 to 15,000 angstroms, and then the copper conductive layer can be deposited by an electrical bonding method. Usually, the deposition process of the barrier layer and the seed layer can be completed sequentially in different chambers of the multi-chamber reaction chamber.
0503-8135B/f ; TSMC2002-0261 ; Chiumeow.ptd 563186 五、發明說明(5) 成而不破真空,藉以提高製程的可靠度與產能。 接下來’請參照第1E圖,完成阻障層1 04與銅金屬層 1 0 6的沈積後’以化學機械研磨法進行平坦化,將内連線 溝槽以外的銅金屬層1 〇 6與阻障層1 〇 4去除,研磨的過程包 括:銅金屬的研磨、阻障層的研磨、以及最後一道氧化物 拋光(oxide buff ing)的手續,其中各階段係使用不同的 研磨衆液。本發明於化學機械研磨後之低介電常數之介電 層1 0 2表面施行一氫氣之電漿處理程序丨〇 7,上述電漿處理 程序之處理條件如下:處理時間介於卜4〇秒之間,以1〇秒 為佳;處理溫度介於20〜500 °C之間,以400 °C為佳;處理 時之氣體流速介於100〜20〇〇sccm之間,以66〇sccm為佳; 處理壓力介於1T〜7T之間,以4T為佳;操作功率介於50〜 3 0 0 0 W之間,以6 0 0 W為佳。且上述電漿處理程序係以電漿 化學氣相沈積法或高密度電漿化學氣相沈積法施行。 之後,再覆以上蓋氮化層1 〇 8,即可得到第丨F圖所示 的結構。 本發明方法之氫氣電漿處理程序具有以下優點,1 )氫 氣電漿處理程序之還原能力優於氨氣之電漿處理程序,可 以還原氧化銅而得到較為純的銅,2)由於使金屬間介電層 與銅導線之氧化銅還原,同時可提高崩潰電壓,因而得以 縮短與產品可靠度(rel iabi丨i ty)相關的依時性介電崩潰 (Unie-dependent dielectric breakd〇wn),產品可靠度 更佳,3)介電層表面之處理雖然不會與表面反應,僅為& 原氧化銅,對於低介電常數材料之介電層表面之附著力也0503-8135B / f; TSMC2002-0261; Chiumeow.ptd 563186 V. Description of the invention (5) It can be completed without breaking the vacuum to improve the reliability and productivity of the process. Next, "please refer to Fig. 1E, after the barrier layer 104 and the copper metal layer 106 have been deposited," planarize by chemical mechanical polishing method, and then copper metal layer 106 and the copper metal layer other than the interconnect trenches. The barrier layer 104 is removed, and the grinding process includes: grinding of copper metal, grinding of the barrier layer, and a final oxide buff ing procedure, wherein different stages use different grinding liquids. According to the invention, a hydrogen plasma treatment process is performed on the surface of the dielectric layer 10 with a low dielectric constant after chemical mechanical polishing. The processing conditions of the above plasma treatment process are as follows: the processing time is between 40 seconds 10 seconds is preferred; processing temperature is between 20 ~ 500 ° C, preferably 400 ° C; gas flow rate during processing is between 100 ~ 200 sccm, and 66 ° sccm is The processing pressure is between 1T ~ 7T, preferably 4T; the operating power is between 50 ~ 300W, preferably 600W. In addition, the above-mentioned plasma treatment process is performed by a plasma chemical vapor deposition method or a high-density plasma chemical vapor deposition method. After that, the nitrided layer 108 is covered again to obtain the structure shown in FIG. The hydrogen plasma treatment process of the method of the present invention has the following advantages: 1) the hydrogen plasma treatment process has a reduction ability better than the ammonia plasma treatment process, which can reduce copper oxide to obtain relatively pure copper, 2) The reduction of the copper oxide of the dielectric layer and the copper wire can increase the breakdown voltage at the same time, thereby shortening the Unie-dependent dielectric breakdwn related to product reliability (rel iabi 丨 i ty). Better reliability, 3) Although the surface treatment of the dielectric layer will not react with the surface, it is only & original copper oxide, and it has good adhesion to the surface of the dielectric layer of low dielectric constant materials.
563186 五 發明說明(6) -------- 幫助’同時’4)上述低介電常數材料 、電常數。 介電層也可降低 露如上,然其並非用 在不脫離本發明之精 飾’因此本發明之保 定者為準。 雖然本發明已以一較佳實施例揭 限定本發明,任何熟習此技藝者, :申::範圍内,當可作各種之更動與潤 °執圍當視後附之申請專利範圍所界 563186 圖式簡單說明 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 第1 A〜1 F圖為一系列剖面圖,用以說明本發明一較佳 實施例之鑲嵌式銅製程。 符號說明 100〜基底與半導體元件; 1 0 2〜低介電常數之金屬間介電層; 丨 1 0 3〜電漿處理程序; 1 0 4〜阻障層; 106〜銅金屬層; 1 0 8〜上蓋層。563186 V. Description of the invention (6) -------- Help ‘at the same time’ 4) The above-mentioned low dielectric constant materials and electric constants. The dielectric layer can also reduce the exposure as above, but it is not used without departing from the decoration of the present invention ', so the warranty of the present invention shall prevail. Although the present invention has been limited to the present invention by a preferred embodiment, anyone skilled in the art can, within the scope of ::, make various changes and modifications. The scope of patents attached to the scope of the application is bounded by 563186 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Section 1 A ~ 1 Figure F is a series of cross-sectional views illustrating a mosaic copper process according to a preferred embodiment of the present invention. Explanation of symbols: 100 ~ substrate and semiconductor element; 102 ~ low intermetal dielectric layer; 10 ~ 3 plasma processing program; 104 ~ barrier layer; 106 ~ copper metal layer; 10 8 ~ top cover.
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