TW557519B - Process for fabricating semiconductor package with lead frame as chip carrier - Google Patents
Process for fabricating semiconductor package with lead frame as chip carrier Download PDFInfo
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- TW557519B TW557519B TW091116104A TW91116104A TW557519B TW 557519 B TW557519 B TW 557519B TW 091116104 A TW091116104 A TW 091116104A TW 91116104 A TW91116104 A TW 91116104A TW 557519 B TW557519 B TW 557519B
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- chip
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- guide leg
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000000465 moulding Methods 0.000 claims abstract description 10
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 239000000084 colloidal system Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 6
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 239000003292 glue Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- ONBQEOIKXPHGMB-VBSBHUPXSA-N 1-[2-[(2s,3r,4s,5r)-3,4-dihydroxy-5-(hydroxymethyl)oxolan-2-yl]oxy-4,6-dihydroxyphenyl]-3-(4-hydroxyphenyl)propan-1-one Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1OC1=CC(O)=CC(O)=C1C(=O)CCC1=CC=C(O)C=C1 ONBQEOIKXPHGMB-VBSBHUPXSA-N 0.000 description 4
- 229940126142 compound 16 Drugs 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000004033 plastic Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 241001596784 Pegasus Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
557519 五、發明說明（1) [發明領域] 本發明係有關一種半導體封裝件製法及其結構，特別 係指一種使用導線架以承載多媒體卡（Multi—Media Card， MMC)晶片之半導體封裝件製法及其結構。 [發明背景] 多媒體卡（Mu 11i-Media Card，MMC)是一種小型積體 電路（Integrated Circuit, IC)裝置，具有控制記憶體晶 片，以儲存及處理如數位影音、圖片畫面等多媒體資料之 功能。然而用在多媒體卡裡的晶片要執行運作，該晶片必 須載接到基板或膠片等晶片承載件上，方可使晶片導電連 結到外部插槽以發揮晶片功能，因此，晶片承載件對多媒 體卡的重要性不言而喻。 惟傳統晶片承載件的種類，不外乎基板、TAB膠片或 導線架三大宗；但基板或膠片在製造過程中需要經過精密 的線路設計及佈局，其單價較高，因此選用基板或膠片作 為晶片承載件會使封裝成本增加，連帶壓縮多媒體卡的利 潤空間。有鑑於此，台灣專利公告號第484, 222號遂揭露 一種以成本較低的導線架（Lead Frame)來載接多媒體晶片 之半導體封裝件。 如第5A圖所示，該半導體封裝件之導線架5〇包含一晶 片座52以及位於晶片座52單側之多數導腳51，各導腳51包 括有一外導腳部51a，一中間導腳部51b及一内導腳部 5 1 c ’該外導腳部5 1 a與内導腳部5丨c間係藉由該中間導腳 部51b相連接。其中，該外導腳部51a構成的平面510a與該557519 V. Description of the Invention (1) [Field of Invention] The present invention relates to a method for manufacturing a semiconductor package and a structure thereof, and particularly to a method for manufacturing a semiconductor package using a lead frame to carry a Multi-Media Card (MMC) chip. And its structure. [Background of the Invention] A multimedia card (Mu 11i-Media Card, MMC) is a small integrated circuit (IC) device that has the function of controlling a memory chip to store and process multimedia data such as digital audio and video, picture frames, etc. . However, for the chip used in the multimedia card to perform operations, the chip must be mounted on a wafer carrier such as a substrate or a film, so that the chip can be conductively connected to an external slot to perform the chip function. Therefore, the chip carrier The importance of self-evident. However, the types of traditional wafer carriers are nothing more than three major substrates, TAB film or lead frames; however, the substrate or film needs to undergo precise circuit design and layout during the manufacturing process, and its unit price is higher, so the substrate or film is selected as the wafer The carrier will increase the packaging cost and compress the profit margin of the multimedia card. In view of this, Taiwan Patent Publication No. 484, 222 then discloses a semiconductor package that uses a low-cost lead frame to carry a multimedia chip. As shown in FIG. 5A, the lead frame 50 of the semiconductor package includes a chip holder 52 and a plurality of guide pins 51 on one side of the chip holder 52. Each guide pin 51 includes an outer guide pin portion 51a and an intermediate guide pin. The portion 51b and an inner guide leg portion 5 1 c ′ are connected between the outer guide leg portion 5 1 a and the inner guide leg portion 5 丨 c through the intermediate guide leg portion 51 b. Among them, the plane 510a formed by the outer guide leg portion 51a and the plane
557519 内導腳部51c平面間具有一預定之高度差；因此，將如多 媒體晶片、快閃記憶體晶片等晶片5 3黏接到内導腳部5 1 c 上，並以多條金線5 4供該晶片5 3與導線架5 0電性連接後， 金線5 4的線弧高度仍然小於該内外導腳間之高度差。 完成上片及銲線作業的導線架50上需形成一用於包覆 該晶片53及導腳51之封裝膠體56，以保護晶片53不受外界 水塵污染。然封膠時該外導腳部5 1 a之頂面必須外露出封 裝膠體56，使晶片53可藉由該導腳51之外露表面電性連結 到外部插槽（未圖示）上。557519 The inner guide leg 51c has a predetermined height difference between the planes; therefore, a chip 5 3 such as a multimedia chip, a flash memory chip, etc. is bonded to the inner guide leg 5 1 c, and a plurality of gold wires 5 are used. After the chip 53 is electrically connected to the lead frame 50, the arc height of the gold wire 54 is still smaller than the height difference between the inner and outer guide pins. The lead frame 50 that has completed the wafer loading and wire bonding operations needs to form an encapsulant 56 for covering the wafer 53 and the guide pins 51 to protect the wafer 53 from external water and dust. However, at the time of sealing, the top surface of the outer guide leg portion 5 1 a must expose the sealing gel 56 so that the chip 53 can be electrically connected to an external slot (not shown) through the exposed surface of the guide leg 51.
然而，此種以導線架承載晶片之半導體封裝件在使用 上具有若干缺失，其一在於此種導線架之外導腳部係高於 内導腳部一高度，因此，導腳在製作時於外導腳部與中間 導腳部之連接處會形成彎角（如第5A圖虛線圈所示），該雙 角部位在模壓作業（Molding)中往往會有溢膠（Flash)產生 其上，導致外導腳部外露的導電區域受溢膠遮蓋，如第5 圖所示，此現象除有礙成品外觀，更會影響多媒體 界裝置之電性連接品質。然若欲清除外導腳部 所形成之溢膠，業者往往需以化學或機 將導致成本增加。 飞马之’如λ [發明概述]However, this type of semiconductor package that uses a lead frame to carry a chip has several defects in use. One is that the outer leg of the lead frame is higher than the inner leg by height. The connection between the outer guide leg and the middle guide leg will form a bend (as shown by the dotted circle in Figure 5A), and the double corner part will often have flash (Flash) generated on it during molding. As a result, the exposed conductive area of the outer guide leg is covered by the overflowing glue. As shown in Figure 5, this phenomenon not only hinders the appearance of the finished product, but also affects the electrical connection quality of the multimedia device. However, in order to remove the spilled glue formed by the outer guide feet, the industry often needs to use chemicals or machinery to increase the cost. Pegasus's such as λ [Invention Summary]
種以導線架為晶片承載 以免導腳表面產生溢 1111質及導電信賴性。 種以導線架為晶片承載 本發明之主要目的在於提供一 件之半導體封裝件製法及其結構， 膠’進而提昇封裝成品的電性連接 本發明之另一目的在於提供一This type uses a lead frame as the chip carrier to prevent the surface of the guide pins from overflowing and 1111 quality and conductive reliability. A main purpose of the present invention is to provide a method for manufacturing a semiconductor package and a structure thereof, and to improve the electrical connection of the packaged product. Another object of the present invention is to provide a
557519 結構，以有效降 爭性。 提供一種以導線 結構’以免除溢 簡化。 ，本發明揭露一 製法及其結構， 以下步驟··首先 導腳及第二導腳 下表面，其中， 間導腳段以及一 腳段係高出該内 段與該第一導腳 至少一晶片到第 銲線，藉以電性 形成一封裝膠體 片，惟該第一及 膠體，以使晶片 五、發明說明（3) 件之半導體封 使多媒體卡在 本發明之 件之半導體封 使多媒體卡的 為達成上 晶片承載件之 體封装件之製 架’該導線架 別具有一上表 導腳各由一外 成，惟該第一 度，且該第二 於同一水平面 段之上表面上 第一及第二導 第一導腳 '第 腳部之上表面 面電性導接至 裝件製法及其 價袼上更具競 再一目的在於 裝件製法及其 封裝製程更為 揭及其他目的 半導體封裝件 造方法係包括 具有多數第一 面及一相對之 導腳段，一中 導腳之該外導 導腳之外導腳 ;之後，接置 ;復銲接多數 腳上；而後， 二導腳以及晶 係外露出封裝 外界。 低封裝成本， 架為晶片承載 膠清除步驟， 種以導線架為 其中，該半導 製備一導線 ’且各導腳分 該第一及第二 内導腳段所構 導腳段一高 之外導腳段位 一導腳内導腳 連接該晶片至 ’用以包覆該 第二導腳外導 得藉此外露表 上述半導體封襄件之製 —，^ ·Τ <承疋々次，在經過導 上片、打線等習知步驟後，需藉由一模壓作 a01dhg)，亦即令載有晶片與銲線之導線架置入一 (Mold)内，以注入熔融樹脂化合物而形成一 、伽、 分導線架之封裝膠體·缺而*难 匕覆日日片與告 ，…、而在傳統模壓過程中，為讓第557519 structure to effectively reduce competitiveness. A wire structure is provided to avoid overflow simplification. The present invention discloses a manufacturing method and a structure thereof. The following steps: first, a lower surface of a guide leg and a second guide leg, wherein an intermediate guide leg segment and a leg segment are higher than the inner segment and the first guide leg by at least one chip to The first bonding wire is used to form an encapsulating gel sheet electrically, but the first and colloid are used to make the wafer. 5. The semiconductor encapsulation of the invention (3) The semiconductor encapsulation of the multimedia card The semiconductor encapsulation of the multimedia card of the invention is Reaching the frame of the body package of the upper wafer carrier, the lead frame has a top table and each foot is made of one outer, but the first degree, and the second on the same horizontal plane above the first surface and The second lead, the first lead, and the upper surface of the first leg are electrically connected to the mounting method and its price. The purpose is to make the mounting method and its packaging process easier and other purposes. The manufacturing method includes a plurality of first faces and a pair of opposite guide legs, a middle guide leg and the outer guide leg outside the guide leg; thereafter, connecting; re-welding the majority of the leg; then, the second guide leg and The crystal system is exposed outside the package boundary. Low packaging cost, the frame is a wafer carrying glue removal step, and a kind of lead frame is used as the semiconductor, and a semi-conductor prepares a wire, and each guide pin is divided by the first and second inner guide pin sections. A guide pin internal guide pin is connected to the chip to 'to cover the second guide pin, so as to expose the above-mentioned semiconductor sealing system—, ^ · T < bearing times, in After the conventional steps such as filming, wire bonding, etc., it is necessary to press a die (a01dhg), that is, the lead frame carrying the chip and the bonding wire is placed in a (Mold) to inject a molten resin compound to form a 、 The encapsulation gel of the sub-lead frame is lacking and difficult to cover Japanese and Japanese films, and ... In the traditional molding process,
16869.ptd16869.ptd
557519 五、發明說明（4) 導腳外導腳段之上表面保持外露狀態，該第一導腳之外導 腳段即使抵住模具，亦無法完全杜絕溢膠問題產生，·因 此:本發明製法在模壓時是將封裝膠體完整地包覆住第一 ^第二導腳之外導腳段，待封裝膠體固化成㈣，再磨除 间出該第一及第二導腳外導腳段之封裝膠體部分，以裸露 出外導腳段之上表面，此舉不但能解決模壓作業中溢膠產 ，的問題，而且無須再進行溢膠清除步驟，使多媒體卡的 製造成本大為降低。 本發明之另一實施例，係將原本接置在該内導腳段上 的晶片移置到與内導腳段同一水平面之晶片座上，由於該 晶片座周圍設有繫條（Tie Bar)，故能提供較強的支撐性 及平面度，避免晶片在後續製程中發生裂損；另一方面， 晶片座亦可充當散熱件使用，使半導體封裝件具有更佳的 散熱效果。 [發明詳細說明及實施例] 以下即配合第1 A至1 E圖及第4圖詳細說明本發明以導 線架作為晶片承載件之半導體封裝件製造方法及其結構。 請參閱第1A至1E圖，該圖係以多媒體卡（Multi__Media557519 V. Description of the invention (4) The upper surface of the outer guide leg of the guide foot remains exposed. Even if the outer guide leg section of the first guide foot is against the mold, the problem of overflow of glue cannot be completely prevented. Therefore: The present invention In the molding method, the encapsulating gel completely covers the outer leg of the first ^ second guide leg, and the encapsulating gel is cured to form a ridge, and then the outer and outer leg portions of the first and second guide legs are ground. The plastic part of the package is exposed to expose the upper surface of the outer guide leg. This can not only solve the problem of plastic overflow in the molding operation, but also eliminate the need for the plastic overflow removal step, which greatly reduces the manufacturing cost of the multimedia card. In another embodiment of the present invention, a wafer originally connected to the inner guide leg section is moved to a wafer holder on the same level as the inner guide leg section. Because a tie bar (Tie Bar) is provided around the wafer holder Therefore, it can provide strong support and flatness to avoid chip damage in subsequent processes; on the other hand, the chip holder can also be used as a heat sink to make the semiconductor package have better heat dissipation effect. [Detailed description and embodiments of the invention] The manufacturing method and structure of a semiconductor package using a lead frame as a wafer carrier according to the present invention will be described in detail below with reference to FIGS. 1A to 1E and FIG. 4. Please refer to Figures 1A to 1E, which are based on the multimedia card (Multi__Media
Card，MMC)為例，詳細說明本發明半導體封裝件之製作流 程。 ",L 如第1A圖所示，製備一金屬材質之導線架ι〇，該導線 架10具有多數之第一導腳11及第二導腳12，各導腳η，12 具有一上表面110, 120及一相對之下表面111，121，且該第 一導腳11與第二導腳1 2係以交錯間隔之方式排列，使任一Card (MMC) as an example to explain in detail the manufacturing process of the semiconductor package of the present invention. ", L As shown in FIG. 1A, a metal lead frame ι0 is prepared. The lead frame 10 has a plurality of first guide pins 11 and second guide pins 12, and each guide pin η, 12 has an upper surface. 110, 120, and a relatively lower surface 111, 121, and the first guide pin 11 and the second guide pin 12 are arranged in a staggered manner so that any
16869.ptd 第11頁 557519 五、發明說明（5) ^ 第〆導腳11倶位於兩第二導腳12之間。其中，該第一及第 二導腳11，12各由一外導腳段Ha、一中間導腳段lib及一 内導腳段11c所構成，並且該第一導腳11之外導腳段11a上 表面110a係高出下導腳段He上表面ll〇c—高度h，且該第 二導腳12之外導腳段12a與第一導腳11之外導腳段iia係位 於同一平面，使得該内導腳段Π c上即便完成銲線作業， 形成於導線架上的金線弧高仍小於内外導腳段11 a，11 c所 形成之高度差（即h)。16869.ptd Page 11 557519 V. Description of the invention (5) ^ The second guide pin 11 倶 is located between the two second guide pins 12. The first and second guide legs 11 and 12 are each composed of an outer guide leg section Ha, a middle guide leg section lib, and an inner guide leg section 11c, and the outer guide leg section of the first guide leg 11 The upper surface 110a of 11a is higher than the upper surface 110c of the lower guide leg He—the height h, and the outer guide leg segment 12a outside the second guide leg 12 and the outer guide leg segment iia outside the first guide leg 11 are located on the same plane. Therefore, even if the welding operation is completed on the inner guide leg section Π c, the arc height of the gold wire formed on the lead frame is still smaller than the height difference (ie h) formed by the inner and outer guide leg sections 11 a and 11 c.
再者，此處使用之導線架10，除以第一導腳11與第二 導腳1 2交錯列置外，亦可僅形成單一種導腳。如第2圖所 示，另一適用於製造多媒體卡之導線架20係由複數條長導 腳21(Longer Lead)構成，每一導腳21均如前述都具有一 外導腳段2 1 a、一中間導腳段2 1 b以及一内導腳段2 1 c，且 外導腳段2 1 a與内導腳段2 1 c間皆形成有一預定之高度差 (同第1 A圖h )，以使晶片（如第2圖中虛線框所示）黏接到内 導腳段2 1 c上後，晶片的厚度仍遠小於此一高度差。Furthermore, in addition to the lead frame 10 used here, in addition to the first guide pin 11 and the second guide pin 12 being staggered, only a single type of guide pin may be formed. As shown in FIG. 2, another lead frame 20 suitable for manufacturing a multimedia card is composed of a plurality of Longer Leads 21 (Longer Lead), each of which has an outer guide leg section 2 1 a A middle guide leg section 2 1 b and an inner guide leg section 2 1 c, and a predetermined height difference is formed between the outer guide leg section 2 1 a and the inner guide leg section 2 1 c (same as in Fig. 1 A h) ), So that after the chip (as shown by the dashed box in Figure 2) is adhered to the inner guide leg section 2 1 c, the thickness of the chip is still much smaller than this height difference.
•除以内導腳段當作晶片載接的承座外，具有晶片座 (Die Pad)之導線架亦適於製造多媒體卡。如第3圖所示， 此導線架30包含有多數單一或非單一型態的導腳31及一晶 片座32，其中，該導腳31具有一外導腳段31&、一中間導 :士一内導腳段31c，且該内導腳段3U係低於外導 敫31a—預設咼度差H，而與該晶片座“位於同一水平面 曰二該晶片座32周圍可藉由至少一繫條33(Tie 供該 -片座32連接至導線架3〇外框，故晶片（未圖示）黏接到晶• In addition to the inner guide leg section as a socket for chip loading, a lead frame with a die pad is also suitable for manufacturing multimedia cards. As shown in FIG. 3, the lead frame 30 includes a plurality of single or non-single types of guide pins 31 and a wafer holder 32, wherein the guide pin 31 has an outer guide leg section 31 and an intermediate guide: An inner guide leg segment 31c, and the inner guide leg segment 3U is lower than the outer guide leg 31a—a predetermined difference in height H, and is located at the same level as the wafer base, ie, around the wafer base 32, by at least one The tie bar 33 (Tie is used to connect the chip holder 32 to the lead frame 30, so the wafer (not shown) is glued to the crystal
557519 五、發明說明（6) 片座32上後可具有較佳的支撐性以及平面度；另一方面， 該晶片座3 2亦可充當散熱件使用，加速排除晶片運作中產 生的熱能，使晶片（未圖示）不致過熱而受損。 接而’如第1B圖所示，備妥至少一半導體晶片13，如 多媒體晶片（Multi-Media Chip)、可抹寫之程式化記憶體 (Electrically- Erasable and Programmable Read-Only Memory，EEPROM)晶片及控制晶片（Controlled Chip)等， 該晶片13具有一作用表面i3〇及一相對之非作用表面131， 該作用表面130上形成有複數個婷塾i32(Bond Pads)。利 用傳統上片技術將該晶片1 3之非作用表面1 3 1黏接到該第 一導腳1 1内導腳段1 1 c的上表面11 〇 c上，復以銲線技術 (Wire Bonding)分別地銲連各晶片銲墊132至第一及第二 導腳11，12之内導腳段lie上，使晶片13可藉由多條金線14 電性連結至導線架1 〇上，以進行模壓作業。 模壓作業（Mo 1 d i ng)之實施係將載有晶片與金線之導 線架放置入一内設模穴150(Mold Cavity)之模具i5(Mold) 中。如第1 C圖所示，藉由一如環氧樹脂（Εροχγ)等熔融狀 態的樹脂化合物1 6注入模穴1 5 0内，用以包覆該第一導腳 11、第二導腳（未圖示）及晶片13，此等步驟倶為習知，故 不另行著墨。然而，該樹脂化合物1 6係完全包覆住該第一 導腳11之外導腳段11a(及第二導腳之外導腳段，圖中未 示）’並未採用習知外導腳段抵住模穴之方式，因此，成 型後的封裝膠體1 6 (指樹脂化合物成型後之狀態，因此與 樹脂化合物1 6以相同標號顯示之）不僅將晶片丨3及第二導557519 V. Description of the invention (6) The chip holder 32 can have better support and flatness after being mounted on the other hand. On the other hand, the chip holder 32 can also be used as a heat sink to accelerate the elimination of heat generated during the operation of the chip, so that The chip (not shown) is not overheated and damaged. Then, as shown in FIG. 1B, at least one semiconductor chip 13 is prepared, such as a Multi-Media Chip, an Electrically-Erasable and Programmable Read-Only Memory (EEPROM) chip. And a control chip (Controlled Chip), the chip 13 has an active surface i30 and an opposite non-active surface 131. A plurality of bonding pads 32 are formed on the active surface 130. The non-active surface 1 3 1 of the wafer 13 is bonded to the upper surface 11 oc of the inner guide leg section 1 1 c of the first guide pin 1 1 by using a conventional wafer bonding technology, and then wire bonding technology is used. ) Weld each of the wafer pads 132 to the first and second guide pins 11 and 12 respectively, so that the chip 13 can be electrically connected to the lead frame 10 through a plurality of gold wires 14, For molding operations. The molding operation (Mo 1 d i ng) is carried out by placing a wire rack carrying a wafer and a gold wire into a mold i5 (Mold) with a built-in cavity 150 (Mold Cavity). As shown in FIG. 1C, a resin compound 16 in a molten state such as epoxy resin (Εροχγ) is injected into the cavity 150 to cover the first guide leg 11 and the second guide leg ( (Not shown) and the wafer 13, these steps are known, so they are not inked separately. However, the resin compound 16 completely covers the outer guide leg section 11a of the first guide leg 11 (and the outer guide leg section of the second guide leg, which is not shown in the figure). The way that the segment resists the cavity, therefore, the molding compound 16 (refers to the state after the resin compound is molded, so it is shown with the same symbol as the resin compound 16) not only the wafer 3 and the second guide
16869.ptd 第13頁 557519 五、發明說明（7) . ^ ^ 腳（未圖示）封包在内’亦完整包覆住整條第一導腳11，使 第一導腳11外導腳段lla的上表面覆有封裝膠體 1 6 ° 之後，如第1D圖所示，使用一研磨機i7(Grinder)將 成型固化的封裝膠體自頂面向下磨除，該磨除部分的厚度 H，經過計算，使研磨完成的半導體封裝件1，其第一導腳 11之外導腳段lla上表面ll〇a(第二導腳外導腳段之上表面 亦同，惟圖中未示）能完整外露出該封裝膠體16頂面。惟 去除外導腳段11a上表面ll〇a上多餘封裝膠體16之方法並 不以研磨技術（Grinding)為限，其他方法若可達成將外導 腳段11a上表面ll〇a外露出封裝膠體16之功效者，倶為本 發明之範疇所涵蓋。 復如第1E圖所示’利用錢鍍（sputtering)或電鍍 (Plat ing)等方式將一導電性保護層i8(Conduct ive Layer)，如金層（Golden Layer)等敷鍍到第一導腳11外導 腳段11a之上表面110a上，俾形成一具有複數個金質銲線 墊19(6〇1(1611卩丨1^6]：)之半導體封裝件1(即多媒體卡，如 第4圖所示），是以，多媒體卡1裡的晶片1 3可以透過金線 14、導腳11及金質銲線墊19而與一外部插槽（未圖示）電性 連接。 本發明之半導體封裝件在膠體封裝完成後，另將多餘 的封裝膠體磨除，使第一導腳之外導腳段上表面完整地外 露出封裝膠體之外，因此相較於習知方法，上揭半導體封 裝件製法完全不會有溢膠污染導腳表面的問題，也無須再16869.ptd Page 13 557519 V. Description of the invention (7). ^ ^ The feet (not shown) are enclosed in the package, and the entire first guide leg 11 is completely covered, so that the first guide leg 11 is outside the leg section. After the upper surface of lla is coated with the encapsulating gel 16 °, as shown in FIG. 1D, the molded solidified encapsulating colloid is removed from the top to the bottom using a grinder i7 (Grinder), and the thickness H of the abraded part passes through It is calculated that the ground surface 11a of the semiconductor package 1 after grinding, the outer surface of the first leg 11a of the first leg 11 (the upper surface of the second leg of the outer leg is the same, but not shown in the figure). The top surface of the encapsulant 16 is completely exposed. However, the method of removing the excess encapsulation gel 16 on the upper surface 110a of the outer guide leg section 11a is not limited to the grinding technique. If other methods can be used to expose the upper surface 110a of the outer guide leg section 11a to the packaging colloid, The effect of 16 is not covered by the scope of the present invention. As shown in Figure 1E, a conductive protective layer i8 (such as a Golden Layer) is applied to the first guide pin by means of sputtering or plating. 11 On the upper surface 110a of the outer guide leg section 11a, a semiconductor package 1 (that is, a multimedia card, such as the first one) having a plurality of gold bonding pads 19 (6〇1 (1611 卩 丨 1 ^ 6) :) is formed. (Shown in FIG. 4), so that the chip 13 in the multimedia card 1 can be electrically connected to an external slot (not shown) through the gold wire 14, the guide pin 11 and the gold wire bonding pad 19. The present invention After the colloidal packaging of the semiconductor package is completed, the extra packaging colloid is ground away, so that the upper surface of the lead leg outside the first lead pin completely exposes the encapsulation gel. Therefore, compared to the conventional method, The semiconductor package manufacturing method does not have the problem of contamination of the surface of the guide pin by overflowing glue, and there is no need to
16869.ptd 第14頁 557519 五、發明說明（8) 進行溢膠清除步驟，對於製程簡化以及降低封裝成本均有 助益。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容範圍，本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中，任何他人所完成之 技術實體或方法，若是與下述之申請專利範圍所定義者係 完全相同，或是同一等效之變更，均將被視為涵蓋於此申 請專利範圍之中。16869.ptd Page 14 557519 V. Description of the invention (8) Performing the overflow cleaning step is helpful for simplifying the manufacturing process and reducing packaging costs. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the patent application described below. Any technical entity or method that is completely the same as defined in the patent application scope described below, or the same equivalent change, will be considered to be covered by this patent application scope.
16869.ptd 第15頁 557519 ---- 圖式簡單說明 [圖式簡單說明] 為讓本發明之上述和其他目的' 顯易懂，將配合較佳實施例以及所 =能更明 明之實价其所附圖式之内容簡述如）：坪細說明本發 第1 Α至1 Ε圖係本發明第一實施例之半 細製作流程圖； 導體封裝件之詳 圖 第2圖係適用於多媒體卡之晶片承載件之 上視示意 第3圖係適用於多媒體卡之晶片承載 上視示意圖； 實施例之 意圖 第4圖係本發明第一實施例之半導體封骏件 視 不 第5A圖係台灣專利第484, 222號所揭露 件之剖面示意圖；以及 千導體封骏 上 第5B圖係第5A圖所示之半導體封裝件 視示意圖。 生溢膠後之 [元件符號說明] 導線架 導腳上表面 1，5半導體封裝件（多媒體卡）i〇,2〇,3〇 11，21，31，51 (第一）導腳 110，120 111，121導腳下表面 11a，21a，31a，51a 外導腳段（部） lib, 21b, 31b, 51b 中間導腳段（部） 11c，21c，31c, 51c 内導腳段（部） 110a，120a，510a 外導腳段上表面16869.ptd Page 15 557519 ---- Simplified illustration of the drawing [Simplified illustration of the drawing] In order to make the above and other objects of the present invention 'obvious and easy to understand, it will cooperate with the preferred embodiment and the actual price The contents of the drawings are as follows :) Figures 1A to 1E of the present invention are semi-fine manufacturing flowcharts of the first embodiment of the present invention; detailed drawings of the conductor package. Figure 2 is suitable for multimedia cards. The top view of the wafer carrier is shown in FIG. 3. FIG. 3 is a top view of a wafer carrier suitable for a multimedia card. The embodiment is intended. FIG. 4 is a view of a semiconductor package in the first embodiment of the present invention. FIG. 5A is a Taiwan patent. A schematic cross-sectional view of the part disclosed in Nos. 484, 222; and a schematic view of the semiconductor package shown in FIG. 5A on the thousand-conductor seal. [Explanation of the component symbols] after the overflow of the glue 1. The top surface of the lead frame of the lead frame 1,5 semiconductor package (multimedia card) i0,20,30,11,21,31,51 (first) lead 110,120 111, 121 lower surface of guide foot 11a, 21a, 31a, 51a outer guide leg section (part) lib, 21b, 31b, 51b middle guide leg section (part) 11c, 21c, 31c, 51c inner guide leg section (part) 110a, 120a, 510a Upper surface of outer guide leg
16869.ptd 第16頁 557519 金質銲線墊 外導腳段與晶片座之高度差 外導腳段與内導腳段之高度差 圖式簡單說明 110c 内導腳段上表面 1 3，5 3晶片 131 晶片非作用表面 1 4，5 4銲線（金線） 150 模穴 17 研磨機 19 Η h Η’ 預設磨除膠體厚度 12 第二導腳32, 52晶片座 130晶片作用表面 1 3 2晶片銲墊 15 模具 1 6，5 6封裝膠體 18 導電性護層16869.ptd Page 16 557519 The height difference between the outer guide leg and the chip holder of the gold wire pad. The height difference between the outer guide leg and the inner guide leg is simple. 110c Upper surface of the inner guide leg 1 3, 5 3 Wafer 131 Wafer non-active surface 1 4, 5 4 Welding wire (gold wire) 150 Mold cavity 17 Grinder 19 Η h Η 'Preset ground colloid thickness 12 Second guide pin 32, 52 Wafer holder 130 Wafer active surface 1 3 2 Wafer pads 15 Moulds 1, 6, 6 Encapsulants 18 Conductive coating
16869.ptd 第17頁16869.ptd Page 17
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| TW091116104A TW557519B (en) | 2002-07-19 | 2002-07-19 | Process for fabricating semiconductor package with lead frame as chip carrier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8232192B2 (en) | 2004-05-05 | 2012-07-31 | Megica Corporation | Process of bonding circuitry components |
| TWI415227B (en) * | 2009-01-06 | 2013-11-11 | Raydium Semiconductor Corp | Chip packaging structure and lead frame |
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2002
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8232192B2 (en) | 2004-05-05 | 2012-07-31 | Megica Corporation | Process of bonding circuitry components |
| TWI415227B (en) * | 2009-01-06 | 2013-11-11 | Raydium Semiconductor Corp | Chip packaging structure and lead frame |
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