TW535107B - Data processing device - Google Patents

Abstract

The invention provides a data processing device that utilizes processor to have fast and efficient calculation processing of huge amount of data as done in computation processing of moving vector test in graphics. It uses the local bus 8 with broader bus width than that of data bus 6 of CPU2 to connect SDMD calculator 4 and work RAM 12 controlled by CPU2, in which SDMA calculator 4, work RAM12 and CPU2 are commonly connected to address bus 10 to have uniform management of SDMD calculator 4, work RAM12 via CPU2 for high speed data processing.

Description

535107 A7 B7 V. Description of the Invention (1) Technical Field The present invention relates to a data processing device, and more specifically, it relates to general use processing such as motion detection, motion compensation processing used for image signal compression and elongation processing. It is a data processing device that performs high-speed and efficient mass data processing. Technical background For video and audio elongation and compression processing, it is necessary to repeatedly perform the same arithmetic processing at a high speed for a large amount of data. For this reason, in the part that performs the same arithmetic processing as described above, a dedicated arithmetic device has been provided, and in order to make the arithmetic device operate at a high speed, it has a plurality of processor elements (processor units) arranged in parallel, and A data processing device composed of a SIMD (Single Instruction Multiple Data) computing device for making these partial operations through the same program has been known. The SIMD computing device is described in the "Interface" document, pages 111 to 113 of March 1998. Specifically, the Pentium MMX technology of Intel Corporation is known. In the SIMD mode computing device, continuously supplying data from the memory to improve the operating rate of the computing unit is an important factor in determining performance. However, a data processing device that combines a conventional Central Processing Unit (CPU) and a SIMD-based processor is connected in the device structure through a common / shell material bus and an address bus. CPU and SIMD computing device. Therefore, it is carried out from the memory to the register in the SIMD computing device (reglSteI *) -4. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) binding

Line 535107 ----------------]! Repair I it Κ]-,! 、 ⑤ ^ _ 5. The data transfer of the invention description (2) is followed by the calculation, and then the operation result in the temporary register is transferred to the memory to start the next data processing operation. In this case, there is a problem that the data used by adjacent processor components cannot be used to improve the operation efficiency. In order to solve the problem, it is conceivable to connect the SIMD computing device and the built-in memory with a system bus and a local bus with a wide independent bus width according to the design method of the large integrated circuit LSI. However, in this way, although the data transfer performance of the SIMD computing device and the memory will be improved, it is not limited to the traffic of the system bus that receives and receives computing instructions from the CPU and the SIMD computing device, which will become a problem. At both ends of the device, an address generator is required, and the CPU cannot manage both the data reading of the memory and the data storage of the SIMD computing device. Therefore, there is a problem that the high-speed performance of the SIMD computing device cannot be effectively applied. SUMMARY OF THE INVENTION The main object of the present invention is to realize a data processing device capable of processing data at a high speed. Another object of the present invention is to realize data reading in a unified management of memory by a central processing device in a data processing device having a computing unit controlled by a central processing device and connected by a memory and a local bus. Data processing device for both data output and data storage of the arithmetic unit. Furthermore, the other object of the present invention is to provide a data processing device for uninterruptedly supplying data to the processor elements constituting the computing unit, not only making every clock operation possible, but also realizing high-speed data processing. This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

In order to achieve the above-mentioned object, the data processing device of the present invention is provided with the following foot structure, an arithmetic unit, which is controlled by a CPU device; a first memory mechanism ', an address sink, and the common connection to the CPU, the arithmetic unit, and the first 1 memory mechanism; and a local data bus (10cal data bus), which has a wider bus width than the data bus width of the above-mentioned CPU, and is combined with the above-mentioned arithmetic unit. In the present invention, since a local data bus is provided between the first memory mechanism and the arithmetic unit, the data transmission performance can be improved, and the control line can be connected to the arithmetic unit from € 1> 11, so that it can be supplied to the arithmetic unit. The flow of calculation instructions from the system bus is independent. Furthermore, for the address bus, in order to connect the CPU device, the arithmetic unit and the memory unit in common, the address generator is preferably provided only in the CPU device, and does not need to be provided in the arithmetic unit. The first memory mechanism is also located in the address space of the CPU with the register of the computing unit. The CPU device can manage the reading of the data of the first memory mechanism and the data storage of the register of the computing unit. Specify the address of the person. According to a preferred embodiment of the present invention, the above-mentioned arithmetic unit is constituted by a SIMD control type arithmetic unit having a plurality of processor elements. Each of the above-mentioned processor elements has a first input terminal, a second input terminal, and an output terminal.歹] The structure of the k · brother 1 register 'its bit width is the total of the bit width of the first input terminal of all processor elements; the second register, its bit width is the total of all processor elements The total of the bit width of the second input terminal; and the third register has a bit width greater than the bit width of the second input terminal of the processor element, and can be used in the second register as the second register. Bit-wide units for data shift 535107 A7 ______ B7 V. Description of invention (4) Bit shift. The data processing device of the present invention is specifically described in the following embodiment, which is effective in the motion detection processing of image encoding processing, and can be applied to a processing device which needs to perform high-speed arithmetic processing in parallel with CPU processing. Brief Description of the Drawings Fig. 1 is a block diagram showing a first embodiment of a data processing apparatus according to the present invention. FIG. 2 is a circuit diagram of the internal structure of the SIMD-type arithmetic unit 4 of FIG. 1. FIG. 3 is an internal configuration diagram of the CPU 2 of FIG. 1. FIG. 4 is an internal configuration diagram of the processor element 38 of FIG. 2. FIG. 5 is an operation explanatory diagram of the SIMD type arithmetic unit 4 of FIG. 2. FIG. 6 is an operation explanatory diagram of the SIMD type arithmetic unit 4 of FIG. 2. FIG. 7 is an explanatory diagram of reference image data used in the first embodiment. FIG. 8 is an explanatory diagram of encoded image data used in the first embodiment. FIG. 9 is an address map on the DRAM 16 of FIG. 1. FIG. FIG. 10 is an address map on the work RAM 12 of FIG. 1. Fig. 11 is a flow chart (flow ehar < t) of the first embodiment. Fig. 12 is an explanatory diagram for explaining data transfer of a register of the SIMD type arithmetic unit 4 of the first embodiment. ° 'Fig. 13 is an explanatory diagram of a calculation range of a vector (0, 0) in the first embodiment. 14 is an explanatory diagram of a calculation range of a vector (1, 0) according to the first embodiment. Fig. 15 is a block diagram showing a second embodiment of the data processing apparatus of the present invention. FIG. 16 is a diagram showing the internal structure of the CPU of the second embodiment. Fig. 17 is an operation flowchart of the second embodiment. This paper size applies to China National Standard (CNS) A4 specifications (210X 297) `` -------

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Line 535107 A7 B7 V. Description of the invention (5) Fig. 18 is a block diagram of the third embodiment of the data processing device of the present invention. Fig. 19 is a block diagram showing a fourth embodiment of the data processing apparatus of the present invention. FIG. 20 is a diagram showing the internal structure of the VPU 160 according to the fourth embodiment. A preferred embodiment for carrying out the present invention < Embodiment 1 > Fig. 1 is a block diagram illustrating a first embodiment of the data processing apparatus of the present invention. The data processing device of this embodiment is a motion detection processor using a block matching method with an arithmetic unit in an image shadow coding process. The former describes the structure of the device, and the latter describes the operation of detecting < movement processing. As shown in the figure, the data processing device has the following: a computing unit 4, which is composed of a central processing device (hereinafter referred to as the CPU) 2 a SIMD calculator directly controlled by control lines 3 and 5; a working random access memory Work RAM 12, which is a memory mechanism; address bus 10, which is commonly connected to CPU 2, computing unit 4, and work random access memory 1 2; and local data bus 8, which has more memory than CPU 2. The bus width of the data bus 6 has a wider bus width, and the arithmetic unit 4 and the working random access memory 12 are combined. The CPU 2 decodes instructions to control the whole. In this embodiment, a RISC type microprocessor is used. 20 is a ROM for storing programs and the like of the CPU device 2, and 18 is a RAM for storing data or programs of the CPU device 2. 12 is a working RAM for temporarily retaining the calculation data of the SIMD type arithmetic unit 4, 16 is a DRAM storing image data, 14 is a DRAM interface of the DRAM and the working RAM 12, and this paper standard applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) 535107 5. Inventive circuit, 22 is a DMA circuit that controls the direct memory access (DMA) transfer of DRAM 16 and work RAM 12. This embodiment has 3 kinds of buses and buses. The bus width of the data bus 6 of the CPU 2 is 32 bits, and the bus width of the address bus 丨 〇 is 32 bits. The data buses 8 and 24 The bus width is 144 bits. The number of oblique lines added to the bus in the figure indicates the bus width (bit width). Hereinafter, the operation of each part structure will be described in detail. FIG. 2 is a circuit diagram illustrating the internal structure of the SIMD type arithmetic unit 4 of FIG. The arithmetic unit 4 is composed of SIMD-controlled arithmetic units with 6 parallel processor elements 3 8, 40, .. 42, and 44; each processor element / has a first input terminal for selection Selector 32 is connected to the register 30; the second input terminal is connected to the register 34; and the output terminal is connected to the data buses 6 and 8. The register 30 has a total bit width of the first input terminal bit width of all processor elements 38, 40, 42, and 44. The bit width of the register 34 is a total of the bit widths of the second input terminals having all the processor elements. In addition, it has the following third register 36: It has a bit width greater than the bit width of the second input terminal of the processor element, and the register 34 has a data unit that can be used as the second input terminal bit width Shift the third register 36. Each processor element 38, 40 ... 42, 44 is controlled by the CPU 2 via control lines 3 and 5. The data supply from the register 30 to the processor elements 38, 40,... 2, 44 can be changed via the selector 32. In addition, the registers 30, 34, and 36 respectively write data from the private lanes 50, 46, and 48 controlled by the address bus 丨 0 through the local data bus 8. Kojima scale suitable for financial and domestic (CNS) M specifications (⑽χ 297 公 董)-一 ~~-

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Line 535107. A7 _____B7 V. Description of the Invention (7) Figure 3 is a block diagram of the Rise microprocessor 2 shown in Figure 1. This structure is exactly the same as the conventional microprocessor, and has the following structure: an instruction decode circuit 58, a fetch circuit 60 from the instruction, and a fetch instruction inputted through the spring 72 and Decode it; the arithmetic circuit 6 4 ′ executes the instruction 6 8 from the instruction decoding circuit $; a program counter 54; and a general purpose register 56. In addition, for example, in the instruction encoding circuit 58, for the operation instruction of the SIMD type arithmetic unit 4, the active signal line 3 is activated; for the simd type operation difference, the result of the reading is 4. The instruction sentiment is the activation signal line. $. 6 6, 6 8, 6, 2, 7, 3 and 74 are command and data transmission lines. FIG. 4 is a structural block diagram of the processor element. The structure of the 16 processor elements 38, 40, 42, 44 of the SIMD type arithmetic unit 4 is exactly the same. Here, as an example, the processor element 38 will be described as an example. The processor element 38 has the following structures: a register 82 for holding the operation results of the arithmetic circuits 80 and 81; and a readout control circuit for controlling the local shell material bus 8 or the data bus Read out of 6. In the operation circuit 8 0, the 9-bit part of the I44 bit width of the register 30 is input via the bus 37, and the register of 44 bits The 9-bit part of the bit width is input through the bus 35. The two types of input data are calculated (subtracted) in the arithmetic circuit 80, and the output of the arithmetic circuit 80 is in the arithmetic circuit. The value of 81 and the register 82 are added. The operation result of the arithmetic circuit 81 is stored in the register 82. Fig. 5 and Fig. 6 are diagrams illustrating the connection form of the selector 32. In the first connection form, it is like As shown in Fig. 5, the most -10- bits of 144 bits from register 30

535107 A7 _____B7 V. Description of the invention (8) The upper bit supplies 9 bits a 0 to each processor element 3 8, 40 ... 44, 42 in common. In the second connection mode, as shown in FIG. 6, the entire contents of the register 30 are 144 bits, and from the upper part, 9 bits a0, a2,.. .4, and al5 are respectively supplied to Processor elements 3 8, 4 0 ··. 4 4, 4 2 Accordingly, as shown in the figure, the 9-bit data of a 0 is allocated to the processor element 38 of 0; the 9-bit data of a 1 is allocated to the processor element 40 of 1 data. Next, the above-mentioned data processing device will be used to explain the processing of the detected image motion in the image signal encoding process using the MPEG 2 standard. Image motion detection using the MPEG 2 specification is compared with a giant data block encoded in units of macroblocks (horizontal block) of 1 $ pixels horizontally and 16 pixels vertically. With reference to the reference picture, the position of the most similar giant data block is obtained in the search range, and the process of obtaining the image frame distance between the two giant data blocks is performed. Generally, motion detection is performed by a data block matching method. The so-called data block matching method is to make the absolute value of the difference between the reference image pixels corresponding to the encoded image pixels, cumulatively add all the pixels in the giant data block, and find the minimum value of the cumulative added value. The processing of the location of the value huge data block. Fig. 7 and Fig. 8 respectively illustrate pixels of a reference image data and a coded image of a giant data block when the image is coded. Here, the reference image data is assumed to be 352 pixels in the horizontal direction and 240 pixels in the vertical direction. In the figure, marks ^, ra2 ... rbl ... rbl7, etc., which are surrounded by circles, are marks for identifying pixels. Also, the giant data block, -11-

535107 A7 B7

The horizontal direction is 16 pixels, and the vertical direction is 6 pixels. In the figure, the marks tal, Ou Dau, etc. surrounded by circles are the marks to identify pixels. FIG. 9 illustrates data stored in the DRAM 16 of FIG. 1. The symbols ral, ra2,... M..., Α8, etc. in the figure represent pixels corresponding to the symbols shown in FIGS. 7 and 8. The address A000 is allocated to the reference image data area σ, and 4 pixels in the horizontal direction are stored in the 32-bit width of the ϋ DRAM 16. The address B000 is allocated to the huge data block, that is, the encoded image data area. FIG. 10 illustrates the encoded image data and the reference image data stored in the work RAM 12. Here, the slave address C000 is allocated to the reference image data area. Each pixel data is 9-bit data, and among the 144 bits starting from the address c00, 16 horizontal pixel data from the pixel ral to the pixel ral6i are stored. The slave address D000 is an area allocated to coded image data. As in the case of the reference image >, in the 144 bits of the address D00, 16 horizontal pixels from the pixel tal to the pixel tal6 are stored. Figure 11 1. The above; the flow chart of the movement detection process of the shell processing device. 0 First, the DRAM 16 data (Figure 9) is transferred to the working RAM 12 via the DRAM interface 16 (steps). , 90). At this time, at every! The sign bit is added to the 8-bit data of each pixel to perform the sign extension of the 9-bit data of each pixel. Four long word data are juxtaposed on the DRAM 16 to generate 144 bit data. Repeating this transfer, data is stored in the work RAM 12 via the bus 24. Next, the reference image data is transferred from the work RAM 12 to the register 34 of the SIMD processor 4 via the local data bus 8 (step 92). -12- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X 297 mm) V. Description of the invention (10) Figure 12 is a detailed operation diagram for explaining step 92, which is based on time The relationship between the 16 processor elements 38, 40,... 42, 44 = H4 bits of register money, register B34, register ⑶ signal = ON. That is, the figure is not at the time shown in the vertical direction (and the contents of the registers 30, 34, 36 at this time change. As in the previous example, the register A30 stores the image that must be encoded The multi-pixel material, the top 9 bits of the-even_bit column are commonly supplied to all the processor elements 38, 40 ... 42, "; stored in the register β34, there is a reference like Multiple pixels: the upper 9 bits are supplied to the processing element 38, the next 9 bits are supplied to the so-called processor element 40, and the land is supplied to other processor elements every 9 bits. Store, register, = Shift data to supply to register B34. Shift in 9 bits; brother, temporarily store as C36 upper 9 bits supply to lower register B34 It can be understood here that at time t = 0 (step 92), the reference image data from the register B34 to the pixel ral to the pixel ral6 are transmitted with a width of 144 bits at a time. Sihai] At t 1 (step 9 4), the data is transferred from the working ram 12 to the temporary register C36. As a result, the reference image data pixel ral7 to pixel ra32 are re-width by 144 bits It is transmitted to the register c36. As a result, the reference image data of the 3 horizontal pixel lines is stored across the register B34 and the register C36. At time t = 2 (step 96), the work RAM 12 To register A30, one time transfer from the pixel tal of the giant data block of the encoded image data to the pixel "M of -13-this paper size is suitable for financial purposes 97 public love) 535107 A7

This paper size 逋 财 a _ (CNS) A4 size (210 X 297 public love)

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Data transfer of 3 registers 30, 34, 36. First, at time _ step 104), the data is transferred from the work RAM 12 to the register B. (At the time of step α, user 20 (step 106), the data is transferred from the work RAM 12 to the temporary storage 36. As a result, the state at the time t = 20 between the time when the map 2 is formed, and the previously transported line is <line The reference image data of the next line is stored across the register 34 and register 36 from the pixel here to this h. At time t = 21 (step 108), the data is transferred from the work RAM 12 to the temporary Register A. As a result, the encoded image pixels of the line from the previous calculation to U16 are stored in register A ^ 3 registers 30, 34, and 36 all store the shell material. Then, Same operation is performed. This action is repeated for 6 lines. "As a result, the register 8 2 inside the processor element 3 8 stores the cumulative addition value of the absolute value of the difference between all the pixels. This value is The result of the block matching operation of the vector (0, 0) in Fig. 3 is the degree of approach corresponding to the vector (0, 0). 'On the other hand, temporarily inside the processor element 40 The memory 82 stores the result of the data block matching operation of the vector (1, 0) in FIG. 14. Similarly, i 6 processor elements 3 8 ··· 4 4 may The data block matching operation result of 16 motion vectors is obtained at this time. In this embodiment, from the working RAM 12 to the SIMD arithmetic unit 4, a large amount of data can be transmitted at the same time without system data 8 through the data processing device, @ 时No address generator is set in the SIMD computing unit 4. Through the address management of the CPU 4, the data transfer between the working RAM 12 and the SIMD computing unit 4 can be managed in a unified manner. Based on this, the data can be matched to map Image processing -15- This paper size applies Chinese National Standard (CNS) A4 (210X 297mm) 535107

Using the same instruction to detect the same number of operations, it becomes effective for necessary data processing. &lt; Example 2 &gt; The construction block of the second embodiment of the data processing device of the second and second inventions 13 (1): I added a second SIMD operation I to the data processing device of FIG. 1. Two Γ is left here, and the control from the CPU 131 is added. The internal structure of the line 134 and a second SIMD calculator 130 is the same as that shown in FIG. 2: the same corresponding structural elements are attached with the same numbers, and their explanations are explained here. The same parts as in FIG. 1 are also attached with the same numbers to omit description. FIG. 16 is a block diagram illustrating the structure of the CPU 131 of the second embodiment (FIG. 15). The structure of the CPU 131 is different from that shown in FIG. The CPU 2 shown in the example embodiment is added with a control line η] *. From the instruction encoding circuit 133, which is essentially the same as the CPU 2. The control lines 132 and 134 are used to control the second SIMD operation. 130 is a processing flowchart illustrating the operation of the data processing device of the embodiment 2. In the embodiment 2, the operation of storing data in the three registers of the SIMD calculator 4 is easy to say, Action of transferring data from DRAM 16 to work ram 12 (step 90), so as to edit data from work ram 12 The image data is sent to the operation of the register A (step 96 mule), identical with the one shown in FIG Shu portions of the same step number of mules.

After step 96, in the case of this embodiment, the data is stored in a register of the SIMD calculator 130. Initially, the reference image data is transferred from the ram 12 to the register B (step 140). Secondly, from the working RAM -16- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 535407 A7 B7 :; year il V. invention description (14) 12 transfer the reference image data to Register C (step 142). Finally, the encoded image data is transferred from the work RAM 12 to the register A (step 144). Then, in the same manner as in the case of the embodiment .1, an operation using a processor element (PE) is performed. As a result, 3 or 2 processor elements can be used at the same time to perform data block matching of different vectors, which can be processed at a higher speed. &lt; Embodiment 3> Fig. 18 is a block diagram illustrating a third embodiment of the data processing apparatus of the present invention. In this embodiment, there are two working RAMs 144 and 146, which can be switched between the DRAM 16 side and the SIMD computing unit 4 side. Data is stored in the work RAM 144. When the SIMD calculator 4 is used for signal processing, the work RAM 144 is connected to the SIMD calculator 4 via selectors 142 and 152. On the other hand, the work RAM 146 is connected to the DMAC 122 side via the selectors 148 and 150. Then, in the work RAM 146, the DMAC 122 is transferred from the DRAM 16, and the SIMD calculator 4 transfers image data used next. Here, the signal processing of the SIMD calculator 4 in the work RAM 144 is completed, and the work RAM 144 and the work RAM 146 are switched. In other words, the work RAM 144 is connected to the DMAC 122 side, and the work RAM 146 is connected to the SIMD calculator 4 side. With this structure, the used data is transferred from the DRAM 16 in the working RAM 146, so the SIMD computing unit 4 can immediately start the computing operation. Accordingly, the operation efficiency can be improved. &lt; Example 4 &gt;

Fig. 19 is a diagram showing a fourth embodiment of the data processing apparatus of the present invention. In this embodiment, the data processing device of the present invention is constructed in the image signal compression LSI -17- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Among those. To the busbar 84 of the M processor element 166, various structural element blocks are connected. The building element block includes: a communication interface 168, which has an interface function with an external modem (modem); an audio (audi0) interface, which has a function of inputting and outputting external audio signals; and a video interface Block 172, which has the function of inputting and outputting with external image signals; Variable-length marshaling and de-mapping block 164, which is responsible for encoding and decoding of variable-length symbols; Q-DCT / IQ-IDCT block 162, which is responsible for Quantization, inverse quantization, DCT, inverse DCT processing, DRAM control block 174, which is responsible for the control of DRAM 176, and motion detection block 160. The motion detection block 60 is the same as that described in the previous embodiment. In this embodiment, compared with the device shown in FIG. 丨, the point where the DRAM 176 corresponding to the DRAM interface 14 and the DRAM 16 is outside B, and the Mpu 166 has a control temporary storage for the control action detection block ι60 Register (c0ntr〇i register) 185 is different. Via the control register 185, the CPU 180 of the motion detection block 160 can be controlled. A description will be given of the operation when the image of this structure is compressed. The encoded image data input via the video interface block 172 is temporarily stored in the dram 176. Then, "疋" reads the working ram of the motion detection block 1 in units of giant shell blocks. At this time, the reference image data of the corresponding search range is also read into the work RAM of the motion detection block 160 at the same time. As explained in the first embodiment, the cumulative addition of the absolute value of the difference between the respective motion vectors is performed. After all the vector operations are finished, the vector with the smallest difference absolute value is used as the motion vector relative to the child data block. Then, use the coded image at this time -1 8-I Paper Size Applicable Towels ® Household Material (CNS) A4 Specification (21GX297 mm) —

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The difference value of each pixel corresponding to the reference image, and the result is sent to the Q_DCT / IQ-IDCT block 164. In the Q_DCT / IQ_IDCT block 164, the DCT processing and quantization processing are performed on the result sent from the slave detection block 160, and it is sent to the pico-length encoding and decoding block 164. Here, a variable-length encoding process is performed, and the compression process of the image data is ended. As described above, by applying the present invention to an image signal compression LSI (Large Integrated Circuit), it is possible to construct a high-performance image signal compression LSI with high programmability. Industrial applicability As explained in the above-mentioned embodiment, the present invention can continuously supply data to the processor elements constituting the SIMD type arithmetic unit. In particular, it can improve a large number of arithmetic operations for repeatedly compressing and extending image signals. Operational efficiency in signal processing. Component symbol description 2 Central processing device 3 Control line 4 Computing unit 5 Control line 6 Data bus 8 Local bus 10 Address bus 12 Working random access memory 14 Working dynamic random access memory 16 Dynamic random access memory -19- This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 535107 A7 B7 V. Description of the invention (17) 18 Random access memory 20 Read-only memory 22 Direct memory access Circuit 24 bus 3 0 register 32 selector 34 register 3 6 register 3 8 processor element 40 processor element 42 processor element 44 processor element 46 socket circuit 48 write circuit 50 write circuit 54 Program counter 56 Universal register 5 8 Instruction decoding circuit 60 Instruction fetch circuit 62 Instruction and data transmission line 64 Operation circuit 66 Instruction and data transmission line 68 Instruction and data transmission line 72 Line-20- This paper is applicable to China Standard (CNS) A4 specification (210X 297 mm) 535107 A7, B7 V. Description of the invention (18) 7 3 Command and data transmission line 7 4 Command and Material transfer line 8 0 arithmetic circuit 8 1 arithmetic circuit 82 register 8 4 read control circuit 122 direct memory access circuit 13 0 second SIMD arithmetic unit 13 1 central processing unit 132 control line 133 instruction decoding circuit 134 control line 142 selector 144 working random access memory 146 working random access memory 148 selector 15 0 selector 1 52 selector 1 60 motion detection block 1 62 Q-DCT / IQ-IDCT block 164 variable length coded block 166 Microprocessor component 16 8 Communication interface block 17 0 Audio interface block -21- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 535107 A7 B7 V. Description of invention (19) 172 Video interface block 174 dynamic random access memory control block 176 dynamic random access memory 180 central processing unit 1 84? Bus 18 5 control register -22- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 (Mm)

Claims (1)

535107 Αδ Βδ 1. A data processing device, which has: w-.._ 运 1 is different from each other and controlled by the cpu; brother 1 memory mechanism; local data _, | needle bus, has a data bus that is higher than the above cpu — The width will be more broad. The bus width is wide, and the above-mentioned 1st arithmetic unit is connected with the above-mentioned first hidden mechanism; and the address bus is connected with the above-mentioned CPU and the above-mentioned first line. Miao Yilian was connected to the above-mentioned first memory mechanism in common. 2. According to the information in item i of the patent application scope 心, scallop processing device, in which the first operation unit is a SIMD type arithmetic unit. 3 :: Please request the data processing device of item i of the patent scope, in which the above-mentioned industrial operation unit is a plurality of parallel configuration. 4 · If the scope of patent application is the first! The data processing device of item, wherein the U memory unit has: a first memory; a second memory; and a read eight circuit, which is connected to the address bus and the data bus, and is controlled in the first memory and Data transfer between 2nd memory. 5. If the data processing device of the 3rd or 4th in the scope of patent application, the above-mentioned 11th memory device has: from the second memory to the i-th memory, the symbol expansion is performed when transferring by the DMA circuit Institution. 6. The data processing device according to item 4 of the scope of patent application, wherein the first memory has first and second work memories; the above-mentioned memory mechanism has the ability to switch the first and second working memories alternately. A mechanism for connecting a body to the above-mentioned first and arithmetic units and a connection to the above-mentioned second memory. 7. The data processing device according to item 1 of the scope of patent application, wherein the above-mentioned first operation unit '疋 is a SIMD control type arithmetic unit which processes and processes multiple data in parallel with a single instruction from the above-mentioned CPU. -23- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 8, = data processing device in the scope of application for item i, in which the first operation list 疋 is composed of the following: A plurality of processor elements have a first input terminal, a second input terminal, and a first output terminal, and are actuated by the control signal from the CPU; the i-th register, whose bit width is 3, is: The sum of the bit widths of all the i-th input terminals 疋; the second temporary ::: whose bit width is all the 2nd inputs of the above-mentioned multiple processor elements: = total of width 'and in a way that all bit widths will not overlap Plus] the second input terminal with the processor element; the third register, which has the bit width of the second input terminal bit width of the processor element or more, and the ::: input terminal bit width The unit shifts data in the second register. The selector can select the resources of the above ^ register and supply it from the i-th input terminal bit width of the highest-order processor component to all of the above. The 丨 round entry &gt; sub-write control circuit of the processor element is derived from the above address pool It is controlled in a row, and the data is written to the first, second, and third temporary storage states respectively through the above-mentioned local area; and the SIMD control type arithmetic unit has the data output of the above output terminals Circuit to the local data bus described above. 9 · If the data processing device for image processing of item 8 of the patent application scope, the processing element described above is within a certain range, and the above-mentioned (division 2 input Sakiko <data subtraction value and output to the calculation circuit The multiple pixel data of the 5 images must be stored in the above! Register, and 1 test (the multiple pixel data of the reference image is stored in the second temporary store and the output of the multiple processor elements is taken as ㈣ The multiples of the motion vectors correspond to the degree of approximation. -24- 535107 VI. Patent Application Fanyuan10 · A SIMD control type arithmetic unit, which has the following ... Multiple processor elements have a first input terminal , The second input terminal and the first output terminal; The first temporary storage benefit, whose bit width is the total of the bit width of all of the above-mentioned multiple processor elements' input terminals; the second temporary register, the bit width The width is the total of the bit widths of all the second input terminals of the f processor elements; and the third register, which has the bit width of the second input terminal of the processor element or more, is greater than and equal to The register is based on the second input terminal The data is shifted by the unit of width. Η · For example, the SIMD control type arithmetic unit of the patent application scope No. 10, among which the first register is provided with the following ... The above processing is prepared from the most significant bit The bit width of the first input terminal is commonly supplied to the connection circuits of all the processor components mentioned above; and the connection circuits of all the bit widths are supplied to all processor components in a non-overlapping manner. The SIMD-controlled arithmetic unit of the range item 丨 0, wherein the first register has the function of supplying the bit width of the first input child of the above-mentioned processor element from the most significant bit to all the above-mentioned processor elements. Alternatively, each clock pulse is used to perform arithmetic processing on the processor element, and in the first register, data shift processing is performed in the bit width unit of the i-th input terminal of the processor element, and The second register and the third register are a mechanism for shifting data in 7G wide units of the second input terminal bit of the processor element. 13 ·, according to the patent, the 11th or 1st scope of the patent is requested. SIMD of 2 items A shape arithmetic unit is used for image processing; a plurality of pixel data of the i-th image are stored in the i-th register; and the second and third registers 25- Paper standard suitable for aa home standard 297 public [535107 A8 A plurality of pixel data of the second image are stored therein; the processor element is composed of an arithmetic circuit that accumulates a difference between data applied from the first input terminal and the second input terminal. Each of the material elements outputs a mechanism of an approximation degree corresponding to a plurality of motion vectors between the image and the second image. 14. A data processing device comprising: a CPU; a first operation unit; a memory mechanism; a connection between the above-mentioned coffee unit and the above-mentioned memory mechanism "address bus; and a local data connection connecting the above-mentioned operation unit and the above-mentioned memory unit It is characterized in that the above-mentioned CPU has an instruction decoding circuit for decoding instructions, which controls the first operation unit with the output of the instruction decoding circuit, and the local data bus has a wider bus width than the CPU . 15. The data processing device according to item 14 of the scope of patent application, wherein the i-th operation unit is a SIMD type arithmetic unit. 16. A data processing device, characterized by having the following: a CPU; a first operation unit controlled by the CPU; a memory mechanism connected to the CPU by an address bus; a DMA circuit connected to the address bus It is connected with the above-mentioned memory unit; and the local data bus has a wider bus width than the data bus width of the above CPU. 17. The data processing device according to item 16 of the scope of patent application, wherein the first operation unit is a SIMD type arithmetic unit. 18. A data processing device, characterized in having the following: a first memory for storing instructions; a CPU, which is connected to the above-mentioned first memory through an address bus and a first data bus; and a second Memory, using the above address -26- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 535107 AB c D ~, patent application range stream to connect with the above CPU; and computing The unit is connected to the second memory through a second data bus; and the second data bus has a wider bus width than the first data bus. 19. The data processing device according to item 18 of the scope of patent application, wherein the above arithmetic unit is a SIMD type arithmetic unit. 20. For example, the data processing device of claim 18 or item 19 has a DMA circuit, and the DMA circuit is connected to the address bus and the first data bus and the second memory. -27- This paper size applies to China National Standard (CNS) A4 (210X297 mm)