TW531878B - Bar circuit for an integrated circuit - Google Patents

Abstract

The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in the semiconductor substrate; and a strip of second well with the second conductivity type in the semiconductor substrate. The strip of second well is located below and adjacent to the strip of first well, whereby forms a junction barrier for reducing the cross talk and the eddy current.

Description

531878

5 -1 Field of Invention ... The present invention relates to a blocking circuit (ba): CU 11 of an integrated circuit, and particularly to a blocking circuit of a chip i inductor circuit. 5-2 Background of the Invention: = Body Circuit The components are designed to reduce the size, and the requirements of different types of two- and two-body circuit wafers are also increased. "For example, if the corpse has become a high-occupancy consumer product, the result is 0. —Hertz (1 ~ 2 GHz) frequency range operation; ： Requirement: ： 1 page front-end circuit to high-capacity silicon integrated circuit process circuit wafer. In the absence, the frequency is combined to the same integrated circuit with 4 power f has 5 quality factors (high_my fact0rs, 1, there are still problems with right stems that are difficult to be overcome. People have made a lot of efforts in silicon, and process technology produces losses such as inductors. Frequency), everyone knows Thing. In the connection to Shi Xi

In the bulk circuit technology, high quality coefficient inductors are integrated but have a quality coefficient ranging from 3 to 8 at most; the problem of using silicon is partly because the field frequency of the silicon substrate causes the field frequency to approach the self-resonant frequency (sel f _res. The nant inductance value will decrease accordingly. This is the inductor lost in the conductive silicon substrate. The stray capacitance of the substrate can have a relatively large value and the conductor.

531878

increase. Therefore, the direction of efforts is to provide a silicon substrate withered + 3 out-grooves, which will be surrounded by oxide, in the form of a spiral π; "j: inductors. The advantage of the above approach is that these oxidized inductors are The insulation structure is separated from the metal layer, but: In any case, it is too much for the CM0S system, which is a new year's eve basement structure. Fork and middle, and the 2 to 4 level junctions are shown in the first figure, The overall mode 9m0n0l inductor? (.N —CMP indUCtr)-general circuit mode intrinsic inductor (parasitic inductor) ... is parasitic; "not parasitic capacitance"; thought on the chip = on (capacity; Cox is the resistance between the inductor on the wafer and the substrate. Quot. Yi ρ-the resistance of the parasitic electric pseudo-eddy current part; Material; y: lost. When the change is made, and then the eddy current generated in the substrate is induced, the magnetic flux is generated. The body is also regarded as an energy container. Energy loss, equivalent to the coefficient of quality current producing cross talk of the inductor meaning substrate p cattle low. Also, via l will happen. 1 shows that the m-ring uuard should; however, the current still exists ’and =; = =

Page 6 531878

^ "Metal shield" can also be used to reduce thirst current, but it will sacrifice inductor performance. 5-3 Purpose and summary of the invention: _, In the above background of the invention, the present invention mainly provides an integrated circuit: L: circuit 'This blocking circuit utilizes the increase-the resistance of the semiconductor substrate reduces the y 9 effect and reduces the Eddy currents induced by inductors of integrated circuits are another object of the present invention. Caused by less semiconductor substrate in a semiconductor substrate

The purpose is to provide a block of electricity in a circuit on a chip. A long deep well below a generally long well can reduce electromagnetic interference (EMI) effects. According to the above-mentioned purpose #, the present invention provides a reduction of integrated circuits = one day of fross talk and one of eddy current to block electricity, and the blocking circuit includes:-the-conductive conductor One of the second conductivity-the first-long well in a half-nano good-eight have one of the first conductivity. The second long well is in semiconductor two: the neighbor; the long well, and the first long Wells open-Connect barriers to block crosstalk and eddy currents. W1878 V. Description of the invention (4) The person of the present invention should have some understanding. It is permissible if the law is not limited to explain the invention. Some scales and descriptions of Chu are based on having a clear understanding of what ’which may be included in manufacturing actual and height. : t While implementing the detailed description of the examples, understand that the invention in this field does not depart from the scope of the proposed patent to request the structure or method to be disclosed. . Circuits and illustrations are only examples, not limiting the scope of the invention. :: body, the different parts of the column have not been exaggerated according to the size of the edge map, and related scales, to improve the understanding of the light ... buh, though: ;; the month and depth are displayed in two dimensions at different stages: ;;;; ;: The area shown is just the two inductor circuits on the chip: :: Toast is an element arranged in a three-dimensional space. Relatively: For the%, the illustrated area has a three-dimensional length and width. The main purpose of the present invention is to provide a reduced integrated circuit taU) = current (eddy — "of; ^ ClrCUlt) 'The blocking circuit includes: Has a first conductivity: t-conductor substrate; an inductor element on the semiconductor substrate; has a second = the number of electrical properties, the third = long well in the semiconductor substrate and the inductor element base bismuth :; A has a plurality of second strip wells having a second conductivity at I ^ body strip wells below the -strip strip wells, and the same. At a glance to form-connect barriers to block crosstalk and eddy currents

Page 8 V. Invention description (5) = The embodiment will be added with reference to the following diagrams: = 1 A schematic diagram of the front view, which is used to explain the integrated circuit of the inductor integrated circuit according to the present invention a: month f has a chip, Doped or non-doped Shi Xi, or germanium on the conductor substrate 12, there are Ruoqianji ruler Guigui Temple 4, in the half Λ. T dry strip well 14. It is particularly emphasized that the arrangement of this stripped well is not limited to the second u-length form. Any arrangement on the semiconductor substrate 12 τ τ ^ forms a flat cicada-type electricity $. . iβ forms an electrical layer, which is transferred to recognize the ΐ benefit 16; of course, the geometric makeup of the inductor is not limited to the shape shown in the figure. "咴 υ is not shaped like a towel. H — The picture is the second section with 2 _2 as a tangent to the cross-sectional audio chart. For the sake of explanation, Qiu Bazhan * 5 Ding ... In the semiconducting substrate "! V Niuya is not shown in the figure, and the Carmo Carving II / is a spiral inductor 16. In the first embodiment, the + conductor substrate 12 is a P-type silicon substrate. 。The name is Dao Guang ^ 〇 mountain, but also WY 414 PH AM ^, the substrate in the neodymium body substrate K strips,: ,,. The key is that under the strip wells 14 Length: There are several long deep wells 15 adjacent to the well 14; long, (juncti〇 ^^ I), /. The depth of the long deep well 15 is about a, ^ m below the surface of the semiconductor substrate 12 Furthermore, the 'long strip well 14' can be connected to an external high voltage (Vdd) or a floating state. The field spiral inductor Is 1 6 will generate a change in magnetic flux in the operation mode, and the semiconductor substrate 1 2 An eddy current is generated. The long deep wells 15 and 531878 and the description of the invention (6) ^ The wells 4 and the semiconductor substrate 12 and the IV can block the formation of the spiral type and the long deep wells 15 in this operation. It can further eliminate the possibility of occurrence through the semiconductor substrate 12. The eddy currents induced by the matched PNP connection resistance inductor 16 are increased to increase the impedance of the semiconductor substrate 12, / Cross-talk (cr0ss taik) in the base layer area 12 reference / f ^ from the figure as early as the second embodiment of the structure of the present invention. The semiconductor bottom of a long p well " Well 14 is in a floating or floating state. "The second picture of the second low-voltage (Vss) connected to the outside is doped with N-type ions in the third twelfth embodiment of the present invention. P-type ion of semiconductor substrate. And in the third: each ": the long well 14 is mixed with different concentrations, which can also block the spiral inductor " cry, in the example is to form the N-p-N connection barrier crosstalk effect; long The wells can reduce the induced eddy current and reduce the state. To external low voltage (Vss) or floating

The second diagram D is a schematic diagram of an embodiment of the fourth material 12 doped with N-type ions and long steam. P-type ions at semiconductor bottom concentration. Long well ^ / 1 5 and long well 1 4 are mixed with 18 and can be connected to the external ^ electricity 1 another long N well 18, PNP connection barriers in long N wells ": d ) Or floating sadness. According to the present invention, the connection barrier can block the spiral type electrical

Page 10 531878 V. Description of the invention (7). The thirst current induced by the sensor 16 and reduce the crosstalk effect. In this way, the energy of the inductor will not be consumed in the semiconductor substrate; further, the structure of the present invention can improve the coefficient of quality and reduce the noise in the semiconductor substrate. In particular, it is emphasized that the long deep well of the present invention can also be used for RF and mixed mode products without the advantage of increasing the complexity of the process. The present invention provides a deep well structure in an integrated circuit having an inductor on a chip. The long deep well improves the quality coefficient of the integrated circuit by blocking the induced eddy current and reducing the crosstalk effect through the deep region of the semiconductor substrate. In this way, the overall performance of the integrated circuit can be increased accordingly. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 531 878 Brief description of diagrams The first diagram is a schematic diagram of some equivalent circuits for explaining one embodiment of the prior art. The second figure is a schematic diagram of a part of the front structure of an embodiment of an integrated circuit having an inductor on a chip according to the present invention. The third A to D diagrams are schematic cross-sectional views of various structures according to the second figure 2-2 tangent line. Main symbols: 12 Semiconductor substrates 14 Long wells 1 5 Long deep wells 16 Spiral inductors 17 Long P wells 18 Long N wells

Claims (1)

531878 VI. Scope of patent application 1. A blocking circuit (bar circuit) for reducing integrated circuit crosstalk (cr osta 1 k) and eddy current, which reduces the resistance of integrated circuit crosstalk and eddy current The cut-off circuit includes: a semiconductor substrate having a first conductivity; a first strip well having a second conductivity in the semiconductor substrate; and a second strip well having the second conductivity In the semiconductor substrate, the second elongated well is below the first elongated well and adjacent to the first elongated well, thereby forming a connection barrier to block the crosstalk and the eddy current. 2. If the first circuit of the patent application reduces the crosstalk and eddy current blocking circuit of the integrated circuit, wherein the first conductivity is opposite to the second conductivity 3. If the first product of the patent application is reduced Block circuit for crosstalk and eddy current of the body circuit, in which the above-mentioned first long well can be connected to an external voltage. 4. For example, reduce the blockage of crosstalk and eddy current of the integrated circuit for the first item of patent application scope. Circuit, in which the above-mentioned first long well can be in a floating state (floating) 〇5. Reduce crosstalk and eddy current of the integrated circuit, such as the first item in the scope of patent application Page 13 531878 6. The patent application scope of the blocking circuit, wherein the second strip well has a dopant concentration different from that of the first strip well. 6. The blocking circuit for reducing crosstalk and eddy current of integrated circuit, such as the first item in the scope of patent application, wherein the above integrated circuit includes at least one on-chip inductor on the first long well. square. 7. The blocking circuit for reducing the crosstalk and eddy current of the integrated circuit according to item 1 of the scope of the patent application, further including a third strip well having one of the first conductivity and the first strip well. 8. If the integrated circuit reduces the crosstalk and eddy current blocking circuit in item 7 of the scope of the patent application, the third long well can be connected to an external voltage. 9. The blocking circuit for reducing crosstalk and eddy current of the integrated circuit according to item 7 of the scope of patent application, wherein the third long well can be in a floating state. 1 0. A blocking circuit (bar circuit) for reducing crosstalk and eddy current of integrated circuit, the blocking circuit for reducing crosstalk and eddy current of integrated circuit includes: A semiconductor substrate having a first conductivity; an inductor Is element on the semiconductor substrate; a plurality of first elongated wells having a second conductivity on the semiconductor substrate Page 14 531878 VI. In the patent application material and below the inductor; and the plurality of second strip wells having the second conductivity are in the semiconductor substrate, and the second strip wells are in the Below the first long well and adjacent to the first long well, a connection barrier is formed to block the crosstalk and the eddy current. 11. The blocking circuit for reducing crosstalk and eddy current of integrated circuits according to item 10 of the scope of patent application, wherein the above-mentioned first conductivity is opposite to the second conductivity. ❹ 1 2. If the integrated circuit reduces the crosstalk and eddy current blocking circuit in item 10 of the scope of the patent application, the above-mentioned first long wells include a plurality of third long wells in the first In a long well. 1 3. The blocking circuit for reducing crosstalk and eddy current of integrated circuits according to item 12 of the scope of patent application, wherein the third long wells described above have the first conductivity. 1 4. The blocking circuit for reducing crosstalk and eddy current of integrated circuit according to item 10 of the scope of patent application, wherein the second long wells are located at a distance greater than 3 from one surface of the semiconducting H body substrate. A depth of microns. 1 5. The blocking circuit for reducing crosstalk and eddy current of integrated circuit according to item 10 of the patent application scope, wherein the second long wells mentioned above have a dopant concentration Page 15 531878 VI. The scope of patent application is larger than those of the first long well. «Page 16