[go: up one dir, main page]

TW527672B - Stacked semiconductor device and method of manufacture - Google Patents

Stacked semiconductor device and method of manufacture Download PDF

Info

Publication number
TW527672B
TW527672B TW091102334A TW91102334A TW527672B TW 527672 B TW527672 B TW 527672B TW 091102334 A TW091102334 A TW 091102334A TW 91102334 A TW91102334 A TW 91102334A TW 527672 B TW527672 B TW 527672B
Authority
TW
Taiwan
Prior art keywords
semiconductor
semiconductor wafer
substrate
patent application
item
Prior art date
Application number
TW091102334A
Other languages
English (en)
Inventor
Chung-Che Tsai
Wei-Heng Shan
Huan-Ping Su
Original Assignee
United Test Ct Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Test Ct Inc filed Critical United Test Ct Inc
Priority to TW091102334A priority Critical patent/TW527672B/zh
Priority to US10/170,665 priority patent/US6709894B2/en
Application granted granted Critical
Publication of TW527672B publication Critical patent/TW527672B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

527672 五、發明說明（l) 【發明領域】： 本發明係有關一種半導體封裝件製法及其結構，尤指 一種批次（batch )疊晶之半導體封裝件製法及其結構。 【發明背景】： 現今之電子產品為符合高性能及多功能化之發展需 求’須朝向高度集積化（High Integration )之方向開 發。亦即須將數量更多之電子元件（Electronic Compnents)安置到一定尺寸之半導體晶片上。惟高度集 積化之半導體晶片在製造上須具備精密的整合技術，故就 現有製程觀之實有其製程上之限制。遂有多晶片半導體裝 置應運而生。
多晶片半導體裝置主係於一晶片承載件，如基板或導 線架等上黏置以二堆疊方式相接之半導體晶片所構成之封 裝結構。惟是種疊晶型半導體封裝件之製法如第“至4(：圖 所示，係先將複數片第一半導體晶片2 2 (以下稱作第一晶 片2 2 )黏置於一晶片承載件2 〇上，並以多數第一銲線2 3銲 連各第一晶片2 2至晶片承載件2 〇上使二者間形成電性藕接 關係；而後’於該第一晶片2 2上逐一塗佈如銀膠或環氧樹 脂（Epoxy)等膠黏劑212(Adhensive)以供複數片第二 半導體晶片25 (以下稱作第二晶片25 )疊接，使晶片承載 件2 0上形成二堆疊晶片結構，最後銲接多條第二銲線2 β電 性連接該第一晶片2 5與該晶片承載件2 〇，並施行模壓，植 球及切單作業，即能製得多數疊晶型半導體封裝件2。 然而，上揭製法中該第二晶片25欲接置第一晶片22構
16576.ptd 第7頁 527672 五、發明說明（2) 成疊晶結構時，必須仰賴一佈膠技術方能於第一晶片2 2之 電路表面上形成膠黏層21 2供第二晶片25穩固接著。傳統 佈膠方法係採戳印（Stamping)或點膠（Globing)等方 式，將一内充膠劑之針具27 ( Syringe)配合晶片承載件 2 0輸送方向往復移動，當針具2 7滑移到第一晶片2 2上方 設位置時，著即吐膠以便在各第一晶片22之電路表面上 ，膠黏劑2 1 2。惟此種佈膠方法對準晶片承載件2 〇上每一 ，二晶片22逐一塗佈膠劑，極為耗時而難以成批 葙H同日ί，每片晶片逐一塗膠亦會明顯拖長封裝時 設備品產量明顯偏低，又須增設昂貴點膠 之維持。 隹二斥差異，亦不利於產品品質一致性 【發明概述】： 於大的即在提供一種屏除傳統點膠方式， 佈時US::表面上一次同時刷·，致使膠劑塗 體封裝件製法及其早位犧晶片佈勝產能之半導 且便目的在於提供-種無須使用昂貴佈膠機 體封裝件製法及其結構。 或夕封裝成本之+導 本發明之再一目的係在提供一 致性之半導體封裝件製法及其結#。维持曰曰片表面佈膠- :、、、達成上揭及其他目的，本發明提供之半導體封裝件 16576.ptd 第8頁 527672 五、發明說明（3) 製法係包含以下步驟：先 黏接複數片 一晶片具有 面，且各第 接，而後’ 該等第一晶 於各第一晶 寸須小於該 一絕緣性膠 於該作用表 該模組板及 體晶片（即 二晶片及基 複數個疊晶 本發明 架撐起一大 阻擋屏障， 對應之孔部 黏層；因此 短佈膠時程 甚者，本發 組板取代昂 少封裝成本 【圖式簡單 第一半 一佈設 一晶片 用一支 片之一 片上方 苐一晶 劑施加 面上形 支撐件 第二晶 板，再 型半導 製法之 小足以 遂佈膠 而使每 導體晶 有多數 與基板 撐件（ 模組板 處乃開 片之作 到該模 成一具 ，並於 片）， 進行模 體封裝 特徵係 遮覆該 後流動 備妥 片（ 電子 間係 如絕 架撐 設有 用表 組板 適當 各膠 復藉 壓、 件。 於佈 等第 膠劑 片第一晶片 可採I膠方式一次 並可維持各第一晶 明封裝方法屏除習 貴點膠機具達成晶 之支出。 說明】： 一基板’並於該基板上分散 即第一晶片），其中，該第 電路及電子元件之作用表 藉由多條第一銲線導電連 緣框架）將大小適足以遮覆 於該基板上，該模組板對應 至少一孔部，並且該孔部尺 面面積，著即實施佈膠，將 上，使該膠劑流入各孔部俾 厚度之膠黏層；最後，移除 黏層上疊接至少一第二半導 多條第二銲線電性導接該第 植球及切單等程序便能製得 膠前先在該基板上用支撐件 一晶片之模組板供作膠劑之 會順勢流入各第一晶片上方 之作用表面上同時形成一膠 成批塗佈所有晶片’大舉縮 片表面之佈膠一致性；尤有 用點膠製程，利用價廉之模 片表面之佈膠作業，更能減
16576.ptd 第9頁 527672 五、發明說明（4) 以下茲以較佳具體例配合所附圖式進一步詳述本發明 之特點及功效： 第1 A至1 F圖係本發明半導體封裝件製法之第一實施例 之製作流程示意圖； 第2A圖係本發明半導體封裝件中佈膠模組板及供其承 載之支撐件之上視示意圖； 第2 B圖係本發明半導體封裝件中佈膠模組板及供其承 載之支撐件之剖面示意圖； 參 第2 C圖係本發明半導體封裝件中一體連設有撐設部之 佈膠模組板之剖面示意圖； 第3圖係本發明半導體封裝件實施佈膠製程另一實施 例之剖面結構圖；以及 第4A至4C圖係習知半導體封裝件製法之製作流程示意 圖。 【發明詳細說明】： 茲配合第1 A至1 F圖詳細揭露本發明半導體封裝件製法 之實施例，惟以下各圖均為簡化之示意圖式而僅標示與本 發明實施例有關之元件，然其實際實施態樣涵蓋之元件種 類與元件數量應更行複雜。 請參閱第1 A至1 F圖進一步說明本發明半導體封裝件製 作流程之第一實施例。如第1 A圖所示，該半導體封裝件製 法之第一步驟係備妥一矩陣式BGA基板1 0，該基板1 0係由 複數個基板單元1 0 0以行數乘以列數之陣列方式排列所構 成者，如圖所示，該矩陣式BGA基板1 0係包含有4 X 4陣列
16576.ptd 第10頁 527672 五、發明說明（5) 共16個基板單元100。 而後，如第1B圖所示，於各基板單元100上預設位置 分別以膠黏劑1 1 1黏接一第一半導體晶片1 2 (以下稱為第 一晶片12)，其中，該第一晶片12具有一作用表面120 (亦即佈設有多數電子電路與電子元件之表面）及一相對 之非作用表面121。待上片完成後，藉由金線等多數第一 銲線1 3將各第一晶片1 2與供該晶片1 2黏接之基板單元1 0 0 導電連接。此採用之打線製程（W i r e Β ο n d i n g )倶屬習知 故不重複贅述，惟為避免打線後線弧突出該作用表面1 2 0 之弧高（Loop Height)太大會影響後續佈膠作業實施， 本實施例亦可採逆向打線技術（R e v e r s e Β ο n d i n g )為 之。 接而，如第1C圖所示，在不影響各第一晶片12與第一 銲線13佈局條件下，備一塑膠薄層或有機基板材質製得之 模組板1 4，該模組板1 4之大小須足以遮覆矩形BG A基板1 0 上所有第一晶片1 2，且模組板1 4内對應於各第一晶片1 2中 央部位係開設有至少一孔部1 4 0，且該孔部1 4 0之尺寸必須 小於該第一晶片1 2之作用表面1 2 0面積。而後，如第2 A圖 (上視圖）及第2B圖（剖視圖）所示，藉由多數與該模組 板14 一體成型並向下延伸之撐設部141或一以FR-4樹脂等 基板材質製成之絕緣框架142抵置於基板10表面，以供該 模組板1 4抬高到該等第一晶片1 2上方，其中，該絕緣框架 142之高度乃取決於後續疊接之第二半導體晶片15 (以下 稱作第二晶片1 5 )(請參閱第1 E圖）尺寸；當該第二晶片
16576.ptd 第11頁 527672 五、發明說明（6) - 1 5面積小於供其承接之第一晶片1 2 (亦即該第二晶片1 5不 會觸接到第一晶片1 2周圍打線區域）時，絕緣框架1 4 2僅 需將該模組板1 5架高到第一晶片丨2上方而無須設限高度。 惟當該第二晶片1 5大小觸及到第一晶片1 2打線區域， 甚至等於或大於供其承接之第一晶片12時，為防止第二晶 片15安置時碰觸第一銲線群13而導致第一銲線13與上下層 晶片1 5，1 2形成不當電性觸接，乃如第3圖另一實施例所 示’該絕緣框架1 4 2之高度（Η )必須大於第一銲線1 3打線 後高出該作用表面120之最大弧高差（h)以及第一晶片12 厚度（HD )之總和，致使佈膠後形成之膠黏層π 2得將夾 f 置於該第一及第二晶片1 2，1 5間之部分第一銲線段1 3完整 包覆，而令每條第一銲線1 3外圍均呈一電性絕緣狀態。 再而，如第1 D圖所示，於該模組板1 4上施以佈膠作 業，其採用之刷膠技術悉同習知故不多言。由於該模組板 1 4内對應於各第一晶片1 2上方均設有至少一孔部1 4 0，因 而佈膠後受到該模組板1 4之阻隔，選自銀膠、環氧樹脂 (Epoxy)或聚亞醯胺（Poly imide )等材質所製之流動性 絕緣膠劑11會流入該等孔部1 40並滯留於各第一晶片1 2之 作用表面120上以形成一具適當厚度之膠黏層112，並且如 前所述該膠黏層1 1 2之厚度（HA )僥由該絕緣框架1 42之高⑩ 度（Η )所決定之。 選用尺寸足以遮覆多數第一晶片12之模組板14架高並 藉内設孔部1 40決定佈膠位置之佈膠方式，將能使矩陣式 BGA基板10上所有第一晶片12預備形成膠黏層之區域（未
16576.ptd 第12頁 527672 一~———<— __ v 五、發明說明（7) ) 1同時外路’故可運用模組概念（Module Concepts 曾―人佈膠完成使批次化製程得以建立。因此，本發明半 V體封裝件製法無須使用傳統點膠技術而能改用設備成本 極為低廉之模組板製程達到佈膠目的，致使封裝成本顯著 降低。同時，經由控制該模組板丨4架設之高度更能進一步 調整膠黏層112之佈設厚度，從而避免第一銲線13觸及上 下層晶片導致短路發生。
如第1 E圖及第1 F圖所示，俟佈膠作業完成後，旋即移 除該模組板1 4及絕緣框架1 4 2，並以疊晶方式將複數片第 二晶片1 5分別黏置於各膠黏層1 1 2上，經過高溫烘烤 (Curing )以及打線程序，令該等第二晶片15藉由多數第 二銲線1 6與各基板單元1 〇 〇間形成導電連接，即能實施模 壓製程，用一封裝膠體17完整包覆該第一、第二半導體晶 片1 2，1 5以及第一及第二銲線1 3，1 6。最後，經過植球及切 單作業而製得複數個疊晶型半導體封裝件1 (按本實施例 所示’以4 X 4陣列排列之基板單元經由本發明封裝方法 可製得十六個疊晶型半導體封裝件）。
惟以上所述具體實施例，僅係用以闡明本發明之特點 及功效’而非用以限定本發明之可實施範圍，故在未脫離 本發明所揭示之精神或原理下完成之任何等效改變或修 飾’如以不連續型態之支撐件取代傳統網板設計等，皆仍 應為下揭之申凊專利範圍所涵蓋。 【符號標號說明】： 1，2 疊晶型半導體封裝件10, 20矩陣式BGA基板
16576.ptd 第13頁 527672
五、發明說明 ⑻ 100 基 板 單元 11 流 動 性 絕 緣 膠 劑 112 ，212 膠黏層 12, 22 第 ^ 半 導 體 晶 片 120 作 用 表面 121 非 作 用 表 面 13, 23 第 銲線 14 模 組 板 140 孔 部 141 撐 設 部 142 絕 緣 框架 15, 25 第 二 半 導 體 晶 片 16, 26 第 二 銲線 17 封 裝 膠 體 27 針 具 h 銲 線 距作用表面 之最大弧南差 Η 支 撐 件高度 Ηλ 膠 黏 層. 厚, 度 Hd 第 一 晶片厚度 16576.ptd 第14頁

Claims (1)

  1. 527672 六、申請專利範圍 1. 一種半導體封裝件製法，係包含以下步驟： 備妥一基板； 散置複數片第一半導體晶片於該基板上，該第一 半導體晶片具有一作用表面及一相對之非作用表面， 使各第一半導體晶片係藉該非作用表面與該基板穩固 黏接， 提供多條第一銲線俾令各第一半導體晶片電性導 接至該基板上； 藉至少一支撐件將大小足以遮覆該等第一半導體 晶片之一模組板架撐至該基板上，其中，該模組板對 應於各第一半導體晶片上方處係設有至少一孔部，且 該孔部尺寸須小於該第一半導體晶片之作用表面面積 佈膠到該模組板上，致使塗覆之膠劑流入該孔部 並滯留於該作用表面上以形成一具適當厚度之膠黏層 ， 移除該模組板及支撐件，並於各膠黏層上疊接至 少一第二半導體晶片； 提供多條第二銲線電性連接該等第二半導體晶片 及基板；以及 施以模壓與切單製程。 2. 如申請專利範圍第1項之半導體封裝件製法，其中，該 半導體封裝件係一疊晶型半導體封裝件（Stacked Semi conductor Package ) 〇
    16576.ptd 第15頁 527672 六、申請專利範圍 3. 如申請專利範圍第1項之半導體封裝件製法，其中，該 作用表面係一佈設有多數電子電路及電子元件之表面 〇 4. 如申請專利範圍第1項之半導體封裝件製法，其中，該 支撐件係由FR-4樹脂等基板材質製成之絕緣框架。 5. 如申請專利範圍第1項之半導體封裝件製法，其中，該 膠劑係一選自銀膠、聚亞醯胺（P 〇 1 y i m i d e )及環氧樹 脂（Epoxy )等絕緣性材質所組組群之一者所製成。 6. 如申請專利範圍第1項之半導體封裝件製法，其中，當 該第二半導體晶片尺寸不小於第一半導體晶片時，該 膠黏層之厚度須大於該第一銲線打線後線弧與第一半 導體晶片作用表面間形成之最大弧高差。 7. 如申請專利範圍第1項之半導體封裝件製法，其中，當 該第二半導體晶片尺寸不小於第一半導體晶片時，該 膠黏層係完整包覆夾置於該第一及第二半導體晶片間 之第一銲線段。 8. 一種半導體封裝件製法，係包含以下步驟： 備妥一基板； 散置複數片第一半導體晶片於該基板上，該第一 半導體晶片具有一作用表面及一相對之非作用表面， 使各第一半導體晶片係藉該非作用表面與該基板穩固 黏接， 提供多條第一銲線俾令各第一半導體晶片電性導 接至該基板上；
    16576.ptd 第16頁 527672 六、申請專利範圍 藉形成於一模組板上之複數個支撐件將該模組板 架撐至基板上，其中，該模組板之大小係足以遮覆該 等第一半導體晶片，且其對應於各第一半導體晶片上 方處並設有至少一孔部，而該孔部尺寸亦需小於該第 一半導體晶片之作用表面面積； 佈膠到該模組板上，致使塗覆之膠劑流入該孔部 並滯留於該作用表面上以形成一具適當厚度之膠黏層 移除該模組板，並於各膠黏層上疊接至少一第二 半導體晶片； 提供多條第二銲線電性連接該等第二半導體晶片 及基板；以及 施以模壓與切單製程。 9.如申請專利範圍第8項之半導體封裝件製法，其中，該 半導體封裝件係一疊晶型半導體封裝件（Stacked Semi conductor Package ) ° 1 0 .如申請專利範圍第8項之半導體封裝件製法，其中，該 作用表面係一佈設有多數電子電路及電子元件之表面 1 1 .如申請專利範圍第8項之半導體封裝件製法，其中，該 支撐件係一與該模組板一體成型並向下延伸之撐設部 〇 1 2.如申請專利範圍第8項之半導體封裝件製法，其中，該 膠劑係一選自銀膠、聚亞酸胺（P 〇 1 y i m i d e )及環氧樹
    16576.ptd 第17頁 527672 六、申請專利範圍 月旨（Epoxy〕 1 3 .如申請專利 該第二半導 膠黏層之厚 導體晶片作 1 4 .如申請專利 該第二半導 膠黏層係完 之第一鲜線 1 5 . —種半導體 一基板； 至少一第一半 等絕緣性材質所組組群之一者所製成。 範圍第8項之半導體封裝件製法，其中，當 體晶片尺寸不小於第一半導體晶片時，該 度須大於該第一銲線打線後線弧與第一半 用表面間形成之最大弧高差。 範圍第8項之半導體封裝件製法，其中，當 體晶片尺寸不小於第一半導體晶片時，該 整包覆夾置於該第一及第二半導體晶片間 段。 封裝件，係包含： 參 相對 體晶 之非作 片穩固 多數第 導體晶 用表面，並藉 黏接於該基板 一鲜線，以供 間電性導接； 一膠黏層，將 組板係 半導體 方處並開設有 部而滯留於該作用表 第二半導體晶 黏置於該第一 二銲線，俾供 板上 遮覆 片上 該孔 該模 各第 至少 半導體晶片 多數第 形成該 藉至少 晶片， 至少一 片，其具有一作用表面及一 該非作用表面將該第一半導 上； 該第一半導體晶片與該基板 膠黏層之膠劑佈覆至一模組 一支撐件架撐於基板上以供 而模組板相對於該等第一晶 孔部，俾令膠劑佈覆後流入 面上； 片，係藉該膠黏層將該第二 半導體晶片上； 該第二半導體晶片導電連接
    16576.ptd 第18頁 527672 以及 六、申請專利範圍 至基板上 一封裝膠體，用以包覆該第一半導體晶片，第一 銲線，第二半導體晶片及第二銲線。 1 6 .如申請專利範圍第1 5項之半導體封裝件，其中，該半 導體封裝件係為一疊晶型半導體封裝件（Stacked Semiconductor Package) 〇 1 7 .如申請專利範圍第1 5項之半導體封裝件，其中，該作 用表面係一佈設有多數電子電路及電子元件之表面。 1 8 .如申請專利範圍第1 5項之半導體封裝件，其中，該支 撐件係由FR-4^•脂等基板材質製成之絕緣框架。 1 9 .如申請專利範圍第1 5項之半導體封裝件，其中，該支 撐件係一與該模組板一體成型並向下延伸之撐設部。 2 0 .如申請專利範圍第1 5項之半導體封裝件，其中，該膠 劑係一選自銀膠、聚亞醯胺（P〇 1 y i m i d e)及環氧樹脂 (Epoxy)等絕緣性材質所組組群之一者所製成。 2 1 .如申請專利範圍第1 5項之半導體封裝件，其中，當該 第二半導體晶片尺寸不小於第一半導體晶片時，該膠 黏層之厚度須大於該第一銲線打線後線弧與第一半導 體晶片作用表面間形成之最大弧高差。 2 2 .如申請專利範圍第1 5項之半導體封裝件，其中，當該 第二半導體晶片尺寸不小於第一半導體晶片時，該膠 層係完整包覆夾置於該第一及第二半導體晶片間之第 一鲜線段。
    16576.ptd 第19頁
TW091102334A 2002-02-08 2002-02-08 Stacked semiconductor device and method of manufacture TW527672B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091102334A TW527672B (en) 2002-02-08 2002-02-08 Stacked semiconductor device and method of manufacture
US10/170,665 US6709894B2 (en) 2002-02-08 2002-06-12 Semiconductor package and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091102334A TW527672B (en) 2002-02-08 2002-02-08 Stacked semiconductor device and method of manufacture

Publications (1)

Publication Number Publication Date
TW527672B true TW527672B (en) 2003-04-11

Family

ID=27657751

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091102334A TW527672B (en) 2002-02-08 2002-02-08 Stacked semiconductor device and method of manufacture

Country Status (2)

Country Link
US (1) US6709894B2 (zh)
TW (1) TW527672B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273438A (ja) * 2003-02-17 2004-09-30 Pioneer Electronic Corp エッチング用マスク
WO2005082611A1 (en) * 2004-02-26 2005-09-09 Boise White Paper, L.L.C. Erasable paper product
KR100696472B1 (ko) * 2004-07-15 2007-03-19 삼성에스디아이 주식회사 증착 마스크, 이를 이용한 유기 전계 발광 소자의 제조방법
KR100761468B1 (ko) * 2006-07-13 2007-09-27 삼성전자주식회사 반도체 장치 및 그 형성 방법
US7859092B2 (en) * 2007-01-02 2010-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures
US9312193B2 (en) 2012-11-09 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
KR20170027391A (ko) * 2015-09-02 2017-03-10 에스케이하이닉스 주식회사 복수의 칩들이 내장된 반도체 패키지 및 그의 제조방법
US10163808B2 (en) 2015-10-22 2018-12-25 Avago Technologies International Sales Pte. Limited Module with embedded side shield structures and method of fabricating the same
US10134682B2 (en) * 2015-10-22 2018-11-20 Avago Technologies International Sales Pte. Limited Circuit package with segmented external shield to provide internal shielding between electronic components
TWI735525B (zh) * 2016-01-31 2021-08-11 美商天工方案公司 用於封裝應用之濺鍍系統及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
US6316289B1 (en) * 1998-11-12 2001-11-13 Amerasia International Technology Inc. Method of forming fine-pitch interconnections employing a standoff mask
JP4757398B2 (ja) * 2001-04-24 2011-08-24 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US6709894B2 (en) 2004-03-23
US20030153123A1 (en) 2003-08-14

Similar Documents

Publication Publication Date Title
US9955582B2 (en) 3-D stacking of active devices over passive devices
TW546795B (en) Multichip module and manufacturing method thereof
US6462412B2 (en) Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
TW567601B (en) Module device of stacked semiconductor package and method for fabricating the same
TWI335652B (en) Stacked packing module
TWI307534B (en) Package structure, fabrication method thereof and method of electrically connecting a plurality of semiconductor chips in a vertical stack
TWI312569B (en) Semiconductor package on which a semiconductor device is stacked and production method thereof
TWI395316B (zh) 多晶片模組封裝件
KR100963471B1 (ko) 로직 및 메모리 집적 회로의 패키징 방법, 패키징된 집적회로 및 시스템
TW200425357A (en) Semiconductor multi-chip package and fabrication method
TW201214587A (en) Integrated circuit package system with offset stacking and anti-flash structure
TW527672B (en) Stacked semiconductor device and method of manufacture
JP2005535103A (ja) 半導体パッケージ装置ならびに製作および試験方法
CN101477956B (zh) 小片重新配置的封装结构及封装方法
TW200839996A (en) Stacked packing module
CN111326505A (zh) 具有电中介体的堆叠管芯半导体封装
CN101241902A (zh) 多芯片的半导体封装件及其制法
CN100446230C (zh) 半导体封装结构及其制法
CN110970414A (zh) 一种多芯片封装结构及制造方法
TW201143018A (en) A three dimensional chip stacking electronic package with bonding wires
CN109390292A (zh) 电子封装件及其制法
CN1216411C (zh) 叠晶型半导体封装件制法及其结构
TWI235464B (en) Carried structure of integrated electronic element and method for fabricating the same
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
TW200908260A (en) Packaging substrate and application thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees