TW525301B - Fabrication method of thin film transistor - Google Patents

Abstract

A fabrication method of thin film transistor is provided. A resist layer is formed on a P- type doped region covering part of the P- type doped region, in which the resist layer covering the P- type doped region has a greater thickness in the central region than at least part of the periphery region. Then, an ion implantation step is performed. Because of the thickness difference between part of the periphery region and the central region, an N+ type doped region and an N- type doped region can be formed in the P- type doped region concurrently. Moreover, the present invention can use an N+ ion implantation step to form the N+ type doped region first and remove the resist layer with certain thickness to expose part of the P- type doped region for forming a self-aligned N- type doped region by an N- ion implantation step. Subsequently, a gate insulation layer and a gate structure are formed sequentially to complete the fabrication of the thin film transistor.

Description

525301 V. Description of the Invention (l) The present invention relates to a method for manufacturing a thin film transistor (TFT), and particularly to a method for manufacturing a polycrystalline silicon thin film transistor. Low temperature polysilicon (LTPS) technology is different from the traditional traditional amorphous silicon (a-Si TFT LCD) technology, and its electron mobility can reach more than 200 cm2 / V-sec, so it can The function of making the TFT element smaller and increasing the aperture ratio (aperture rat i0), thereby increasing the degree of display respect and reducing power consumption. In addition, due to the increase in electron mobility, some driving circuits can be manufactured on the glass substrate together with the TFT process. This greatly improves the characteristics and reliability of the liquid crystal display panel, which greatly reduces the manufacturing cost of the panel, so the manufacturing cost is lower than that of a-si TFT. LCD is much lower. In addition, LTPS has the characteristics of thin thickness, light weight, and good resolution. It is especially suitable for mobile terminal products that require light and power saving. Low-temperature polycrystalline @TFT LCD

Yes, adopts Solid Phase Crystallization (SPC) process-but for high temperature processes up to 1,000 degrees, it is necessary to use a quartz substrate with a higher melting point. Because the cost of a quartz substrate is much more expensive than a glass substrate, and the substrate size Due to the limitation, the panel is only about 2 to 3 inches, so in the past only small daggers were exhibited. Later, due to the development of laser, the process of laser crystallization (aser CrystaHization) or excimer laser annealing (Excim s = r Annealing, ELA) process was used to make the amorphous silicon thin film into two shots. Let it be re-bonded: :: a 1 cd glass substrate can be used to make larger

525301 V. Description of the invention (2) Size panel. Figures 1A to II are shown as cross-sectional schematic diagrams of a manufacturing process of a conventional polycrystalline silicon thin film electric crystal. First, referring to FIGS. 1A to 1B, an amorphous silicon layer 140 is formed on a substrate 100. Then, an excimer laser annealing (Excimer User Annealing, ELA) process step 104 is performed to make the amorphous silicon film into a polycrystalline silicon film, and then a lithographic etching process is performed to form a patterned polycrystalline silicon layer. Next, a channel ion implantation is performed to form a first P-type doped region 102 and a second P-type doped region 102b. After that, please refer to FIG. 1C to form a patterned photoresist layer 106 on the substrate 100. Then, using the photoresist layer 106 as a mask, an ion implantation step 108 is performed to partially N + -type doped regions 103a, 103b are formed in a P-type doped region 1023. ’′ Then, referring to FIG. 1D, the photoresist layer is removed, and then a gate insulating layer 11 is formed on the substrate 100. And a second gate electrode is formed on the gate insulating layer 110 above a portion of the second p-type doped region I 02b, and on the gate oxide layer 110 above the first p-type doped region \ 〇2 &丨 丨 2b and the first 112a. Then, referring to FIG. 1E, the surface of the first gate electrode 112a is oxidized by using an anodic oxidation method to form a gate electrode II 3 ′ having an oxide layer n3a on the surface, wherein the gate oxide layer 11 3a is effective for blocking ion penetration. The capacity is lower than the gate 11 3. Then, a photoresist layer 4 is formed on the gate insulating layer 丨 丨 0, and the gate electrode 13 and the gate oxide layer 11 3a are exposed. Next, the photoresist layer

525301 V. Description of the invention (3) :: Gate oxide layer! Ua is a mask, which is doped by a type of dopant + medium, #two places 16 / Because of the oxide layer 1133 on the surface of the gate 113, it blocks the force The gate electrode 113 is low, and thus the first P-type doped region 101 is partially doped. Since the N-type doped region 101 is a doped region with a lower doping degree than N + & 10, the N-type doped H \ is a lightly doped drain (Light Doped Drain). , LDD), N + -type doped regions 103a, b 'formed in the first P-type doped region 102a are first source / drain electrodes. . Next, referring to Section IX, the photoresist layer 114 is removed, and then a photoresist layer 118 is formed on the insulative layer to expose the gate electrode 1121) and a second gate insulating layer over the doped region 1 0 2 b.丨 丨 〇. After that, a p + doped ion implantation step ι20 is performed using the gate electrode and photoresist f 118 as a mask to form a p + doped region 1 in part of the two P-type doped regions 1021). 5a, i05b, which are the second source / drain. In this way, the production of the polycrystalline silicon thin film transistor is completed, and the pixel unit of the thin film transistor liquid crystal display on the right includes the following steps: First, please refer to FIG. 1G for thin After the photoresist layer 118, a dielectric layer 122 is formed on the gate insulating layer u0 to cover the gate electrodes 12b and 113. Openings 124a, 124b, and 12b are formed in the dielectric layer 122 and the gate insulating layer ι10, The openings 124a and 124b respectively expose p + -type doped regions 105a and 105b, and the openings 12a and 126b respectively expose n + -type doped regions 103a and 103b. Next, please refer to FIG. 1 Fill the metal layers' in the openings 1 2 4 a, 1 2 4 b, 1 2 6 a, 126b to form the source wiring 128a, 13 (^ and the drain matching page 6 525301 V. Description of the invention (4) Lines 128b and 130b. After that, referring to FIG. 1i, a protective layer 132 is formed on the dielectric layers 122, source wirings 128a, 130a, and drain wirings 128b, 130b. Then, the protective layer 132 is formed in the protective layer 132. An interlayer window 134 is formed on the protective layer 132, and a day element electrode 136 is formed through the interlayer window 1 3 4 is electrically connected to the drain wiring 1 30b. In this way, the fabrication of a daytime structure is completed. Once known, the N-type doped region 1101 (LDD) is formed in a thin film transistor. The gate electrode 11 2a is first formed on the surface by an anodic oxidation method with an oxide layer U3a Ϊ = 13, and then the gate electrode 113 and the oxide layer 1 on the surface of the gate are used as the curtain. After the ion implantation step, The N-type doped region 101 (LDD) can be formed in part -p_. In the method, a step of adding a photomask (1⑽) is performed (a thin doped region ma,! 〇). 3b Λ Xi: Gate standard (πΠ-aUgrO forms N-type doped region) to the United States and Israel. The gate is self-aligning. However, if the gate is anodized, there are only a few metals (shao or button) available. Doping, the selectivity of this method to the gate metal, the rolling method, because the uniformity after anodization is important, and the gate is in the N-type doped region 1 Yangxinhua 2 produces quite symmetrical hetero-regions, which will increase the difficulty of the process .: is the formula to make N-type doped N-type doped regions, the disadvantage is that One more = one photomask is produced from the eve and there will be alignment problems between the two photomasks, plus the production cost of the mask, which is not easy to ensure the lightness formed. Page 7 of the invention, description of the invention (5) The self-alignment of the pole can be achieved. The purpose of the present invention is to provide the disadvantages of a thin film transistor: 晶体 f! Disadvantages of doping problems. s σ is the cost of a mask and the alignment between the two masks to avoid t! Π months? The purpose of f 7 is to provide a thin-film transistor manufacturing method, which can be used to manufacture light-doped drains in a low fabrication process. -型 # # Ε _ is formed with a first p ~ -type doped region and a

I-η-connector, forming a -th-photoresistance sound on the substrate, F: part-II-type -ρ-type exchange area, which is covered by * is greater than at least part of the edge; part: resistance: first The thick portion of the intermediate portion and the edge portion are used—and at least the edge portion of the first photoresist layer has sUWhalf_t0; e. Some masks / exposed areas (such as the thin photoresistive edge of the border. After that, An N + -type doped ion implantation step is formed in a ramp shape, and a photoresist layer is used as a mask to make the thickness different from the middle part. Therefore, at least part of the edge of the resist layer forms an N + -type doped region and an N —Doped σ ^, the first photoresist layer is formed in the 苐 -bu type doped region, and then the substrate is completely focused on the substrate. Then the second P-type doped region is removed and the second photoresist is removed. The resist layer 'exposes the implantation step' to perform a second ionization in part :: 2 ', and the impurity e forms -P + doping 525301. 5. Description of the invention (6) Region' It is a second source. The pole / drain region., On the free insulating layer above the region, are formed respectively-the first-gate two: the second "another thin film transistor A substrate, wherein the substrate 柘 tp, 士, and 百 -M-p ^ iA, 4 r are formed with a first p-type doped region and a first P-type doped region. Then, a substrate is formed on the substrate. Covering the second P-type doped region and part of the p-type region firstly, the thickness of the first p-type region is greater than at least a part of: to prevent: the first few Qiu Qixi, the interest margin plus \ 7 ^ degree A photoresist layer has a P1 edge and a F1 edge blade. It uses a # 1) $ with a local edge portion (such as a thin photoresist edge on the edge of the wheel gallery. After that, The first /) / is formed in a slope-like row, and the type is implanted with a hybrid ion implantation step; the next step is: 1 == !!, and the first step is: p— [to form an N + type doped region in the type doped region; It is-/ and the polar region. After that, the dry part of the edge part of the source part is exposed, and the part of the first type is exposed: the layer of the least:-, type doped ion implantation ㈣, in Partially,-; _, and then enter the edge of the N + type doped region to form N_ type dopant light; dope the drain region. Then remove the first photoresist layer, and then: -A second photoresist layer, exposing part of the ρ: 'The formation layer on the soil plate is a mask, and a P + # 杉 杂 & is used in the second photoresistance-type doped region Γ:: ίϊ implantation step' to partially part of the second ρ- region: ^ = :: = Area 'It is a second source / drain junction substrate-intermediate insulation layer' and is formed on the first Bu type doping, page 9, description of the invention (7) can avoid the conventional Utilization will be limited to only a few gate insulation layers above the gate region that can be avoided and a first gate electrode and a P / type doped region above the gate insulation layer are formed separately. P >, a gate. Gate anodization ^ type = doped drain method metal can be used for the anode ^ also made into lightly doped drain electrode in the shape of the present invention :! limits. The anodizing method is formed by the formula: to avoid the conventional points. Miscellaneous, and extremely, there is a lack of increasing process difficulty

The present invention utilizes a photomask with a thinner photoresist at the edge of the right edge ^ ° 卩 to form at least part of the photomask: an additional mask is required to form a photomask at the edge of the factory to form at least part of the photomask for the invention: and since = Of ;, drain. The detailed description is as follows: The car is "exemplified, and in accordance with the attached drawings, the detailed description of the diagram is shown: 1 0 0, 2 0 0: substrate 101, 201: N-type doped region 1 4 0, 2 4 0: Polycrystalline silicon layers 102a, 102b, 202a, 20 2b: P-type doped regions 103a, 103b, 203a, 203b: N + type doped regions 104, 108, 116, 120, 204, 208, 209, 2 "· · a "z. Ion implantation 525301 V. Description of the invention (8) Steps 105a, 106, 105b, 205a, 205b: P + type doped regions 114: 118, 20 6, 20 6a, 20 7, 207a 2 1 0: Photoresistor 110 112a 113a 122 124a, 226b: openings 128a, 130a 128b 132 134 136 2 1 6 b: gates 126b, 224a, 224b, 226a 2 1 4: gate insulation layers, 112b, 113, 216a: oxide layer 222: Dielectric layer, 124b, 126a, 228a, 130b, 228b protective layer interlayer window day electrode 2 3 0 a: source wiring 230b: drain wiring 232 234 236 250: photomask 250a: partial exposure area example 2A As shown in FIG. 2 to FIG. 2, FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a polycrystalline silicon thin film transistor according to a preferred embodiment of the present invention. As shown in FIG. 3, FIG. FIG. 2C is a schematic diagram of forming a patterned photoresist layer. Referring to FIGS. 2A to 2B, a polycrystalline chip layer 240 is formed on a substrate 200. A method of forming the polycrystalline chip layer 240 is, for example, To form an amorphous silicon layer on the substrate 200, and then anneal with an excimer laser to

Page 11 525301 V. Description of the invention (9) The amorphous silicon layer is formed into a polycrystalline silicon layer. Afterwards, the polysilicon sound is patterned (for example, using a lithography process). Next, an ion implantation process is performed to form a polycrystalline silicon layer—the first p-type doped region 20 and the second p-type doped region 202b. / 、 After the first one, please refer to FIG. 2C, and form two layers 206 and 206a on the substrate 200 to define the N + -type doped region 203 = cover: cover part of the first P-type doped Photoresist layer above the miscellaneous area: a method in which the thickness of the photoresist layer is greater than at least part of the edge portion of the at least part of the edge resist layer ma; for example: = photomask 250 with a partially exposed area 25 0a (as in (Shown in Fig. 3), and the 2 exposed areas 25a are, for example, a combination region having a plurality of stripe patterns. The photoresist layer formed after the Sa / exposure, because the light transmittance of the first & or 25〇a is low, so the photoresist layer 2Oh = should be in the local exposure area 2 5 Oa After the exposure, only a part of the thickness is removed; the thickness of the at least part of the edge portion formed by the layer 2:63 is thicker than the at least part of the edge portion of the photoresist layer 206a formed by the layer may be, for example, a slope Shaped outline. Next, using the photoresist layers 206 and 206a as a mask, an ion implantation is performed for two hours in the part and a Γ-type doped region 202a to form an n + -type dopant & The source / drain, wherein the ion implantation concentration of the N 屮 -type doped ρ 103a2 03b may be, for example, a concentration in the range of 1014 to 1016 atonT / cn /. Then, referring to FIG. 2D, at least a part of the edge portion of the photoresist layer 206a is removed to form photoresist layers 207 and 207a. Wherein the photoresist layer M is removed. Page 12 525301 V. The method for describing at least a part of the edge of the invention (for example) can be, for example, using a dry etching method (such as a dry etching process using an oxygen plasma) to remove the photoresist layer 206, 2 0 6a So that the slope portion of the photoresist layer 206a can be removed.

After that, using the photoresist layers 207 and 207a as a mask, an ion implantation step 209 is performed to form an N-type doped region 201 in a portion of the first p-type doped region 202a. The N-type doped region 201 is a doped region with a lower doping degree than the N + -type doped regions 203a and 203b. Therefore, the N-type doped region 201 is a lightly doped region. Pole (LDD). The ion implantation concentration of the N-type doped region 201 may be, for example, a concentration that is one-tenth to one-thousandth of the doping degree of the N + -type doped regions 203a and 203b (for example, 1013 ~ 10i4 at〇m). / cm2). The schematic cross-section of the method shown in FIG. 4 is / ,,,,, and is another method of forming a lightly doped drain electrode according to the present invention. Please refer to the method in the region 2 01. The thickness of the implantation step 2 0 8 is less than 2 0 2a. Forming N + This form of N-type 2 0 6 a has the least degree of difference to penetrate through the blocking energy of the blocking ability is better than forming an N + replacement. Figure 4 shows a series of the present invention to form another N-type The doping is directly performed by using the photoresist layer 206a as a mask, wherein the thickness of the at least part of the edge portion of the photoresist layer 206a and the middle portion of the photoresist layer 206a is to be doped at the same time. The regions 203a, 203b, and the N-type doped region 200m. The method of the hybrid region 201 uses a photoresist layer after exposure

The f-edge portion and the middle portion 'have a proper, 3: = the thicker part of the photoresist layer is more sensitive to the force, and the thinner part of the photoresist layer is lower to achieve the-ion implantation step = area 2〇3a, 2 ° 3b, and -N-doped /:

525301 V. Description of the invention (11) Please refer to Figure 2E. After removing the photoresist layers 206 and 206a (or photoresist layers 2 07 ~, 207a), a photoresist layer 21 is formed on the substrate 200, only A portion of the second P-type doped region 20 2b is exposed. Next, an ion implantation step 212 is performed to form a P + -type, hetero-regions 20 5a and 20 5b in the second p-type doped region 20 仏 which is not covered with the photoresist layer 210, which is the second Source / Drain. Next, according to FIG. 2F, remove the photoresist layer 2 10, and then form a gate insulating layer 2 丨 4 on the substrate 200. The material of the gate insulating layer may be, for example, silicon nitride. Next, a first gate electrode 2j6a is formed on the gate insulating layer above the first P-type doped region 202 & which may or may not include the N-doped region 201 and above, and A second gate electrode 216b is formed on the gate insulating layer above the two P-type doped regions 20 ". The material of the gate electrodes 2i6a, 216b may be, for example, genus. === This completes the production of the polycrystalline silicon thin film transistor. However, in order to complete the pixel structure of a thin film transistor liquid crystal display, the following steps are further included: Referring to FIG. 2G ', a dielectric layer 2 2 2 is formed on the gate insulating layer 2 1 4 to cover the first-middle a 216b. And the dielectric is fine; = openings 224a, 224b, 226a, 226b are formed in the layer 214, where the openings 224a, 224b respectively expose the P + -type doped regions 205a, 205b, and the openings 226a, 226b. N + doped regions 203a and 203b are respectively exposed. Then, referring to FIG. 2H, a conductor layer is filled in the openings 224a, 224b, 226a, and 2 2b, and the material of the conductor layer may be, for example, Are metal to form source wirings 2 2 8 a, 2 3 0 a and drain wirings 2 2 8 b, 2 3 0 b. After that, refer to page 21 , The dielectric layer 222, the source wiring 228a, 230a and drain line 228b, a protective layer 232 is formed on 230b.

Page 14 525301 V. Description of the invention (12) Then 'formed in the protective layer 232-the interlayer window m' and then a pixel electrode 236 is formed on the protection, wherein the day element electrode 236 is connected to the electrode line via the dielectric layer 234 230b is electrically connected. So? Made. Yi Er, said, this embodiment uses a small portion of the i to form a material layer 206a, in order to form the n + -type doped regions 203a, 20p: = etch method to remove the photoresist layer 2_ The slope part ☆, and then thinner H; secondly, the same photoresist layer is used to form the type " ° 2〇oop and \ -type doped region 201, so there is no need for an additional light ^ y # ^ 201 (ldd) The part of J 2 is slope-shaped and round. 廉 = This type of doped region 203a, 2_-doped region is also quite uniform at this degree. ^ N-type doped region produced 201⑽), its width is as described above. The present invention has the following advantages: Polar anode oxygen: the square A of the hybrid pole can avoid the conventional Ezra 2 · The formation of the present invention _ 4 moxibustion anode anodization : t doped drain method can avoid the habitual use of gate. / y Lightly doped drain, which has the disadvantage of increasing the difficulty of the process. The mask 3 is used to dope the drain,… increasing-channel 4 is too complicated, so the production cost can be reduced. ¾ Clearly use a photomask with a partially exposed area to form at least a portion 525301. 5. Description of the invention (13) A thin photoresist layer with a thin edge thickness can be used to make a self-aligned lightly doped drain electrode. 0 Although the present invention has been The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be regarded as The appended application patents shall prevail.

525301 on page 16 is a simple illustration. Figures 1A to 1I are not intended to illustrate the manufacturing process of a polycrystalline silicon thin film transistor. Figures 2A to 2I are diagrams according to a preferred embodiment of the present invention. A schematic sectional view of the manufacturing process of a polycrystalline silicon thin film transistor; and FIG. 3 is a schematic view of forming a patterned photoresist layer in FIG. 2C; and FIG. 4 is a schematic sectional view of another method for forming a lightly doped drain in the present invention.

Page 17

Claims (1)

525301 6. Scope of patent application 1. A thin film transistor provides a substrate, the first type is doped in the base impurity region and a plate is formed to form a portion of the first area, which is covered with a middle portion and an edge portion. The thickness of the edge part is performed in a second type to remove the in part at the base in the first type doped region, a second gate 2. As claimed in the method, wherein the corridor. 3. As applied to the law, one of them has a local part. The first ion-implanted heavily doped region is a photoresist layer; a region on the second area plate is formed above the gate. The patent range of the photoresist layer is the patent range of the photoresist layer exposure area. A method for manufacturing a local exposure region includes the following steps:-A -type-doped region has been formed on the first region, and the first region and the first region and the first region; a photoresist layer, overlay strike # 结 朴 士Grasp and reproduce the photoresist layer in the second area and the part of the plate on the first u ^ & domain, and the thickness of the intermediate post A A • T ° ° min is greater than at least the step, to On the same day, A ^ t ^ inches form a first-type lightly doped region in a middle region; a first-type heavily-doped region; a gate insulating layer; and a first-type doped region and the second region. A first gate electrode and a thin film transistor according to item 1 are formed on the second insulating layer in the region. At least part of the edge part is in a slope shape. The thin film transistor according to item 2 is manufactured. The at least part of the edge portion is formed by using a photomask. The manufacturing method of the thin film transistor described in item 3 and is a combination of a plurality of stripe patterns No. 18 Tribune 5253〇i 6. Method of Patent Application 5. As described in the item No. of the scope of patent application, the manufacturing method of the 闸 -gate does not cover the n-type body, which leads to the formation of the mystery of the No.-= Miscellaneous 1 = ^ An amorphous silicon layer is formed on the substrate; a polycrystalline silicon layer is performed with an excimer laser; and, to teach the amorphous silicon layer to be formed, an ion implantation step is performed, so that Xi Yue visited the fart-doped area. The first type is formed by the silicon layer of Shi Xixi. 7. A thin film transistor manufacturer, providing-a substrate, the package has been opened on the substrate; the following steps: 4 the first type doped region has a first region two Type doped region, and the company # forms a photoresist layer on the substrate, Mo She visits the region, two = a region, which covers part of the g a = region and part has a middle part and an edge part, and Or the photoresist layer has a thickness of a portion of the edge portion; μ the thickness of the middle portion is greater than at least μ μ a first ion implantation step is performed to form a second type in a region of the husband Doping the photoresist layer without wind, removing the at least part of the photoresist layer, 'I =' — region 5 = dividing the -type doped region with an edge portion ♦, exposing the first to second The ion implantation step is to remove the photoresist layer in a first-th-type region by forming a first-type doped region; a doped region; forming a heavily-doped region in a portion of the second region; 525301 6. The scope of the patent application forms a gate insulation layer on the substrate; and On the gate insulating layer of the first type doped region of the first region of the first type doped region above the second area, respectively, forming a first gate electrode and a second gate. 8. The method for manufacturing a thin film transistor according to item 7 in the scope of the patent application, wherein the at least part of the edge portion of the photoresist layer has a sloped profile. 9. The method for manufacturing a thin-film transistor according to item 8 of the scope of patent application, wherein the at least part of the edge portion of the photoresist layer is formed using a photomask having a partially exposed area. 10. The method for manufacturing a thin film transistor according to item 9 of the scope of the patent application, wherein the locally exposed area is an area having a plurality of stripe pattern combinations. 11. The method for manufacturing a thin film transistor according to item 7 of the scope of the patent application, wherein the method of forming the first type doped region comprises: forming an amorphous silicon layer on the substrate; and performing the process with an excimer laser. A process for forming the amorphous silicon layer into a polycrystalline silicon layer; and performing an ion implantation step for forming the polycrystalline silicon layer into the first type doping region. 1 2. The method for manufacturing a thin film transistor according to item 7 of the scope of the patent application, wherein the method of removing the at least part of the edge portion of the photoresist layer includes a plasma dry-etching method. 1 3 · Manufacturer of thin film transistor as described in item 7 of the scope of patent application Page 20 525301 6. Method of applying for patent scope, in which the first gate does not cover the first step _____ team wing 丨 above a lightly doped region 1 4 · A lightly doped drain (LDD) The manufacturing method includes the following steps: providing a substrate having a first type doped region on the substrate; forming a photoresist layer on the substrate to cover a part of the first type doped region, wherein the first type doped region is covered; The photoresist layer on the doped region has a middle portion and an edge portion, and the thickness of the middle portion is greater than at least a portion of the thickness of the edge portion; and a first ion implantation step is performed to simultaneously form the first type A second heavily doped region and a second lightly doped region are formed in the doped region. 15. The method for manufacturing a lightly doped drain (LDD) as described in item 14 of the scope of the patent application, wherein the at least part of the edge portion of the photoresist layer is a sloped profile. μ, I6. The method for manufacturing a lightly doped drain (LDD) as described in item 15 of the scope of patent application, wherein the at least part of the edge portion of the photoresist layer is formed by using a photomask having a partially exposed area form. 17. The method of lightly doped drain (ldd) according to item 16 of the scope of patent application, wherein the locally exposed area is an area having a plurality of stripe pattern combinations. Manufacturing, production 18. The method of fabricating a lightly doped drain (LDD) as described in item 14 of the scope of patent application, wherein the concentration of the second type lightly doped region is doped in the second type heavily doped region One tenth to one thousandth concentration. Manufacture, master 19. The method of applying a lightly doped drain (LDD) as described in item 14 of the patent application, wherein the method of forming the first type doped region includes: Page 52 52i Forming an amorphous silicon layer on the substrate; forming the amorphous silicon layer overnight; performing a process with an excimer laser, a polycrystalline silicon layer; and performing an ion implantation step to doped the region. In order to form the polycrystalline stone layer to form the first type 20, a lightly doped drain (LDD) manufacturing method, the method includes the following steps: a type doping has a small part of the A substrate is provided. The substrate has a first type doped region. A photoresist layer is formed on the substrate f to cover a part of the first region. The photoresist is covered on the first type doped region. Layer, intermediate portion and edge portion, and the thickness of the middle portion is greater than the thickness of the edge portion; the exposed portion of the photoresist layer is subjected to a first ion implantation step so as not to be covered with the first type doping Forming a second plastic heavily doped region in the region; removing the at least part of the edge portion of the photoresist layer, the first type doped region; and performing a second ion implantation step to partially part of the first A second type of lightly doped region is formed in the type doping. = ·, Lightly Doped Drain (LDD) as described in item 20 of Shenjing's patent scope The edges of the photoresist layer are obliquely broken. ^ The edge of the lightly doped drain (LDD) as described in item 21 of the scope of the patent application, wherein the at least part of the edge portion of the photoresist layer is formed, and the axe has light in a partially exposed area. Simple formation. 525301 6. Scope of patent application 2 3 · The manufacturing method of lightly doped drain (LDD) as described in item 22 of the patent application scope, wherein the locally exposed area is an area having a plurality of stripe pattern combinations. 24. The method for manufacturing a lightly doped anode (LDD) as described in item 20 of the scope of patent application, wherein the method of forming the first type doped region includes: forming an amorphous silicon layer on the substrate; A process is performed with an excimer laser to form the polycrystalline silicon layer from the amorphous stone layer; and an ion implantation step is performed to form the polycrystalline silicon layer to form the first type impurity region. 25. The method for manufacturing a lightly doped drain (LDD) as described in item 20 of the patent application scope, wherein the method of removing the at least part of the edge portion of the photoresist layer includes a plasma dry etching method. Page 23