TW523877B - Method for increase the contact between conducting wire and landing pad - Google Patents

Abstract

The present invention relate to a method for increase the contact between the conducting wire and the landing pad, and improve the problem of bitline capacitor contact resistance. The method of present invention utilizes hot H3PO4 to eliminate the cap layer of nitride layer to expose more contact area onto landing pad poly silicon, which is between gates. Therefore, the align accuracy of bitline can be improved due to increasing the contact in following process of depositing the bitline polysilicon, and can also decrease the capacitor contact resistance.

Description

523877

V. Description of the invention (1) 5 -1 Field of the invention: The present invention relates to a process of a circuit in an integrated circuit, and particularly to a type of dynamic random access memory (DRAM) with additional wires and routing (^ landing pad) Contact surface 'method to improve bit line alignment accuracy. 2 BACKGROUND OF THE INVENTION Recently, integrat semiconductor technology has increased its junctions. Recently, the size of components and DRAM (p0ysi process, especially the accuracy problem), due to the ultra-large ion (ULSI) technique 'makes the crystal fruit' caused a 'high resolution size for its main bit line and section 1 i con p lug The size problem on the large-scale semiconductor substrate with ultra large scale lithography on the lithography of other components formed on the chip with incorrect micrographs must be 'reduced'. The density of integrated circuits has increased, and the reduction in the size of this density and the advancement of ^ technology and etching technology for component group density have been achieved. Therefore, in order to reduce the size of components, this type of line in DRAM polysilicon plugs requires very much Accurate lithography is very difficult to achieve. Due to the short circuit and other traditional methods of making bit lines that are difficult to control, the main storm provides-bottom # (not shown), substrate 2 following steps. First, Bottom: In the first layer in Figure -A-a device 'This device shows a dielectric layer such as θ eve silicon crystal (interpoly 523877 V. Description of the invention (2) --- — dielectric layer (IPD1) 105) A polycrystalline silicon layer (p〇lysiHcón ia = 101) is formed on the upper, a, and middle sides of the two gate electrodes, and then a tungsten silicide layer 102 is formed on the polycrystalline layer 101. Then, on the tungsten metal stone / metal compound layer 102, a nitride nitride layer (S is N4) 103 is formed, and a silicon nitride spacer 104 is formed on both sides of the gate. Next, a planarization process of the polysilicon dielectric layer in the first layer is performed to facilitate the process of transferring and engraving in the next figure T. The polycrystalline silicon in the first layer is transferred through the photoresist 107 pattern transfer and etching process. The Shi Xi dielectric layer (IPD1) 105 is partially etched, and the inner polycrystalline silicon dielectric layer (IPDl) 1 〇5Α above the interrogator and the inner polycrystalline silicon dielectric layer (IPD 1) 1 0 5 Β on the gate and the gate are left. The surface of the columnar polycrystalline silicon layer 01 and the tungsten metal oxide layer 10 2, the silicon nitride layer 1 0 3, and the silicon nitride spacer 1 0 4 are shown in the first β diagram. As shown in Figure C, the etched portion is cleaned and filled with a land pad polys il icon 106, so that Fill up the engraved space, then remove part of the landing pad polysilicon 106 in the process of worming, and then cut the columnar top of the inner polycrystalline silicon dielectric layer by chemical mechanical polishing (CMP). 105 A and the top part of the polycrystalline silicon dielectric layer (IPDl) 1 05B on the side, as shown in the first figure d. Next, a second polycrystalline silicon dielectric layer (IPj) 2) i0g was deposited, and a planarization process was performed. Next, the photoresist is 109, as shown in the first E diagram. Next, Qian carved to remove the second polycrystalline silicon dielectric layer (丨 pD2) in the middle of the two gates, and formed a bit line contact surface A A1, and performed bit line polycrystalline silicon (

523877 V. Description of the invention (3) bitline polyS1lic0n) deposit n0, so that the upper and lower bit lines communicate. The disadvantage of the above-mentioned traditional method is that the bit line contact surface, A: touch ^ meters and t, the bit line is aligned in this way: the contact surface ordering and joining does have its difficulties. Therefore, in order to improve the accuracy of bit line alignment, the use of increased: contact area to improve the accuracy of the bit line contact surface. {Practical Improvement Department 5-3 Invention Purpose and Overview The second purpose is to provide a method to improve Dynamic Random Capture " " A method to improve the bit line contact accuracy in a social organization with 1 anding pad on the road pad. ^ The purpose of the contact is to provide-a method to reduce the bit line capacitance landing. According to: i: L, the method of the invention is mainly to remove the nitride from the gate and the gate 1 part of the gate. Xi ’s cap layer (cap polysi lic〇nf called “land pad polycrystalline silicon” (landing _ τ *, _) makes the bit line contact have a larger contact area. In the following bit line polycrystalline stone (bltllne) Chanka) deposited in ^

Page 8 523877 of crystalline silicon 5. In the description of the invention (4), due to the increase of the contact area, the accuracy can be obtained. In the actual step, a polycrystalline silicon layer and a silicided metal layer are deposited, and then a polycrystalline polysilicon dielectric, IPD1 process is filled around the first layer to remove the etched part and backfill the land pad polysilicon), in order to remove part of the The columnar top of the inner polycrystalline silicon dielectric layer facing the road pad, and then a silicon nitride layer), and then removed by P 0 * to increase the bit line contact with the inter polysilicon dielectric layer (inter p0iysUieQn), and perform the second inner polycrystalline silicon layer. The second layer of polycrystalline silicon in the middle of the two gates is etched as a bit line. Polycrystalline silicon is deposited ^ The polysilicon dielectric layer is etched much larger. This contact surface is enlarged, and then, Perform bit line multi-line connection. 5 4 Detailed description of the invention: The preferred embodiment of the present invention will increase the bit line alignment (alignment). First, a silicon nitride layer is used as a gate on a substrate. The Shi Xi dielectric layer (inter) is pattern-transferred and etched with a layer of polycrystalline silicon (filling the etch polycrystalline layer to deposit a layer of two gate areas, and then die 1 ect process, silicon The dielectric layer can improve the bit deposition and pass the space than the conventional bit line connection. Then, the silicon nitride layer (the middle nitride stone layer is deposited in the second layer, IPD2) after the #etch is exposed. Next, the pattern transfer and this inverted T-shaped art use the second layer of internal contact surface, and the range of the pixel line alignment accurately completes the MOS landing pad. The details are discussed later. The example is to use

523877

It is not intended to limit the invention to describe the scope of a particular example using the invention. In this embodiment, the second diagram A to the second G diagram are each embodiment of the present invention. In the second diagram A, first, a substrate is provided (a device is not shown on the substrate, and the device is shown as follows: there is a first layer inside) and an interpoly dielectric layer (IPDl) 2〇5 少 = 少; 1 The top, side and middle of the gate, and the CMP planarization process is performed on the upper surface of the polycrystalline silicon in the first layer.

(iirst layer polysilicon layer) 201, and then a tungsten metal silicide layer (tungsten si 1 pesticide layer) 20 2 is formed on the polysilicon layer 201. Next, a silicon nitride layer (Si3N4) 203 is formed on the tungsten metal silicide layer 202, and a silicon nitride spacer (Si1 icon nitride spacer) 204 is formed on the gate side. Next, a planarization process of the first polycrystalline silicon dielectric layer 205 is performed to facilitate subsequent pattern transfer and etching processes. After the photoresist 2.0 pattern transfer and etching process, the first inner polycrystalline silicon dielectric layer (IPD 1) 2 0 5 is partially etched, and the remaining

The inner polycrystalline silicon dielectric layer (IPD 1) 2 0 5 A above the electrode and the polycrystalline silicon dielectric layer (IPD 1) 2 0 5B on the side and the polycrystalline silicon layer 201 on the gate and the tungsten metal silicon oxide layer 202, the silicon nitride layer 203, and the silicon nitride spacer 204 'on the gate side are shown in the second figure B. Next, as shown in FIG. 2C, the #scribed portion is filled with a landing pad polysilicon 20 6 to fill the I-etched portion.

523877

Space, and the Cmp planarization process is performed on the upper surface of the polysilicon layer of the road pad. Then, a part of the landing pad polysilicon cap is removed by an etch back process. The space where the gate electrode is recessed is called a landing pad polysilicon cap. 20 6A 'Next, a layer of silicon nitride layer (Si 1 icon nitride layer) 301 is deposited as shown in the second D diagram. Next, the hot silicon oxide solution was used to etch the silicon nitride layer in the middle of the two gates to form the circuit 301 and then deposit the second polycrystalline silicon dielectric layer (inte) f (CDOcHelectnc, IPD2). 3 0 2, and a photoresist 3 3 on the polycrystalline silicon dielectric layer 30 2 in the second layer, as shown in the second E diagram. It must be mentioned here that the removal of the inner dielectric layer is performed by using wet dilute hydrofluoric acid (dUute hdrofluoric acid (DHF)) as a wet etchant. Next, the lithography process is used to remove the second inter poly dielectric layer 302 under the photoresist. This contact window plug communicates with the landing pad space 301 and forms a bit line contact (bitHne contact) plane BB1, as shown in the second F diagram. At this time, the bit line contact area has increased, as shown by the BB1 line. As for the bit line structure, the increase of the contact surface can increase the accuracy of the alignment. Next, as shown in FIG. 20, the bit line polycrystalline silicon (1 ^ 1: 1; [1161) 0; ^ was deposited at 1,040,044 to complete the bit line structure. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Application described

523877

The 523877 diagram on page 12 briefly illustrates the first diagram A to the first diagram F, which are cross-sectional views showing the structure of a conventional bit line structure; the second diagram A to the second diagram G show the manufacturing steps according to an embodiment of the present invention. A cross-sectional view of the element line structure process. Representative symbols of main parts: 101 polycrystalline silicon 1 02 tungsten metal silicide layer

1 03 Silicon nitride layer 104 Silicon nitride spacer wall 105 First polycrystalline silicon dielectric layer 105A Polycrystalline silicon dielectric layer above the gate 105B Polycrystalline silicon dielectric layer on the side 106 Polysilicon pad 107 Photoresist 108 Second In-layer polycrystalline silicon dielectric layer 1 0 Θ photoresist

110 bit line polycrystalline silicon 201 polycrystalline silicon 2 0 2 tungsten metal silicide layer 2 0 3 silicon nitride layer 2 04 silicon nitride spacer 2 0 5 polycrystalline silicon dielectric layer in the first layer

Page 13 523877 Brief description of the diagram 2 0 5A Inner polycrystalline silicon dielectric layer on the gate 2 0 5 B Inner polycrystalline silicon dielectric layer on the side 2 0 6 Landing pad polycrystalline silicon 2 0 6A Landing pad polycrystalline silicon cap 2 0 7 Light 301 silicon nitride layer 301A landing pad 3 0 2 polycrystalline silicon dielectric layer in the second layer 3 0 3 photoresist 3 04 bit line polycrystalline silicon 3 0 9 bit line contact AA1 traditional bit line contact surface BB1 The present invention Bit line contact surface

Page 14

Claims (1)

Method for adding the contact surface of the conducting wire and the road pad 523877 6. Scope of patent application 1. A method of integrative circuit device at least comprising: providing a substrate having a first gate structure and a second gate A pole structure is located on the substrate; a first internal dielectric layer is deposited on the substrate; a portion of the first internal dielectric layer is removed; a first conductor layer is formed on the first gate and the second Between the gates; the remaining part of the first conductor layer is formed; a cover layer is formed on the first conductor layer; a second internal dielectric layer is deposited on the cover layer and the first internal dielectric layer; The second inner dielectric layer above the first gate and the second gate, and the cover layer; and a second conductor layer forming a second conductor layer on the first gate and the second gate On a conductor layer. The inner inner layer on page 15th. Hai Hai = mouth = mouth product level, pondering the middle, the process, passing the French Fang Tan's flat item P 11 PIW, the enclosing "Sacrifice to Boli, 'Please pass by special trip . Application layers such as electricity • Intermediary 7Γ 6 y > 523877 6. Scope of patent application The first internal dielectric layer above. 5. The method according to item 1 of the scope of patent application, wherein the solvent of the etch-back coating layer contains at least 3P04. 7. The method according to the first item of the patent application, wherein the process of depositing the second inner dielectric layer includes a CMP planarization process to smooth the second inner dielectric layer. 0. The first application of the first patent application The method of claim 1, wherein the rest of the capping layer between the two gates is removing a silicon nitride cap. 9. The method according to item 1 of the patent application scope, wherein the removal of the inner dielectric layer comprises at least dilute hdrofluoric acid (D H F) as a solvent for wet #etch (wet e t c h i n g) technology. 10. A method for adding a contact surface of a conducting wire and a road pad in an integrated circuit device, the method at least comprising: providing a substrate having a first gate structure and a second gate structure located on the substrate Above Page 16 523877 6. The scope of the patent application deposits a first silicon oxide layer on the substrate; removes part of the first silicon oxide layer; forms a first contact window opening by a lithography process, and the contact window opening is located at Between the first gate structure and the second gate structure; depositing a first polycrystalline silicon layer in the contact window opening to form a contact window plug; etch back a part of the top of the contact window plug Part to form a landing pad; fill a silicon nitride layer in the landing pad; Etch back the silicon nitride layer between the two gates; deposit a second polycrystalline silicon layer on the silicon nitride layer and the first silicon oxide layer; form a second opening by a lithography process, and the second The opening is located above the second silicon oxide layer in the middle of the two gates; and a bit line polycrystalline silicon is deposited to fill the landing pad, the second opening, and the second polycrystalline silicon layer. 11. The method of claim 10, wherein the gate structure includes at least a polycrystalline layer, a monocrystalline layer, and a substrate. 1 2. The method according to item 11 of the application, wherein the polycrystalline silicon layer is a tungsten metal oxide layer. 1 3 · If the method in the scope of patent application No. 10, wherein the first lithography Page 17 523877 6. The scope of patent application includes at least: pattern transfer and etching of the first inner dielectric layer next to the two gate electrodes and above the gate electrodes. 14. The method according to item 10 of the scope of patent application, wherein the solvent of the remaining nitride layer includes at least H3P04. 15. The method of claim 10, wherein the process of depositing the first inner dielectric layer comprises a CMP planarization process to smooth the first inner dielectric layer. 16. The method of claim 10, wherein the process of depositing the second inner dielectric layer comprises a planarizing process with CMP to smooth the second inner dielectric layer. 1 7. The method according to item 10 of the scope of patent application, wherein the rest of the covering layer between the two gates is the removal of a silicon nitride cap. 18. The method according to item 10 of the scope of patent application, wherein the removal of the inner dielectric layer includes at least dilute hdrofluoric acid (DHF) as a wet-etching technology. Solvent. _ Page 18