522479 五、發明說明α) 詳細說明： 技術領域： 本發明係關於一種形成雙鑲嵌的方法，特別是關於一 種具雙硬式護罩模式（Dual Hard Mask Approach; DHM)之 雙鑲嵌的製程方法。 發明背景： 為了追求更快的運作速率以及更大的集積密度，積體 電路之研究單位及製造業者無不竭盡心力地設計及製造關 鍵尺寸（Critical Dimension; CD)更小的元件。根據實驗 顯示，當積體電路的製程進入0 . 1 8微米甚至0 . 1 3微米的技 術領域之後，影響元件運作速率的關鍵因素已從閘極的寬 度轉換至金屬内連線（metal interconnection)的電阻-電 容遲滯（R C d e 1 a y )效應。 因導線的阻值與其截面積成反比，隨著積體電路之集 積密度的提高，金屬内連線的線寬和厚度都隨之縮小，因 此其阻值便隨之提高；尤有甚者，隨著積體電路之集積密 度的提高，亦使金屬内連線的線距隨之縮小，因而造成導 線之間的耦合電容升高。因此當積體電路的製程進入深次 微米領域之後，金屬内連線的電阻-電容遲滯大幅提高， 也因此影響積體電路的運算速率和存取速率。為了提高積 體電路的集積密度，在線寬和線距都不宜提高的條件之 下，更換金屬内連線和層間介電層的材質是最佳的選擇。 在金屬内連線方面，金屬材質由原先的鋁矽銅合金或鋁銅522479 V. Description of the invention α) Detailed description: Technical field: The present invention relates to a method of forming a dual damascene, in particular to a method of a dual damascene process with a dual hard mask approach (DHM). Background of the Invention: In order to pursue faster operating speed and greater accumulation density, research units and manufacturers of integrated circuits have devoted all their efforts to designing and manufacturing smaller critical dimension (CD) components. According to experiments, when the integrated circuit manufacturing process enters the technical field of 0.8 micrometers or even 1.3 micrometers, the key factors affecting the operating speed of the components have been changed from the width of the gate to the metal interconnection. Resistance-capacitance hysteresis (RC de 1 ay) effect. Because the resistance of a wire is inversely proportional to its cross-sectional area, as the integrated density of the integrated circuit increases, the line width and thickness of the metal interconnects also decrease, so the resistance value increases accordingly; especially, With the increase of the integrated density of the integrated circuit, the line spacing of the metal interconnects is also reduced, thereby causing the coupling capacitance between the wires to increase. Therefore, after the manufacturing process of the integrated circuit enters the deep sub-micron field, the resistance-capacitance hysteresis of the metal interconnect is greatly improved, which also affects the operation rate and access rate of the integrated circuit. In order to improve the integration density of the integrated circuit, under the condition that the line width and line spacing should not be increased, it is the best choice to replace the material of the metal interconnects and interlayer dielectric layers. In terms of metal interconnects, the metal is made of the original aluminum-silicon-copper alloy or aluminum-copper
第4頁 522479 五、發明說明（2) 合金換成銅金屬，除了具有低電阻的特性外，更具有良好 的抗電子遷移性和良好的抗應力性，除了可以提高元件的 操作速率外，同時可以提升元件的可靠度；在另一方面， 層間介電層則必須選擇低介電常數（D i e 1 e c t r i c C ο n s t a n t)的材質以取代原有的二氧化石夕，以降低金屬内 連線之間的耦合電容。二氧化矽的介電常數約為3. 9，因 此必須選取介電常數小於3. 9的介電質做為層間介電層， 方可達到降低電阻-電容遲滯的功效，例如：氟摻雜之二 氧化矽（Si OF)、有機旋塗玻璃（HSQ)等等。 在銅製程的技術中，因銅金屬無法如同鋁合金一般用 氯氣進行蝕刻，因此業界發展出一種雙鑲嵌 (dual-damascene)的製程方法。首先請參考圖一，其為習 知技藝中形成雙鑲嵌之製程的示意圖。首先提供一已完成 前段製程的半導體基板10，形成一層第一介電層12，並在 所述第一介電層12中形成第一金屬連線14。接下來在所述 第一介電層1 2和第一金屬連線1 4之上陸續形成阻障層1 6、 第二介電層18、#刻停止層（etching stop layer)20、第 三介電層22、第一硬式護罩（hard mask)24、以及第二硬 式護罩26等等。其中所述第二介電層18和第三介電層2 2是 多孔性低介電常數介電層（porous l〇w-k dielectric 1 ay e r )，第一硬式護罩2 4係碳矽化物 (silicon-carbide)，第二硬式護罩2 6則為氮氧化石夕 (oxynitride)。因本製程使用雙層硬式護罩，因此業界稱 之為雙硬式護罩模式（Dual Hard Mask Approach; DHM)。Page 4 522479 V. Description of the invention (2) In addition to the characteristics of low resistance, the alloy is replaced with copper metal, which also has good resistance to electron migration and good stress resistance. In addition to improving the operating speed of the component, at the same time Can improve the reliability of the component; on the other hand, the interlayer dielectric layer must choose a material with a low dielectric constant (Die 1 ectric C ο nstant) to replace the original dioxide, in order to reduce metal interconnects Coupling capacitance between. The dielectric constant of silicon dioxide is about 3.9, so a dielectric with a dielectric constant less than 3.9 must be selected as the interlayer dielectric layer to achieve the effect of reducing the resistance-capacitance hysteresis, such as: fluorine doping Silicon dioxide (Si OF), organic spin-on glass (HSQ), etc. In the copper process technology, because copper metal cannot be etched with chlorine like aluminum alloy, the industry has developed a dual-damascene process method. Please refer to FIG. 1 first, which is a schematic diagram of a process of forming a dual mosaic in a conventional technique. First, a semiconductor substrate 10 that has completed the previous process is provided, a first dielectric layer 12 is formed, and a first metal wiring 14 is formed in the first dielectric layer 12. Next, a barrier layer 16, a second dielectric layer 18, a #etching stop layer 20, and a third layer are successively formed on the first dielectric layer 12 and the first metal connection 14. The dielectric layer 22, the first hard mask 24, the second hard mask 26, and the like. The second dielectric layer 18 and the third dielectric layer 22 are porous low dielectric constant dielectric layers (porous lww dielectric 1 ay er), and the first hard shield 2 4 is a carbon silicide ( silicon-carbide), and the second hard shield 26 is oxynitride. Because this process uses a double hard mask, the industry calls it the Dual Hard Mask Approach (DHM).
522479 五、發明說明（3) 接下來請繼續參考圖一，首先利用微影及蝕刻技術對所述 第二硬式護罩2 6進行蝕刻以形成開口 2 8，接下來再次利用 微影及蝕刻技術以形成通孔3 0，該蝕刻製程係終止於所述 名虫刻停止層2 0。 惟，當此一習知技藝運用於多孔性低介電常數介電層 之雙鑲嵌製程時有一嚴重缺點。在後續將所述第一硬式護 罩24穿透蝕刻的製程中，業界係使用含有（：11乂？丫/人1'/02之 電漿做為蝕刻氣體，其對於硬式護罩的蝕刻速率約為每分 鐘2 0 0 0埃，然而其對多孔性低介電常數介電層的蝕刻速率 高達每分鐘1 2 0 0 0埃。由於其對於多孔性低介電常數介電 層的蝕刻速率實在太高，因此通常在第一硬式護罩2 4尚未 完全穿透蝕刻時，第二介電層1 8已被完全蝕刻而裸露出所 述阻障層1 6。如此一來，當蝕刻製程繼續進行而將所述第 一硬式護罩2 4完全穿透蝕刻時，所述阻障層1 6早已被完全 蝕刻，導致蝕刻氣體進而蝕刻所述第一金屬連線1 4，並導 致所述第一金屬連線1 4因而受損害，嚴重影響產品的良率 及可靠度。 因此，為了提高產品的良率，發展出一種穩定之銅導 線/多孔性低介電常數介電層的整合製程以解決上述之過 度蝕刻問題，便成為半導體業界一項很重要的課題。 發明概述： 本發明的主要目的為提供一種具雙硬式護罩模式 (Dual Hard Mask Approach; DHM)之雙鑲喪的製程方法。522479 V. Description of the invention (3) Next, please continue to refer to FIG. 1. First, the second hard cover 26 is etched using lithography and etching technology to form an opening 28. Then, the lithography and etching technology is used again. To form a through hole 30, the etching process is terminated at the famous etch stop layer 20. However, there is a serious disadvantage when this technique is applied to the dual damascene process of porous low-k dielectrics. In the subsequent process of through-etching the first hard shield 24, the industry uses a plasma containing (: 11 乂? Ah / person 1 '/ 02 as an etching gas, which has an etching rate for the hard shield It is about 2000 Angstroms per minute, however, its etching rate for porous low dielectric constant dielectric layers is as high as 120 Angstroms per minute. Because of its etching rate for porous low dielectric constant dielectric layers, It is too high, so usually when the first hard shield 24 has not been completely etched, the second dielectric layer 18 has been completely etched and the barrier layer 16 is exposed. In this way, when the etching process When the first hard shield 24 is completely penetrated by continuing the etching, the barrier layer 16 is already completely etched, which causes an etching gas to etch the first metal wiring 14 and causes the As a result, the first metal connection 14 is damaged, which seriously affects the yield and reliability of the product. Therefore, in order to improve the yield of the product, a stable copper wire / porous low-k dielectric layer integration process has been developed. In order to solve the above-mentioned problem of over-etching, it becomes a semiconductor Bound of a very important issue Summary of the invention: The main object of the present invention is to provide a rigid shield having dual-mode (Dual Hard Mask Approach; DHM) of the process of preparing bis insert mourning.
522479 五、發明說明（4) 本發明的次要目的為提供一種形成雙鑲嵌的方法。 本發明揭露一種形成雙鑲嵌的方法，首先提供一已完 成前段製程的半導體基板，形成一層第一介電層，並在所 述第一介電層中形成第一金屬連線。後續在所述第一介電 層和第一金屬連線之上陸續形成阻障層、第二介電層、和 硬式護罩。利用微影技術定義出開口的位置，再利用非等 向性蝕刻技術對所述硬式護罩進行部分蝕刻。接下來利用 微影技術定義出通孔的位置，再利用非等向性蝕刻技術對 所述硬式護罩進行部分蝕刻。利用非等向性蝕刻技術以 C Η X F Y / A r / 0 2之電漿做為蝕刻氣體將所述開口内之所述硬 式護罩全部蝕刻後，再利用非等向性蝕刻技術對所述第二 介電層進行姓刻，以所述阻障層做為#刻終點。最後利用 非等向性蝕刻技術將所述通孔内之所述阻障層去除。 其中所述第二介電層是多孔性低介電常數介電層（porous l〇w-k dielectric layer)或非多孔性低介電常數介電 層，其厚度係習知技藝中第二介電層與第三介電層之厚度 之和，所述硬式護罩係碳石夕化物（s i 1 i c ο η - c a r b i d e )、氮 氧4匕石夕（oxynitride)或氮4匕石夕（nitride)0 12-第一介電層 1 6 -阻障層 2 0 虫刻停止層 2 4-第一硬式護罩 圖號說明 1 0 -半導體基板 14 -第一金屬連線 18-第二介電層 22-第三介電層522479 V. Description of the invention (4) The secondary object of the present invention is to provide a method for forming a dual damascene. The invention discloses a method for forming a dual damascene. First, a semiconductor substrate that has completed the previous process is provided, a first dielectric layer is formed, and a first metal connection is formed in the first dielectric layer. Subsequently, a barrier layer, a second dielectric layer, and a hard shield are successively formed on the first dielectric layer and the first metal connection. The position of the opening is defined by lithography technology, and then the hard shield is partially etched by using anisotropic etching technology. Next, the position of the through hole is defined by a lithography technique, and then the hard shield is partially etched by using an anisotropic etching technique. An anisotropic etching technique is used to etch the hard shield in the opening with C C XFY / Ar / 0 2 plasma as an etching gas, and then the anisotropic etching technique is used to The second dielectric layer is engraved, and the barrier layer is used as the #engraving end point. Finally, an anisotropic etching technique is used to remove the barrier layer in the through hole. The second dielectric layer is a porous low dielectric constant layer (porous lwk dielectric layer) or a non-porous low dielectric constant dielectric layer, and its thickness is the second dielectric layer in the conventional art. And the thickness of the third dielectric layer, the hard shield is a carbon oxide (si 1 ic ο η-carbide), an oxynitride, or a nitrogen nitride. 12-First dielectric layer 1 6 -Barrier layer 2 0 Insect stop layer 2 4-First hard shield drawing number description 1 0 -Semiconductor substrate 14 -First metal connection 18-Second dielectric layer 22 -Third dielectric layer
522479 五、發明說明（5) 2 8-開口 1 02-第一介電層 1 0 6 -阻障層 1 1 0 -硬式護罩 114-開口 1 1 8 -通孔 2 6-第二硬式護罩 3 0 -通孔 1 0 0 -半導體基板 104 -第一金屬連線 1 08-第二介電層 1 1 2-第一光阻 1 1 6-第二光阻 本發明係關於一種形成雙鑲嵌的方法，特別是關於一 種具雙硬式護罩模式（Dual Hard Mask Approach; DHM)之 雙鑲嵌的製程方法，不需使用蝕刻停止層，便可完成銅導 線/多孔性低介電常數介電層的整合製程。 首先請參考圖二，其為本發明中形成雙鑲嵌之製程的 示意圖。在圖二A中提供一已完成前段製程的半導體基板 100，形成一層第一介電層102，並在所述第一介電層102 中形成第一金屬連線1 0 4。接下來在所述第一介電層1 0 2和 第一金屬連線1 0 4之上陸續形成阻障層1 0 6、第二介電層 108、硬式護罩（hard mask)110。接下來塗佈上第一光阻 1 1 2，利用微影技術定義出開口的位置。 其中所述第二介電層10 8是多孔性低介電常數介電層 (porous 1 ow-k dielectric layer)或非多孑匕性低介電常 數介電層，其厚度係習知技藝中第二介電層1 8與第三介電 層22之厚度之和（煩請一併參考圖一），然不需有習知技 藝之#刻停止層2 0。所述硬式護罩1 1 0係碳石夕化物522479 V. Description of the invention (5) 2 8-opening 1 02-first dielectric layer 1 0 6-barrier layer 1 1 0-hard cover 114-open 1 1 8-through hole 2 6-second hard cover Cover 3 0-through hole 1 0 0-semiconductor substrate 104-first metal connection 1 08-second dielectric layer 1 1 2-first photoresist 1 1 6-second photoresist The present invention relates to a method for forming a double Damascene method, especially a dual damascene process method with dual hard mask approach (DHM), without the need for an etch stop layer to complete copper wires / porous low-k dielectrics Layer integration process. First, please refer to FIG. 2, which is a schematic diagram of a process of forming a dual damascene in the present invention. In FIG. 2A, a semiconductor substrate 100 having completed the previous process is provided, a first dielectric layer 102 is formed, and a first metal wiring 104 is formed in the first dielectric layer 102. Next, a barrier layer 106, a second dielectric layer 108, and a hard mask 110 are successively formed on the first dielectric layer 102 and the first metal connection 104. Next, the first photoresist 1 1 2 is coated, and the position of the opening is defined by a lithography technique. Wherein, the second dielectric layer 108 is a porous low-k dielectric layer (porous 1 ow-k dielectric layer) or a non-multi-layer low-k dielectric layer, and its thickness is in the conventional art. The sum of the thicknesses of the second dielectric layer 18 and the third dielectric layer 22 (please refer to FIG. 1 together), but it is not necessary to have a known technique of # 刻 STOP 层 20. The hard guard 1 1 0 is a carbonaceous compound
五、發明說明（6) (silicon — carbide)、氮氧 (nitride)。 矽（Myhtnde)或氮化石夕 接下來請參考圖二B，利 硬式護罩1 1 0進行部分蝕刻，非等向性蝕刻技術對 利用含氧氣之電漿去除所述 形成初級開口 i丨4。接述 接下來請參考圖二D，在 光阻11 2，如圖二c所7來 上 第二光阻116,再利用微影技硬式護罩11〇之上塗=。 來利用非等向性蝕刻技術餅所τ，定義出通孔的位置。接、 刻，以形成初級通孔11 8，如圖4硬式護罩110進行部分Ζ 氣之電漿去除所述第二光 Υ〜Ε所示。接下來利 接下來請參考圖二圖…。 硬式護罩110進行穿透餘刻，以开姓刻技術對所述 % Η Μ iri /n / 成一、及開口 1 1 4 a 〇 所、+、 、口 』技術係使用含有CHXFY/Ar/〇2之電喂做太述 刻氣體’同時亦會對所述第二介電層108進行蝕刻，：麵 加深所述初級通孔U8的深度而形成二級通孔n8a。而 所-t- ί下ί請參考圖二H，利用非等向性姓刻技術繼續斟 所述弟二介電層108進行蝕刻’以所 只訝 終點（e灿ng s_)。所述二級開π 114:及層二：：， =度因而增加而分別形成三級開口 "4級：級通孔11; 級通考圖二卜利用非等—刻技術將所述-nt孔U8b内之阻障層_去除’以形成開口 U4C及;^ 以上所述係利用較佳實施例詳細說明本發明，而非 522479 五、發明說明（7) 制本發明的範圍，而且熟知此技藝的人士亦能明瞭，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。 522479 圖 式簡單說明 圖 式 的 簡 要說 明 ； 圖 一 為習 知 技藝中形成雙鑲嵌之製程的示意圖。 圖 -— A是本發明製程 中 利 用 微 影技 術 定義 出開口的位 置 之 製 程 的剖 面 示意圖。 圖 二 B是本發明製程 中 利 用 非 等向 性 1虫刻 技術對所述 硬 式 護 罩 進行 部 分触刻， 以形成初級開口之製程的剖面示 意 圖 〇 圖 二 C是4 ^ 4 t明製程 中 去 除 第 一光 阻 之製 程的剖面示 意 圖 0 圖 二 D是本發明製程 中 利 用 微 影技 術 定義 出通孔的位 置 之 製 程 的剖 面 示意圖。 圖 二 E是本發明製程 中 利 用 非 等向 性 1虫刻 技術對所述 硬 式 護 罩 進行 部 分#刻， 以形成初級通孔之製程的剖面示 意 圖 〇 圖 二 F是本發明製程 中 去 除 第 二光 阻 之製 程的剖面不 意 圖 〇 圖 二 G是本發明製程 中 利 用 非 等向 性 雀虫刻 技術對所述 硬 式 護 罩 進行 穿 透ii刻， 以形成二 二級開口之製程的剖面示 意 圖 〇 圖 二 Η是4 &明製程 中 利 用 非 等向 性 蝕刻 技術繼續對 所 述 第 二 介電 層 進行姓刻 ，以所述阻障層做為蝕刻終點之 製 程 的 剖 面示 意 圖。 圖 二 I是本發明製程 中 利 用 非 等向 性 1虫刻 技術將所述 --- 級 通 孔 内之 阻 障層去除之製程的剖面示意圖。 522479 圖式簡單說明V. Description of the invention (6) (silicon — carbide), nitrogen oxide (nitride). Silicon (Myhtnde) or nitride nitride is shown in Figure 2B. The hard shield 110 is partially etched. The anisotropic etching technique is used to remove the oxygen-containing plasma to form the primary opening i 丨 4. Next, please refer to FIG. 2D, and apply a second photoresist 116 on the photoresist 11 2 and 7 shown in FIG. 2c, and then use the lithography technique to harden the cover 1110. Use the anisotropic etching technique to define the position of the via. Then, it is engraved to form a primary through hole 118, as shown in FIG. 4, the hard shield 110 performs plasma removal of part of the Z gas as shown in FIG. Next, please refer to Figure 2 and Figure…. The hard cover 110 is penetrated for the rest of the time, and the% Η iri / n / 成 一, and opening 1 1 4 a 〇, +,, 口 technology are used to open the nickname technique, which contains CHXFY / Ar / 〇. The electric power of 2 is used to perform the etching gas, and at the same time, the second dielectric layer 108 is etched, and the depth of the primary via hole U8 is deepened to form a secondary via hole n8a. And so please refer to FIG. 2H, using the non-isotropic surname engraving technique to continue to ponder the second dielectric layer 108 to etch the end point (ecanng s_). The two-level opening π 114: and the second level ::, = degrees are increased to form three-level openings " level 4: level through hole 11; level pass test diagram II using the non-equal-engraving technique to describe the- The barrier layer in the nt hole U8b _removed 'to form the opening U4C and; ^ The above description uses the preferred embodiment to describe the present invention in detail, rather than 522479. V. Description of the invention (7) The scope of the present invention is well known Those skilled in the art can also understand that making appropriate changes and adjustments will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention. 522479 Schematic brief description of the schematic brief description; Figure 1 is a schematic diagram of the process of forming a double mosaic in the conventional art. Figure-A is a schematic cross-sectional view of a process for defining the position of an opening using lithography in the process of the present invention. FIG. 2B is a schematic cross-sectional view of a process in which the hard guard is partially etched using an anisotropic 1 etch technique to form a primary opening in the process of the present invention. FIG. 2C is a 4 ^ 4 t removal process. Sectional schematic diagram of the process of the first photoresist. FIG. 2D is a schematic sectional diagram of the process of using the lithography technique to define the position of the through hole in the process of the present invention. FIG. 2E is a schematic cross-sectional view of a process in which the hard shield is partially etched using an anisotropic 1 etch technique to form a primary through hole in the process of the present invention. The cross-section of the photoresist process is not intended. Figure 2G is a schematic cross-sectional view of the process of using the anisotropic bird engraving technique to penetrate the hard cover in the process of the present invention to form a second or second opening. FIG. 2 is a schematic cross-sectional view of a process in which the second dielectric layer is continuously etched using an anisotropic etching technique in the 4 & Ming process, and the barrier layer is used as an etching end point. FIG. 2I is a schematic cross-sectional view of a process for removing the barrier layer in the --- level through-hole by using the anisotropic 1-etching technique in the process of the present invention. 522479 Schematic description
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