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TW520562B - Voltage regulated circuit with well resistor divider - Google Patents

Voltage regulated circuit with well resistor divider Download PDF

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Publication number
TW520562B
TW520562B TW91101217A TW91101217A TW520562B TW 520562 B TW520562 B TW 520562B TW 91101217 A TW91101217 A TW 91101217A TW 91101217 A TW91101217 A TW 91101217A TW 520562 B TW520562 B TW 520562B
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Taiwan
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doped region
voltage
region
patent application
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TW91101217A
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Chinese (zh)
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Yao-Wen Chang
Hui-Chih Lin
Tao-Cheng Lu
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Macronix Int Co Ltd
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Abstract

This invention relates to a voltage regulated circuit, more particularly, to a voltage regulated circuit with a well resistor divider. The present invention applies two well resistors act as the voltage regulated circuit and uses the characteristic of the well resistor in the resistance value, which is increased following the voltage that is transmitted to the well resistor to make an output voltage become a stable value. When the input voltage is an instable and over-high value, the depletion region in the well resistor will extend to absorb the over-high voltage value and make the output voltage to become a stable voltage value.

Description

520562 五、發明說明α) 5 - 1發明領域: 本發明係為一種電壓穩壓電路,特別是有關於一種利 用井電阻分壓的電壓穩壓電路。本發明利用兩個井電阻組 成電壓穩壓電路,使輸出的電壓為一穩定值。 5 - 2發明背景: 在積體電路中,電壓穩壓電路通常扮演著使輸出的電 壓為一穩定之電壓值的角色,以達到產品的需求。為了要 達到產品之效能,在某些半導體電路上的一些電路需要一 穩定的輸入電壓以維持其正常的功能。但是一般外界的輸 入電壓值,往往為一在一定範圍内變動之不穩定值,此不 穩定之電壓值將容易對某些電路產生不良的影響,進而降 低積體電路之效能並影響積體電路之品質。因此通常在需 要穩定電壓輸入值之積體電路上加入一電壓穩壓電路,以 維持電路之效能,並提高積體電路之品質。 通常大部分的電壓穩壓電路,均只隨著輸入電壓源的 改變而做調整。但是在大部分半導體元件的内部電路中, 電路的參考電壓將會隨著溫度及系統電壓源的改變而改變 。此種改變將會影響某些需要固定參考電壓之電路的運作 ,進而影響整個積體電路之品質。520562 V. Description of the invention α) 5-1 Field of the invention: The present invention relates to a voltage regulator circuit, and more particularly to a voltage regulator circuit using a well resistance divided voltage. The invention uses two well resistors to form a voltage stabilization circuit, so that the output voltage is a stable value. 5-2 Background of the Invention: In integrated circuits, voltage regulator circuits usually play the role of making the output voltage a stable voltage value in order to meet the needs of the product. In order to achieve product performance, some circuits on some semiconductor circuits require a stable input voltage to maintain their normal function. However, the external input voltage value is usually an unstable value that changes within a certain range. This unstable voltage value will easily have an adverse effect on some circuits, thereby reducing the performance of the integrated circuit and affecting the integrated circuit. Quality. Therefore, a voltage regulator circuit is usually added to the integrated circuit that needs to stabilize the voltage input value to maintain the performance of the circuit and improve the quality of the integrated circuit. Generally, most voltage regulator circuits only adjust as the input voltage source changes. However, in most internal circuits of semiconductor devices, the reference voltage of the circuit will change with temperature and system voltage source. This change will affect the operation of certain circuits that require a fixed reference voltage, and then affect the quality of the integrated circuit.

520562 五、發明說明(2) 5 - 3發明目的及概述: 本發明主要的目的為利用兩個井電阻組成一電壓穩壓 電路,以使輸出的電壓值為一穩定之電壓值。 本發明的第二個目的為利用兩個井電阻組成一電壓穩 壓電路,以提高積體電路之品質及良率。 本發明的第三個目的為利用兩個井電阻組成一電壓穩 壓電路,以加速積體電路之製程運作的效率。 本發明之再一個目的利用兩個井電阻組成一電壓穩壓 電路,以降低積體電路之製程運作的生產成本。 根據以上所述之目的,本發明提供了一項電壓穩壓電 路,利用兩井區電阻作為電壓穩壓電路,以使輸出電壓為 一穩定之電壓值。當輸入電壓穩壓電路之電壓為一不穩定 之電壓值時,其中一井電阻井區内的空乏區會隨著電壓的 增大而增加井電阻的電阻值。利用井電阻所增加之電阻值 可消耗輸入電壓所過多之電壓值,使得輸出之電壓值為一 預設之穩定的電壓值。另外,由於本發明之電壓穩壓電路 可由兩個相同架構的井電阻組成。當溫度變化時,兩個井520562 V. Description of the invention (2) 5-3 Purpose and summary of the invention: The main purpose of the present invention is to form a voltage regulator circuit using two well resistors so that the output voltage value is a stable voltage value. A second object of the present invention is to form a voltage stabilization circuit using two well resistors to improve the quality and yield of the integrated circuit. A third object of the present invention is to use two well resistors to form a voltage stabilization circuit to accelerate the efficiency of the process operation of the integrated circuit. Another object of the present invention is to use two well resistors to form a voltage regulator circuit to reduce the production cost of the integrated circuit during the process operation. According to the above-mentioned object, the present invention provides a voltage stabilizing circuit, which uses two well area resistors as a voltage stabilizing circuit so that the output voltage becomes a stable voltage value. When the voltage of the input voltage stabilizing circuit is an unstable voltage value, the empty area in the resistance area of one well will increase the resistance value of the well resistance with the increase of the voltage. The increased resistance value using the well resistance can consume the excessive voltage value of the input voltage, so that the output voltage value is a preset stable voltage value. In addition, the voltage regulator circuit of the present invention can be composed of two well resistors of the same architecture. When the temperature changes, two wells

電阻會同時變大或變小,、 所變化。利用本發明之=使輸出電壓不隨溫度改變而有 程之運作效率,並提高於壓穩壓電路還可加速積體電路製 可降低積體電路之製裎、=體電路之品質及良率。本發明更 、i連作的生產成本。 5一4發明詳細說明: w t發明的一些實施例合〜4 、、、田描述外,本發明還可ϋ平細描述如下。然而,除了詳 本發明的範圍不受限定,二爻地在其他的實施例施行,且 ”以之後的專利範圍為準。 電壓穩壓電路& 為電壓穩壓電路可控制略中為一相當重要之電路,因 某些積體電路的正^運=的電壓為一定值,因此可維持 範圍内變動之電壓值日±,雷當輸入的電壓值為在一固定之 能,吸收多餘之電壓=丄1壤穩壓電路可發揮其應有之功 壓值。 別,以供給某些電路一穩定之電 穩 電 聯 參照第〜圖所示,此Α 壓電路至少包含一楚一 f電壓穩壓電路之示意圖。電壓 阻100之一端鱼證干;、阻100與一第二電阻20 0。第一 的狀態。〜而電源弟二電阻20 0之 端而一參考電壓:塾Vcc ) 3⑽連接至第一電阻100之另 i ( vref ) 400由第一電阻1〇〇與第二電阻The resistance will increase or decrease at the same time. By using the invention, the output efficiency of the output voltage does not change with the temperature and has a range of operating efficiency, and the voltage regulator circuit is improved. The integrated circuit system can also be accelerated. The integrated circuit system can be reduced. . According to the present invention, the production cost of continuous cropping is increased. Detailed description of the 5-4 invention: In addition to the description of some embodiments of the invention, the present invention can be described in detail as follows. However, the scope of the present invention is not limited except that the scope of the present invention is not limited, and is implemented in other embodiments, and "subject to the scope of the subsequent patents. The voltage regulator circuit & is a voltage regulator circuit that can be controlled is slightly equivalent. Important circuits, because the voltage of positive voltage of some integrated circuits is a certain value, it can maintain the voltage value within a range of ±, and the input voltage value of Leidang is a fixed energy to absorb the excess voltage = 丄 1 The voltage stabilization circuit can exert its proper power voltage value. In addition, to provide some circuits with a stable electrical stability, the power supply circuit can be referred to as shown in the figure. This A voltage circuit contains at least one voltage. Schematic diagram of the voltage stabilization circuit. One terminal of the voltage resistance 100 is dry; the resistance 100 and a second resistance 20 0. The first state. ~ And the power source resistance of the two resistance 20 0 and a reference voltage: 塾 Vcc) 3⑽ Another i (vref) 400 connected to the first resistor 100 is composed of a first resistor 100 and a second resistor

第7頁 520562Page 7 520562

之接觸端拉出。第一電阻100之電阻值為R1且第二電阻 2⑽之電阻值為R2。巾第二電阻2〇〇之另一端則接地。因此 麥考電壓40 0的電壓值等於電源電壓3 電阻2 0 0之電阻值在總電阻(Ri+R2)之比例(又上弟一Pull out the contact end. The resistance value of the first resistor 100 is R1 and the resistance value of the second resistor 2A is R2. The other end of the second resistor 200 is grounded. Therefore, the voltage value of the McCaw voltage of 40 0 is equal to the ratio of the power supply voltage 3 resistance 2 0 0 to the total resistance (Ri + R2).

Vref = Vccx (R2/(R1+R2)))。當若第一電阻ι〇〇 及第二電阻 2〇〇均採用-般之電阻’則當電源電壓3〇〇值增加時 電剔00值也隨之增加。當第—電阻1〇〇採用本發明之井電 :且:,二;電源電壓3 00增強’落在第-電阻100上的跨壓 W加,則井電阻内之空乏區將會隨之擴大,電阻也隨之辩 大’而消耗過大之電壓值’使得參考電壓40 0仍為一定值曰 >’’、、_第一圖所示,此為利用本發明之井電阻為一 阻1 00的示意圖。此時井電阻運用在隔離區之下方。 阻位於—底材51()内,而底材内51Q内至 區520、一第二摻雜區53。、一第三摻雜區54。、—弟Y 550及-第四摻雜區56〇。帛一摻雜區52〇與第: :分別在第二,雜區53〇之兩㈣,而隔離區55〇則位於第?: 雜,5 2 0與第一摻雜區5 3 〇之間。隔離區5 5 〇可為—淺严>Vref = Vccx (R2 / (R1 + R2))). When the first resistor ιOO and the second resistor 2000 are both of the same resistance, when the power supply voltage 300 value is increased, the value of the electric pick-up 00 is also increased. When the first-resistor 100 adopts the well power of the present invention: and :, two; the power supply voltage 3 00 is strengthened, and the voltage across W-resistor 100 is increased, the empty area in the well resistance will be enlarged accordingly. The resistance will also be debated, and the voltage value that is too large is consumed, so that the reference voltage 40 0 is still a certain value, as shown in the first figure. This is to use the well resistance of the present invention as a resistance 1 00 schematic. Well resistance is now applied below the isolation zone. The resistance is located in the substrate 51 (), and within the substrate 51Q to the region 520 and a second doped region 53. And a third doped region 54. --- Y Y 550 and-fourth doped region 56. The first doped region 52 and the second region are respectively located at the second and second regions of the hetero region 53 and the isolation region 55 is located at the second? : Doped, between 5 2 0 and the first doped region 5 3 0. The isolation zone 5 5 〇 may be-shallow strict >

Hshallow trench ls〇Uti〇n; sn)區域或是場:化 16 〇Xlde ; F〇X)區域。第一摻雜區520、第二养% 530與=離區550均位於第三摻雜區54〇之上方。通 之:1〇為一 P型底材。帛-摻雜區520與第二摻雜Η 通常植入Ν+離子作為第一電極與第二電極。第三摻:30Hshallow trench (synchronous; Sn) region or field: Hxallow region; Fox) region. The first doped region 520, the second nutrient% 530, and the = off region 550 are all located above the third doped region 54. General: 10 is a P-type substrate. The erbium-doped region 520 and the second doped erbium are usually implanted with N + ions as the first electrode and the second electrode. Third blend: 30

第8頁 五、發明說明(5) 5 4 0通常植入n型離子 通常植入P型離子作為—、、#垔井區電阻。而第四摻雜區560 二電極與第三電極葬、第:電極且第三電極接地5 6 5。第 由第—摻雜區52〇輸曰入,、、二電阻f00連接。電源電壓3〇〇值 考電壓40 0。第一^ 亚可在第二摻雜區5 3 0上得到一參 隨著電路需求之一不同阻20第0為^型井電阻或是ρ型井電阻。 同結構之電阻。 電阻2 0 0可與第一電阻1 0 0為相 所需之離Ϊ通常Γ /區540及第四摻雜區56〇内植入 分有⑽至‘:;:摻雜區520植入的劑量為每立方公 米。第-tm· ’而離子植人之深度為U至U微 弟—摻濉£53〇植入的劑量為每立方公 021個離子至,而離子植入之 摻雜區540植入的劑量為每立/分· =〇. 5微米。第三 的劑n = 至1微米。第四摻雜區-植入 ]川里為母立方公分有1〇18至1〇21個 深度為〇·ι至0.5微米。 而離子植入之 電二弟一推雜區5 20輸入-電壓值後,此 =[將經由弟三徐雜區540而在第二摻雜區5 3 0上得到—夂 考電壓40 0之電壓值。當電源電壓3 0 0之電 古雷 壓值時’在第三摻雜區540和底材51〇之間的空區二電 向外擴散,而降低中性電性之區域(表昭曰 〆…、乐二圖戶斤不) ,Page 8 V. Description of the invention (5) 5 4 0 Usually implanted with n-type ions Usually implanted with P-type ions as-,, # 垔 Well area resistance. In the fourth doped region 560, the second electrode and the third electrode are buried, the first electrode and the third electrode are grounded to 5 5 5. The first-doped region 52 is input, and the two resistors f00 are connected. The value of the power supply voltage is 300. The test voltage is 40. The first sub-layer can obtain a parameter on the second doped region 5 3 0. Depending on one of the circuit requirements, the resistance 20 is the 0-type well resistance or the p-type well resistance. Same structure resistance. The resistance 2 0 0 can be the same as that required for the first resistance 1 0 0. Generally, the Γ / region 540 and the fourth doped region 56 are implanted with : to ′:; The dose is per cubic meter. -Tm · 'and the depth of implantation of the ion is U to U micro brothers-濉 doped £ 53. The implanted dose is 021 ions per cubic centimeter, and the implanted dose in the doped region 540 of the ion implantation is Per liter / min. = 0.5 micron. The third agent n = to 1 micron. Fourth Doped Region-Implantation] Chuanli has 1018 to 1021 cubic cubic centimeters and a depth of 0.5 to 0.5 microns. After the ion implantation of the second implanted region 5 20 input-voltage value, this = [will be obtained on the second doped region 5 3 0 through the third implanted region 540—consider the voltage of 40 0 Voltage value. When the electric voltage of the power source is 300, the second electric charge diffuses outward in the vacant region between the third doped region 540 and the substrate 51, and decreases the neutral electrical region (Table Zhao Yue) …, Le Ertu households do not weigh),

第9頁 520562 發明說明(6) 一 ΐ t::阻之電阻值’以吸收過量的輸入電壓*,使得在 第:二J:30上仍可獲得一穩定之參考電壓4〇〇值。因此 : 0中的空乏區545所擴大的範圍視由第-摻雜 入的電/Lt入之電壓值而決定。當第一摻雜區5 2 0上所輸 ,且共:值越大時,則苐二摻雜區540所擴大的範圍越大 若在:阻值也越高,以吸收過量之輸入電壓值。 # ^ R中,第二電阻2 0 0與第一電阻100均為相同姓構< 井電阻,則去、、W疮終仆n士,; h I ~ w U、、、口構之 ,以伟鈐山二井電阻會同時變大或變小 乂使輸出電壓不隨溫度改變而有所變化。 阻! 0 〇參白^導四體圖元另此發明立之井電阻為第一電 、二Γ Λ 材内51°内至少包含—第-摻雜區52。 5fin / —摻錶區530、一第三摻雜區54〇、一第四摻雜區 刀^弟二#雜區5 3 0之兩側,而第五摻雜區0 :=區52〇與第二掺雜區53。之間。第—摻雜區二於弟 按”530通常植入r離子作為第一電極與第::弟- 摻雜區56 0通常植入P型離子作為一第:電而弟四 二電極與第三電極藉由= “隹區57〇通常植人P型離子且接地58Q。電源電獅〇 =Page 9 520562 Explanation of the invention (6) ΐ t :: resistance resistance value to absorb excess input voltage *, so that a stable reference voltage value of 400 can still be obtained at the second: J: 30. Therefore: The extended range of the empty region 545 in 0 depends on the voltage value of the first doped doping / Lt doping. When the first doped region 5 2 0 is input, and the larger the total: value is, the larger the range of the second doped region 540 is. If the resistance value is also higher, the excessive input voltage value is absorbed. . In # ^ R, the second resistor 2 0 0 and the first resistor 100 are both of the same name structure < well resistance, then go to, and sores, and h I ~ w U,, and, The Weijingshan Erjing resistance will increase or decrease at the same time, so that the output voltage does not change with temperature. Obstruct! In the present invention, the resistance of the standing well is the first electric and the second Γ Λ at least including the -first-doped region 52 within 51 °. 5fin /-doped surface region 530, a third doped region 54o, a fourth doped region ^ Di Er # heteroregion 5 3 0 on both sides, and the fifth doped region 0: = region 52 and Second doped region 53. between. The first-doped region is usually implanted with r 530 as the first electrode and the first ::-the doped region 56 0 is usually implanted with p-type ions as the first: electrical and fourth electrode and third The electrode is usually implanted with P-type ions and is grounded to 58Q with "" region 57. Power lion 〇 =

第10頁 520562 五、發明說明(7) 第—摻雜區5 2 0輸入,並可右篦-抶枚广 壓二電阻2。。可為亡得到-參考電 著電路需求之不同,第:電阻UK,井電阻。隨 結構之電阻。 $阻2()()可與弟-電阻1GG為相同 、第百5依照半導體元件之電壓需求,在第-摻雜區520 入ί::Ϊ區53V第三摻雜區540及第四摻雜區56。内植 分有1而二 通'第一摻雜區520植入的劑量為每立方公 =有,至nm個離子’而離子植入之深度狀⑴& : : Ϊ雜區530植入的劑量為每立方公分有1018至1 離子植人之深度狀1至G. 5微米。第:捭 而籬早始方公分有1015至1018個離子, 添丨J量為每2 〇.3至1微米。第四換雜區560植入的 ί in -018至1021個離子,而離子植人之深 又二·至〇· 5微米。第五摻雜區57 0植入的離子數量為每 立方公分有1〇18至1021個離子,而離子植入之ζ數里為母 〇. 1至0.5微米。 心冰度為Page 10 520562 V. Description of the invention (7) The first-doped region 5 2 0 input, and the right 篦-抶 wide-voltage two resistor 2 can be input. . Available for reference-the difference in reference circuit requirements, number: resistance UK, well resistance. With the resistance of the structure. The resistance 2 () () can be the same as the brother-resistor 1GG. According to the voltage requirements of the semiconductor element, the fifth-doped region 520 is filled with the d :: Ϊ region 53V, the third doped region 540, and the fourth doped region. Miscellaneous area 56. Endophytic components have 1 and two-way 'first doped region 520 implanted dose per cubic cubic = yes, to nm ions' and ion implantation depth ⑴ &: doped region 530 implanted dose For each cubic centimeter there are 1018 to 1 ions implanted into a depth of 1 to G. 5 microns. Number: 捭 There are 1015 to 1018 ions in the early square centimeter, and the amount of added J is every 0.2 to 1 micron. The fourth implantation area 560 implanted Γ-018 to 1021 ions, and the implantation depth of the ions was another two to 0.5 micrometers. The number of implanted ions in the fifth doped region 57 0 is 1018 to 1021 ions per cubic centimeter, and the zeta number of the ion implantation is 0.1 to 0.5 microns. Heart ice degree is

當電源電壓300由第—摻雜區52〇輸入一 壓將經由第三摻雜區540而在第二摻雜區53 =JWhen the power supply voltage 300 is input from the first doped region 52, a voltage will pass through the third doped region 540 and the second doped region 53 = J

電壓400。當電源電壓3。〇突然升高電壓值 〗J 空= 上圍,/降低中性電性之區域(參照=所 不) 心大的弟二摻雜區540内的空乏區545將會增加井 520562 五、發明說明(8) 電阻之電阻值,以吸收過量的輪》 雜區530上仍可獲得一穩定之參考使=在弟二摻 540所擴大的範圍視由第三摻雜區54〇内之、、曲:第三摻雜區 此第三摻雜區540所擴大的範圍視由 礙度而決定,因 入之電壓值而決定。當第一換圍雜視二 越大時,則第三摻雜區540内的空 2輸入的電壓值 ,且井電阻的電阻值也越高, 尹夕大的範圍越大 電路中,第二電謂0與第-電二==電壓值。若在 阻,則當溫度變化時,兩個井電阻構之井電 使輸出電麼不隨溫度改變而有所變;叫交大或變小,以 、,卩現著製程需求之不同,底材5 1 〇也可按用M剂 當底材5 1 〇為N型之底材睥,筮 里之底材。The voltage is 400. When the supply voltage is 3. 〇 Sudden increase in voltage value J J = blank, upper / lower neutral area (reference = nothing) The vacant region 545 in the divalent doped region 540 of the heart will increase the well 520562 5. Description of the invention (8) The resistance value of the resistor to absorb the excess wheel. A stable reference can still be obtained on the miscellaneous region 530 so that the range extended by the second doped 540 is considered to be within the range of the third doped region 54. : The third doped region The enlarged range of the third doped region 540 is determined by the interference, and is determined by the voltage value. When the first parasitic change is larger, the voltage value of the space 2 input in the third doped region 540 is higher, and the resistance value of the well resistance is also higher. The larger the range of Yin Xi, the larger the second in the circuit. Electricity is 0 and -electricity == voltage value. If it is in resistance, when the temperature changes, the wells of the two wells make the output power do not change with the temperature change; it is called Jiaoda or smaller, so the difference in process requirements is shown. 5 1 〇 can also use M agent when the substrate 5 1 〇 is N-type substrate 睥, 筮 the substrate.

mo盥t 底材 弟一摻雜區52〇、第二摻# F 53 0契弟二#雜區54Q所植入的離 區5 60與第五摻雜區57〇所植入 而弟四摻雜 t ,,ρ , , 0 , , , ^ , ^ ^^^tt 7 4日口包丨且值e F現者溫度而呈現同比例的捭 07 穩壓電路的輸出電壓不僅不隨輸 ^化=—來此 隨環境溫度變化而改變。 i又化而改變,亦不 根據以上所述之實施例,本發明提供了一項 電路,利用-井區電阻作為電壓穩壓電路中一串:d 之其中之-電阻以使輸出電壓為一穩定之電壓值。當輸入 520562 五、發明說明(9) 電壓穩壓電路之電壓為一不穩定之電壓值時,井電阻之井 區内之空乏區會隨著電壓的增大而增加井電阻的電阻值。 利用井電阻所增加之電阻值可消耗輸入電壓所過多之電壓 值,使得輸出之電壓值為一預設之穩定的電壓值。利用本 發明之電壓穩壓電路還可提高積體電路之品質及良率。本 發明更可降低積體電路之製程運作的生產成本,不僅具有 實用功效外,並且為前所未見之設計,具有功效性與進步 性之增進,故已符合專利法之要件,爰依法具文申請之。 為此,謹貴 審查委員詳予審查,並祈早日賜准專利,至 感德便。 以上所述僅為本發明之較佳實施例而已,此實施例僅 係用來說明而非用以限定本發明之申請專利範圍。在不脫 離本發明之實質内容的範疇内仍可予以便化而加以實施, 此等變化應仍屬本發明之範圍。因此,本發明之範疇係由 以下之申請專利範圍所界定。The substrate 5 is implanted with a first doped region of 52 °, the second doped region # F 53 0 and the second doped region 54Q is implanted with a separation region 5 60 and a fifth doped region 57 is implanted, and the fourth region is implanted Miscellaneous t ,, ρ,, 0,,, ^, ^ ^^^ tt 7 4 day mouth bag, and the value of e F presents the same temperature as the current temperature. = —Here changes with changes in ambient temperature. i is changed and changed, and according to the embodiment described above, the present invention provides a circuit that uses -well resistance as a string in the voltage stabilization circuit: one of d-resistance to make the output voltage be one Stable voltage value. When input 520562 V. Description of the invention (9) When the voltage of the voltage stabilization circuit is an unstable voltage value, the empty area in the well area of the well resistance will increase the resistance value of the well resistance with the increase of the voltage. The increased resistance value using the well resistance can consume the excessive voltage value of the input voltage, so that the output voltage value is a preset stable voltage value. The voltage stabilization circuit of the present invention can also improve the quality and yield of the integrated circuit. The invention can further reduce the production cost of the integrated circuit manufacturing process operation. It has not only practical effects, but also a design never seen before. It has improved efficacy and progress. Therefore, it has met the requirements of the patent law, Apply for it. For this reason, the examiners are honoured to examine it in detail, and pray for the granting of patents at an early date. The above description is only a preferred embodiment of the present invention. This embodiment is only used for illustration, not for limiting the scope of patent application of the present invention. It can still be implemented without departing from the essence of the present invention. Such changes should still fall within the scope of the present invention. Therefore, the scope of the present invention is defined by the following patent application scope.

第13頁 520562 圖式簡單說明 第一圖為電壓穩壓電路之示意圖; 第二圖為利用本發明之井電阻為第一電阻的半導體電 路之示意圖; 第三圖為在利用本發明之井電阻為第一電阻的半導體 電路上通入過大電壓值之示意圖; 第四圖為利用本發明之井電阻為第一電阻的另一半導 體電路之示意圖;以及 第五圖為在利用本發明之井電阻為第一電阻的另一半 導體電路上通入過大電壓值之示意圖。 主要部份之代表符號 100 第 一 電 阻 200 第 二 電 阻 300 電 源 電 壓 400 參 考 電 壓 510 底 材 520 第 一 摻 雜 區 530 第 二 摻 雜 區 540 第 二 摻 雜 區 545 空 乏 區520562 on page 13 Brief description of the diagram The first diagram is a schematic diagram of a voltage stabilization circuit; the second diagram is a schematic diagram of a semiconductor circuit using a well resistance of the present invention as a first resistor; the third diagram is a well resistance using the present invention Schematic diagram of excessive voltage applied to the semiconductor circuit of the first resistor; Schematic diagram of another semiconductor circuit using the well resistance of the present invention as the first resistor; and Schematic diagram of the fifth resistor using the well resistance of the present invention Schematic diagram of excessive voltage applied to another semiconductor circuit of the first resistor. Representative symbols of the main parts

第14頁 520562Page 14 520562

第15頁Page 15

Claims (1)

520562 六、申請專利範圍 1. 一種利用一井電阻分壓的電壓穩壓電路,其中至少包含 一第一電阻,該第一電阻為該井電阻且該第一電阻包 含一第一端點及一第二端點; 一第二電阻,該第二電阻包含一第三端點與一第四端 點,其中上述之第三端點連接該第二端點且該第一電阻與 該第二電阻為一率聯的狀態; 一電源電壓,該電源電壓連接該第一端點;以及 一參考電壓,該參考電壓連接該第三端點與該第二端 點。 2. 如申請專利範圍第1項的電壓穩壓電路,其中上述之井 電阻為一N型井電阻。 3. 如申請專利範圍弟1項的電壓穩壓電路,其中上述之井 電阻為一 P型井電阻。 4. 如申請專利範圍第1項的電壓穩壓電路,其中上述之第 二電阻為一井電阻。 5. 如申請專利範圍第4項的電壓穩壓電路,其中上述之第 二電阻為一 N型井電阻。 6. 如申請專利範圍第4項的電壓穩壓電路,其中上述之第520562 6. Scope of patent application 1. A voltage stabilizing circuit using a well resistance divided voltage, which includes at least a first resistance, the first resistance is the well resistance and the first resistance includes a first terminal and a A second terminal; a second resistor including a third terminal and a fourth terminal, wherein the third terminal is connected to the second terminal and the first resistor and the second resistor It is in a state of being connected; a power voltage connected to the first terminal; and a reference voltage connected to the third terminal and the second terminal. 2. The voltage stabilizing circuit according to item 1 of the patent application range, wherein the well resistance is an N-type well resistance. 3. For example, the voltage stabilization circuit of item 1 of the patent application, wherein the well resistance is a P-type well resistance. 4. For the voltage regulator circuit of item 1 of the patent application, wherein the second resistor is a well resistance. 5. The voltage regulator circuit of item 4 of the patent application, wherein the second resistor is an N-well resistor. 6. The voltage regulator circuit of item 4 in the scope of patent application, wherein the first 第16頁 520562 六、申請專利範圍 二電阻為一p型井電阻。 7. 如申請專利範圍第1項的電壓穩壓電路,其中上述之參 考電壓為一穩定之電壓值。 8. —種利用一井電阻分壓的電壓穩壓電路,其中至少包 含: 一第一掺雜區,該第一摻雜區位於一底材内且該第一 摻雜區連接一電源電壓,其中上述之底材為一 P型之底材 一第二摻雜區,該第二掺雜區位於該底材内且該第二 摻雜區連接一參考電壓; 一第三摻雜區,該第三摻雜區為該井電阻位於該底材 内且接觸該第一摻雜區與該第二摻雜區; 當該電源電壓突然增加時,該第三摻雜區會隨之擴大 ,以使該參考電壓為一穩定之電壓值; 一隔離區,該隔離區位於該第一摻雜區與該第二摻雜 區之間之該底材内,且位於該第三摻雜區之内;一第四摻 雜區,該第四摻雜區位於該底材内且位於該第二摻雜區之 一側;以及 一電阻,該電阻連接該第二摻雜區與該第四摻雜區。 9. 如申請專利範圍第8項的電壓穩壓電路,其中上述之第 一摻雜區為一 N型摻雜區。Page 16 520562 6. Scope of patent application The second resistor is a p-well resistor. 7. The voltage regulator circuit of item 1 in the scope of patent application, wherein the above reference voltage is a stable voltage value. 8. A voltage stabilizing circuit using a well resistance voltage divider, which at least comprises: a first doped region, the first doped region is located in a substrate, and the first doped region is connected to a power supply voltage, The aforementioned substrate is a P-type substrate and a second doped region, the second doped region is located in the substrate and the second doped region is connected to a reference voltage; a third doped region, the The third doped region is that the well resistance is located in the substrate and is in contact with the first doped region and the second doped region; when the power supply voltage suddenly increases, the third doped region will expand accordingly, so that Making the reference voltage a stable voltage value; an isolation region located in the substrate between the first doped region and the second doped region and within the third doped region A fourth doped region, the fourth doped region is located in the substrate and on one side of the second doped region; and a resistor is connected between the second doped region and the fourth doped region Area. 9. The voltage regulator circuit according to item 8 of the patent application, wherein the first doped region is an N-type doped region. 第17頁 520562 六、申請專利範圍 1 0.如申請專利範圍第8項的電壓穩壓電路,其中上述之第 二摻雜區為一 N型摻雜區。 1 1.如申請專利範圍第8項的電壓穩壓電路,其中上述之第 三摻雜區為一 N型井區。 1 2.如申請專利範圍第8項的電壓穩壓電路,其中上述之第 四摻雜區為一 P型摻雜區。 1 3.如申請專利範圍第8項的電壓穩壓電路,其中上述之隔 離區為淺渠溝隔離區。 1 4.如申請專利範圍第8項的電壓穩壓電路,其中上述之隔 離區為場氧化區。 1 5.如申請專利範圍弟8項的電壓穩壓電路,其中上述之隔 離區可以一第五推雜區取代。 1 6.如申請專利範圍第8項的電壓穩壓電路,其中上述之第 二電阻為一井電阻。 1 7.如申請專利範圍第1 6項的電壓穩壓電路,其中上述之 第二電阻為一N型井電阻。Page 17 520562 6. Scope of patent application 10. The voltage regulator circuit according to item 8 of the patent application scope, wherein the second doped region is an N-type doped region. 1 1. The voltage regulator circuit according to item 8 of the patent application, wherein the third doped region is an N-type well region. 1 2. The voltage regulator circuit according to item 8 of the patent application, wherein the fourth doped region is a P-type doped region. 1 3. The voltage regulator circuit according to item 8 of the scope of patent application, wherein the above-mentioned isolation area is a shallow trench isolation area. 1 4. The voltage regulator circuit according to item 8 of the scope of patent application, wherein the above-mentioned isolation region is a field oxidation region. 1 5. The voltage regulator circuit according to item 8 of the scope of the patent application, wherein the above-mentioned isolation region can be replaced by a fifth miscellaneous region. 1 6. The voltage regulator circuit according to item 8 of the scope of patent application, wherein the second resistor is a well resistance. 1 7. The voltage regulator circuit according to item 16 of the patent application scope, wherein the second resistor is an N-well resistor. 六、申請專利範圍 如申請專利範圍第1R s 第二電阻為~P型井㊁:項的電壓穩壓電路,其中上述之 一種利用兩井雷阻八^ 含: 刀壓的電壓穩壓電路,其中至少包 ^ 弟 接雜區,該第一 摻雜區連接一電源電壓,多雜區位於一底材内且該第一 且該第:摻雜區為一 型摻、雜中區上述之底材為一 N型之底材 弟一換雜區,該第—/σ 摻雜區連接—泉考電壓,雜區位於該底材内且該第二 摻雜區; ,、中上述之第二摻雜區為一 Ρ型 第—摻:Ρ ^雜區,忒第二摻雜區位於該底材内且接$ b ‘區與該第二摻雜區, &柯門且接觸该 P型井,之第一井電阻; 、中上述之第三摻雜區為一 當該電源電壓突然增加時,兮茧-协^广 大,,該參考電壓為一穩定之電f參雜區會隨之擴 第四摻雜區’該第四摻雜區位 弟二摻雜區之一側,苴中上p 於4底材内且位於該 區,· 之 〃迷之第四推雜區為一 N型摻雜 第—第五摻雜區,該第五摻雜區位於該第一换 其;Π區之間之該底Γ,且位於該第三㈣ϊ:該 士述之第五摻雜區為一N型摻雜區且接地·、之内, -第二井電阻’該第二井電阻連接該第二穆 :及區與該 第19頁 520562 六、申請專利範圍 第四摻雜區。 2 0.如申請專利範圍第1 9項的電壓穩壓電路,其中上述之 第五摻雜區可以一隔離區取代。 2 1.如申請專利範圍第1 9項的電壓穩壓電路,其中上述之 隔離區為淺渠溝隔離區。 2 2.如申請專利範圍第1 9項的電壓穩壓電路,其中上述之 隔離區為场氧化區。 2 3.如申請專利範圍第1 9項的電壓穩壓電路,其中上述之 第二電阻為一N型井電阻。 2 4.如申請專利範圍第1 9項的電壓穩壓電路,其中上述之 第二電阻為一 P型井電阻。6. The scope of patent application, such as the scope of the patent application, the first resistance is the voltage stabilization circuit of ~ P-type well: item, of which the above one uses the two-well lightning resistance ^ Including: the voltage regulator circuit of the knife voltage, The first doped region is connected to a power supply voltage, the first doped region is located in a substrate, and the first and the first: doped region is a type doped and doped middle region. The material is an N-type substrate. The impurity region is changed. The-/ σ doped region is connected to the spring test voltage. The impurity region is located in the substrate and the second doped region. The doped region is a P-type doped: P ^ doped region, the second doped region is located in the substrate and is connected to the $ b 'region and the second doped region, & Komen and contacts the P-type Well, the first well resistance; and the third doped region mentioned above is that when the power supply voltage suddenly increases, the cocoon-coupling is large, and the reference voltage is a stable electric f-parallel region. Expand the fourth doped region. 'The fourth doped region is located on one side of the second doped region. The upper p is in the 4 substrate and is located in this region. The doping region is an N-type doped fifth-fifth doped region, the fifth doped region is located in the first for the first doped region; the bottom Γ between the Π regions, and the third frame: The fifth doped region is an N-type doped region and is grounded. Within the second well resistance, the second well resistance is connected to the second well: the area and the page 520562. Four doped regions. 20. The voltage regulator circuit according to item 19 of the application, wherein the fifth doped region may be replaced by an isolation region. 2 1. The voltage regulator circuit according to item 19 of the patent application scope, wherein the above isolation area is a shallow trench isolation area. 2 2. The voltage regulator circuit according to item 19 of the scope of patent application, wherein the above-mentioned isolation region is a field oxidation region. 2 3. The voltage regulator circuit according to item 19 of the patent application scope, wherein the second resistor is an N-well resistor. 2 4. The voltage regulator circuit according to item 19 of the scope of patent application, wherein the second resistor is a P-well resistor. 第20頁Page 20
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906952B2 (en) 2009-01-14 2011-03-15 Prolific Technology Inc. Voltage regulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906952B2 (en) 2009-01-14 2011-03-15 Prolific Technology Inc. Voltage regulator

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