TW518732B - A semiconductor packaging process for ball grid array (BGA) - Google Patents
A semiconductor packaging process for ball grid array (BGA) Download PDFInfo
- Publication number
- TW518732B TW518732B TW090126348A TW90126348A TW518732B TW 518732 B TW518732 B TW 518732B TW 090126348 A TW090126348 A TW 090126348A TW 90126348 A TW90126348 A TW 90126348A TW 518732 B TW518732 B TW 518732B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- adhesive
- semiconductor packaging
- patent application
- packaging process
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
518732518732
【發明領域】 少 本發明係有關於一種球格陣列半導體封裝過程,胜… 击、關於一種點施或塗施黏膠黏著晶片與具窗口型態球牧 陣列基板之半導體封裝過程。 “。 【先前技術】 在美國專利案第6, 1 90, 943號「晶片尺寸封裝方法」 中’揭示一種窗口球格陣列半導體封裝結構(wind〇w」[Field of the Invention] The present invention relates to a ball grid array semiconductor packaging process. The invention relates to a semiconductor packaging process of a spot-applied or applied adhesive-bonded wafer and a window-type ball grazing array substrate. ". [Prior art] In" Paper Size Packaging Method "of US Patent No. 6, 1 90, 943," a window ball grid array semiconductor package structure (window) "is disclosed.
Ball Grid Array semiconductor package)及其封裝方 法’如第1圖所示,該半導體封裝結構2 〇主要包含一基板 22 (即具有窗口型態之球格陣列基板)、一晶片24、一封 膠體42、一熱塑性黏膠28、複數條金屬導線32及複數個焊 球44 ’其中該基板22係具有貫穿其上表面3〇及下表面38之 狹長狀窗口34,該晶片24之主動面26 (active surface ) 係以熱塑性黏膠28黏固於基板22之上表面30,該金屬導線 32係經由該窗口34電性連接晶片24與基板22,而該封膠體 4 2係形成於晶片2 4及窗口 3 4之周邊,以保護晶片2 4及金屬 導線32,另在該基板22之下表面38形成複數個呈矩陣排列 之烊球44 ’使該半導體封裝結構2〇成為「窗口球格陣列」 (即Window BGA )之半導體封裝結構。 上述半導體封裝結構2 0之封裝方法如下:一、提供一 基板22 ’该基板22係具有一上表面30、一下表面38及貫穿 該上表面3 0與該下表面3 8之窗口 3 4 ;二、以網板印刷 (stenci 1 ing )方式在該基板22之部份上表面3〇塗施一液 態之熱塑性黏膠28 (thermoplastic adhesive);三、將Ball Grid Array semiconductor package) and its packaging method 'As shown in FIG. 1, the semiconductor package structure 20 mainly includes a substrate 22 (ie, a ball grid array substrate with a window type), a wafer 24, and a colloid 42 A thermoplastic adhesive 28, a plurality of metal wires 32, and a plurality of solder balls 44 ', wherein the substrate 22 has an elongated window 34 penetrating the upper surface 30 and the lower surface 38, and the active surface 26 of the wafer 24 (active surface) is adhered to the upper surface 30 of the substrate 22 with a thermoplastic adhesive 28, the metal wire 32 is electrically connected to the wafer 24 and the substrate 22 through the window 34, and the sealant 4 2 is formed on the wafer 24 and the window The periphery of 3 to protect the chip 24 and the metal wire 32, and a plurality of balls 44 'arranged in a matrix are formed on the lower surface 38 of the substrate 22, so that the semiconductor package structure 20 becomes a "window ball grid array" ( That is, the semiconductor package structure of Window BGA. The packaging method of the above-mentioned semiconductor package structure 20 is as follows: 1. A substrate 22 is provided. The substrate 22 has an upper surface 30, a lower surface 38, and a window 3 4 penetrating the upper surface 30 and the lower surface 38. 2. 1. Apply a liquid thermoplastic adhesive 28 (stenci 1 ing) to the upper surface 30 of the substrate 22;
518732 五、發明說明(2) 該晶片24之主動面26接觸該基板22上之熱塑性黏膠28,使 得該晶片2 4主動面2 6之焊墊3 6係對應於該窗口 3 4 ;四、在 預定之溫度(1 9 0 °C )、壓力(3 9 0 g )及時間(五秒)之 狀態下,施壓加熱基板22與晶片24,使兩者黏合;五、以 打線(wire bonding )方式將該金屬導線32穿過該窗口34 電性連接晶片24之焊墊36與基板22之導接墊41 ;六、形成 一封膠體42於晶片24及窗口34之周邊;七、在該基板22之 下表面3 8植接複數個呈矩陣排列之焊球4 4。 藉由上述之步驟以製備半導體封裝結構2 〇 (即窗口球 格陣列封裝結構)’由於該熱塑性黏膠28係由網板印刷方 式塗施(步驟二)形成於基板2 2之部份上表面3 〇,在加熱 壓合晶片24與基板22時,該液態熱塑性黏膠28之流動不易 控制’且當塗施之膠量過多時,該液態之熱塑性黏膠28會 溢流並覆蓋至晶片24之焊墊36,導致打線失敗,因此該熱 塑性黏膠28之印刷塗施膠量必須精準控制,使其製造良率 仍低,而導致半導體封裝之信賴度嚴重降低,且在半導體 封裝產業中,該熱塑性黏膠28 (如一種無溶劑、彈性且半 2明之矽橡膠…等)係非大量生產及使用,故其成本亦較 咼,此外,此一習知封裴過程中晶片黏合方法係為加壓及 加熱同時進行(步驟四),然而要同時加壓及加熱之機台 較為複雜且成本亦較昂貴,亦提高了封裝製程成本。 【發明目的及概要】 本發明之主要目的在於提供一種球格陣列半導體封裝 過程,其係在基板之黏晶區上點施或塗施黏膠,然後先將 518732518732 V. Description of the invention (2) The active surface 26 of the wafer 24 contacts the thermoplastic adhesive 28 on the substrate 22, so that the pads 36 of the active surface 26 of the wafer 24 correspond to the window 3 4; At a predetermined temperature (190 ° C), pressure (390g), and time (five seconds), the substrate 22 and the wafer 24 are heated under pressure to bond the two together; five, wire bonding ) Method to pass the metal wire 32 through the window 34 to electrically connect the solder pad 36 of the wafer 24 and the conductive pad 41 of the substrate 22; 6. form a gel 42 on the periphery of the wafer 24 and the window 34; The lower surface 3 8 of the substrate 22 is implanted with a plurality of solder balls 4 4 arranged in a matrix. Through the above steps, a semiconductor package structure 20 (that is, a window ball grid array package structure) is prepared. Since the thermoplastic adhesive 28 is applied by screen printing (step 2), it is formed on a part of the upper surface of the substrate 22 30. When the wafer 24 and the substrate 22 are heated and pressed, the flow of the liquid thermoplastic adhesive 28 is not easy to control. When the amount of the applied glue is too much, the liquid thermoplastic adhesive 28 will overflow and cover the wafer 24. The solder pad 36 leads to the failure of wire bonding. Therefore, the amount of printing and application of the thermoplastic adhesive 28 must be accurately controlled, so that its manufacturing yield is still low, and the reliability of semiconductor packaging is severely reduced. In the semiconductor packaging industry, The thermoplastic adhesive 28 (such as a solvent-free, flexible, semi-bright silicone rubber, etc.) is not mass-produced and used, so its cost is relatively high. In addition, the conventional method of wafer bonding during the sealing process is: Pressing and heating are performed at the same time (step 4). However, the machine to be pressurized and heated at the same time is more complicated and costly, and it also increases the cost of the packaging process. [Objective and Summary of the Invention] The main object of the present invention is to provide a ball grid array semiconductor packaging process, which is to apply or apply adhesive on the die-bonding area of the substrate, and then apply 518732 first.
晶片加壓以黏合於基板上,並加熱使該黏膠固化,而使晶 片緊密黏合於基板上,即使在後續之高溫固化而形成封^ 體時,亦旎緊密結合晶片與基板,此外,在點施或塗施黏 膠時,其膠量易控制,達到在不需額外增加材料成本的^ 況下增進半導體封裝之良率。 本發明之次要目的在於提供一種球袼陣列半導體封裝 j,,其係在半導體封裝產業中,該上述之黏膠係為一種 環氧膠(epoxy adhesive)或銀膠(Ag — epoxy adhesive )···等熱固性或熱塑性之黏膠,其在半導體封裝產業中 係為大量生產及使用,故其成本較低,且該球格陣列半導 體封裝過程係先加壓後再加熱,而不須使用成本較昂貴之 可同時加壓加熱之機台,故降低製程成本。 、、 上述之半導體封裝過程,其係在基板之黏晶區點施或 塗施上述之黏膠,然後將晶片之主動面(active surface )黏貼至該基板之黏晶區,再執行加熱使該黏膠固化,而 使晶片緊密黏合於基板上,而後進行打線及封膠,在以壓 模方式(molding)、印刷(printing)或點注(p〇tting ) 專方式封膠時’以高溫固化而形成結合性良好之封膠 體,亦能緊密結合晶片與基板,故此半導體封裝過程係能 增進半導體封裝信賴度及降低製程成本。 【發明詳細說明】 請參閱所附圖式,本發明將列舉以下之實施例說明: 在本發明之一具體實施例中,第2a圖至第2e圖係為一 球格陣列(ball grid array,以下簡稱BGA)半導體封裝The wafer is pressurized to adhere to the substrate, and the adhesive is cured by heating, so that the wafer is tightly adhered to the substrate. Even when the subsequent high-temperature curing forms a seal, the wafer and the substrate are tightly combined. In addition, When applying or applying adhesive, the amount of glue is easy to control, and the yield of the semiconductor package can be improved without additional material cost. A secondary object of the present invention is to provide a ball-shaped array semiconductor package j, which is used in the semiconductor packaging industry. The above-mentioned adhesive is an epoxy adhesive or silver adhesive (Ag — epoxy adhesive) · ·· Such thermosetting or thermoplastic adhesives are mass-produced and used in the semiconductor packaging industry, so their cost is low, and the ball grid array semiconductor packaging process is pressurized and then heated without using costs. The more expensive machine can be pressurized and heated at the same time, so the process cost is reduced. The aforementioned semiconductor packaging process is to apply or apply the above-mentioned adhesive to the die attach area of the substrate, and then paste the active surface of the wafer to the die attach area of the substrate, and then perform heating to make the The adhesive is cured, so that the wafer is tightly adhered to the substrate, and then wire bonding and sealing are performed. When the sealing is performed in a molding, molding, or potting method, the adhesive is cured at a high temperature. The formation of a good sealant can also tightly combine the wafer and the substrate. Therefore, the semiconductor packaging process can improve the reliability of the semiconductor packaging and reduce the manufacturing cost. [Detailed description of the invention] Please refer to the attached drawings. The present invention will enumerate the following embodiments: In a specific embodiment of the present invention, Figures 2a to 2e are a ball grid array, (Hereinafter referred to as BGA) semiconductor package
第7頁 518732 五、發明說明(4) 過程實施步驟之截面示意圖,第3圖係為以塗膠方式塗施 黏膠後之頂視圖’第4圖係為一 B G A封裝結構之截面圖。 如第4圖所示,該BGA封裝結構1 〇〇主要係包含一晶片 110、一封膠體120、一黏膠130、一基板140、複數條金屬 導線150及複數個焊球160,其中該基板14〇係具有貫穿其 上表面144與下表面145之窗口 146,該晶片11〇之主動面 111 (active surface)係黏固於該基板14〇之上表面 144 ’該金屬導線150係以打線方式(wire bonding)穿過 該窗口146電性連接晶片110與基板140,該封膠體120係用 以密封該晶片110及金屬導線150,以保護晶片11〇及金屬 導線150免受外界環境之侵害,另在該基板14〇之下表面 145形成複數個呈矩陣排列之焊球1 60,該焊球160之材料 係為船錫合金…等,使其成為球格陣列(即)封裝結 構。 上述之BGA封裝結構100之封裝過程詳述如下: 首先如第2a圖所示,首先提供一基板140,該基板14〇 係具有一上表面144及下表面145,其中該基板140之上表 面1 4 4係具有至少一黏晶區1 4 8,該黏晶區1 4 8係具有至少 一貫穿該基板140上表面144及下表面145之窗口 146,而該 基板140之下表面145係形成一電路層143,該電路層143係 具有金屬線路(圖未繪出)及複數個位於窗口 146周邊之 導接墊142 (contact pad),其中該金屬線路(圖未綠出 )係用以導接焊球1 6 0,而該導接塾1 4 2係用以焊接金屬導 線 1 5 0 〇Page 7 518732 V. Description of the invention (4) A schematic cross-sectional view of the implementation steps of the process. Figure 3 is a top view after the adhesive is applied by means of adhesive coating. 'Figure 4 is a cross-sectional view of a B G A package structure. As shown in FIG. 4, the BGA package structure 100 mainly includes a chip 110, a gel 120, an adhesive 130, a substrate 140, a plurality of metal wires 150, and a plurality of solder balls 160, wherein the substrate The 14o series has a window 146 penetrating the upper surface 144 and the lower surface 145 thereof. The active surface 111 of the wafer 11 is adhered to the upper surface 144 of the substrate 14 and the metal wire 150 is wired. (Wire bonding) The chip 110 and the substrate 140 are electrically connected through the window 146. The sealing body 120 is used to seal the chip 110 and the metal wire 150 to protect the chip 110 and the metal wire 150 from the external environment. In addition, a plurality of solder balls 1 60 arranged in a matrix are formed on the lower surface 145 of the substrate 14. The material of the solder balls 160 is a ship tin alloy, etc., which makes it a ball grid array (ie) packaging structure. The packaging process of the above BGA packaging structure 100 is detailed as follows: First, as shown in FIG. 2a, a substrate 140 is first provided. The substrate 140 has an upper surface 144 and a lower surface 145, and the upper surface 1 of the substrate 140 is provided. The 4 4 series has at least one sticky crystal region 1 4 8, the sticky crystal region 1 4 8 has at least one window 146 penetrating the upper surface 144 and the lower surface 145 of the substrate 140, and the lower surface 145 of the substrate 140 forms a The circuit layer 143 has a metal circuit (not shown in the figure) and a plurality of contact pads 142 (contact pads) located around the window 146. The metal circuit (not shown in the figure) is used for conducting connections. The solder ball 1 6 0, and the lead 塾 1 4 2 are used to solder the metal wire 1 5 0 〇
518732 五、發明說明(5) 再如第2b圖所示,以點膠機170 (dispenser)在基板 1 4 0上表面1 4 4之黏晶區1 4 8以點膠方式點施黏膠1 3 0,或如 第3圖所示’其係以塗膠方式在基板1 4 0之黏晶區1 4 8塗施 黏膠1 3 0 ’其中該黏膠1 3 0係為環氧膠(epoxy adhesive) 或銀膠(Ag - epoxy adhesive)···等熱固性或熱塑性之黏 膠。 之後,如第2c圖所示,將複數個晶片1 1 〇之主動面1 i j 接觸該基板140之黏晶區148上之黏膠1 30,並施加預定壓 力使晶片11 0黏合於基板1 4 0上,而該晶片11 〇之焊塾11 2係 位於晶片11 0之主動面111之中間位置且位置對應該窗口 1 4 6,然後再以預定溫度加熱(約1 5 〇至丨7 5左右), 使該黏膠130固化,以使複數個晶片丨10緊密黏合於該基板 140 上。 然後,如第2d圖所示,將複數個晶片丨丨〇之焊墊丨丨2以 金屬導線150打線經由該基板140之窗口 146而電性連接至 該基板140之電路層143之導接墊142,再以壓模方式 (molding)、印刷(printing)或點注(p〇tting)…等 方式形成封膠體120,以密封複數個晶片丨1()及金屬導線 150,再以高溫(約150至18〇 〇c )固化而形成結合性良 好之封膠體120,並緊密結合晶片π〇與基板14〇。 最後’如第2e圖所示,在該基板14〇下表面145之電路 層1 4 3上植接複數個烊球丨6 〇,該焊球丨6 〇係呈矩陣排列, 使該基板140上形成複數個BGA封裝結構1〇〇 (其亦為窗口 球格陣列封裝結構),然後再切割基板丨4 〇,使複數個Μ a518732 V. Description of the invention (5) As shown in Fig. 2b, the glue sticking area 1 4 4 on the upper surface 1 4 4 of the substrate 1 4 0 is dispensed by the dispenser 170 (dispenser). 30, or as shown in FIG. 3, 'It is a method of applying an adhesive 1 3 0 to the crystallized region 1 4 8 of the substrate 1 4 0 by an adhesive method' wherein the adhesive 1 3 0 is an epoxy adhesive ( epoxy adhesive) or Ag (epoxy adhesive) ... and other thermosetting or thermoplastic adhesives. After that, as shown in FIG. 2c, the active surfaces 1 ij of the plurality of wafers 1 1 0 are brought into contact with the adhesive 1 30 on the die attach region 148 of the substrate 140, and a predetermined pressure is applied to make the wafers 1 10 adhere to the substrate 1 4 0, and the welding pad 11 2 of the wafer 11 〇 is located at the middle position of the active surface 111 of the wafer 11 0 and the position corresponds to the window 1 4 6 and then heated at a predetermined temperature (about 1 50 to 7 5 or so). ), The adhesive 130 is cured, so that the plurality of wafers 10 are tightly adhered to the substrate 140. Then, as shown in FIG. 2D, the plurality of wafers 丨 丨 pads 丨 2 are wired with metal wires 150 through the window 146 of the substrate 140 to be electrically connected to the conductive pads 143 of the circuit layer 143 of the substrate 140 142, and then forming a sealing compound 120 by molding, printing, or potting, etc., to seal a plurality of wafers 1 () and metal wires 150, and then by high temperature (about 150 to 1800c) is cured to form a sealant 120 with good adhesion, and tightly bond the wafer π0 and the substrate 14o. Finally, as shown in FIG. 2e, a plurality of ball 丨 6 〇 is planted on the circuit layer 1 4 3 of the lower surface 145 of the substrate 14, and the solder balls 6 〇 are arranged in a matrix, so that the substrate 140 is Form a plurality of BGA packaging structures 100 (which are also window ball grid array packaging structures), and then cut the substrate 4 to make a plurality of M a
518732 五 發明說明(6) 封裝結構100成為單一之封裝單元(如第4圖所示)。 在上述BGA封裝結構1〇〇之封裝過程中,由於該黏膠 3 0係以點膠機1 7 〇點施於基板1 4 〇上表面1 4 4之黏晶區η 8 $或以塗膠方式塗施於基板14〇之黏晶區148 ),其膠量易 控制,成本又低,達到在不需額外增加材料成本的狀況下 支曰進半導體封裝之良率,且在加熱固化黏膠丨3〇前,先加 壓使晶片110黏合於基板丨40上,再執行加熱,而該黏膠 1。30的固化溫度為15〇。〇至175。〇左右,當加溫15〇。〇至175 C左右時’該黏膠130會囱化而使晶片110緊密黏合於基板 1 4 0 ’而後進行打線及封膠,在封膠時係以壓模、印刷或 ,^ ·、··等方式灌注熱固性環氧樹脂,當灌注該熱固性環氧 樹脂並使其固化時之溫度為15〇至18〇它左右,且以高溫 固化而形成結合性良好之封膠體12〇,亦能緊密結合晶片 110與π基^板140 ’此外’在半導體封裝產業中’該黏膠130 (即%氧膠或銀膠…等)係為大量生產及使用,故在此半 ^體封裝過程中’該黏膠130係能低成本地大量使用,且 =BGΑ封裝結構1 〇〇之封裝過程係先執行加壓後,再執行加 熱’ ^需要習用之黏晶機與烘烤設備,而不須另行購置及 使用可同時加壓加熱之昂貴機台,故該可低成本地大量使 用之黏膠1 30及製程設備之通用性均降低了製程成本。 ;故本發明之保護範圍視後附之申請專利範圍所界定者 為準’任何熟知此項技藝者,在不脫離本發明之精神和範 圍内所作之任何變化與修改,均屬於本發明之保護範圍。 第ίο頁 518732 圖式簡單說明 【圖式說明】 第1圖:美國專利第6, 19〇, 943號「晶片尺寸封裝方法」 中’一 S 0 c封裝結構之截面圖; 第2 a圖·依本發明之一具體實施例,提供一基板後之截面 圖; 第2b圖·依本發明之一具體實施例,以點膠方式點施黏膠 後之截面圖; 第2 c圖依本發明之一具體實施例,黏貼晶片後之截面 圖; 第2d圖.依本發明之一具體實施例,打線及封膠後之截面 圖; 第2e圖·依本發明之一具體實施例,植接焊球後之截面 圖; 第3圖:依本發明之一具體實施例中,或以塗膠方式塗施 黏膠後之頂視圖;及 第4圖·依本發明之一具體實施例中,一 BGA封裝結構之 截面圖。 【圖號說明】 20 半導體封裝結構 22 基板 24 晶片 26 主動面 28 熱塑性黏膠 30 上表面 32 金屬導線 34 40 窗口 導電層 36 焊墊 38 下表面 41 導接墊 42 封膠體 44 焊球518732 V Description of the invention (6) The packaging structure 100 becomes a single packaging unit (as shown in Figure 4). During the above-mentioned packaging process of the BGA package structure 100, the adhesive 30 was applied to the substrate 14 14 with the adhesive region η 8 $ on the upper surface 1 4 4 of the substrate 1 170 by a dispenser, or by gluing. The method is applied to the die-bonding region 148 of the substrate 14). Its glue amount is easy to control and its cost is low. It can reach the yield of semiconductor packaging without additional material cost and cure the glue by heating. Before 30, the wafer 110 is first pressed to adhere to the substrate 40, and then heating is performed, and the curing temperature of the adhesive 1.30 is 150. 〇 to 175. 〇 or so, when warming up 15 〇. 〇 to 175 C or so 'the adhesive 130 will chimney and the wafer 110 is tightly adhered to the substrate 1 4 0', and then wire bonding and sealing are performed, and the sealing is performed by stamping, printing or ... The thermosetting epoxy resin is poured in other ways. When the thermosetting epoxy resin is poured and cured, the temperature is about 150 to 180 °, and it is cured at high temperature to form a good sealant 12 °, which can also be tightly bonded. The wafer 110 and the π-based substrate 140 are also used in the semiconductor packaging industry. The adhesive 130 (that is,% oxygen adhesive or silver adhesive, etc.) is mass-produced and used. Adhesive 130 can be used in large quantities at low cost, and the encapsulation process of = BGA package structure 1000 is performed after pressing and heating. ^ Need to use a conventional die attaching machine and baking equipment without purchasing separately And the use of expensive machines that can be heated under pressure at the same time, so the low cost and large use of adhesive 130 and the versatility of the process equipment have reduced process costs. Therefore, the scope of protection of the present invention is subject to the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention are protected by the present invention. range. Page 518 732 Brief description of the drawings [Illustration of the drawings] Figure 1: Sectional view of the '-S 0 c package structure in US Patent No. 6, 19〇, 943 "Chip Size Packaging Method"; Figure 2 a · According to a specific embodiment of the present invention, a cross-sectional view after a substrate is provided; FIG. 2b. According to a specific embodiment of the present invention, a cross-sectional view after the adhesive is applied by a dispensing method; FIG. 2c is according to the present invention. A specific embodiment, a cross-sectional view after the wafer is pasted; FIG. 2d. According to a specific embodiment of the present invention, a cross-sectional view after wire bonding and sealing; FIG. 2e. According to a specific embodiment of the present invention, a plant connection Cross-section view after solder ball; Figure 3: Top view in accordance with one embodiment of the present invention, or after application of adhesive by means of glue coating; and Figure 4: In a specific embodiment of the present invention, A cross-sectional view of a BGA package structure. [Illustration of drawing number] 20 semiconductor package structure 22 substrate 24 chip 26 active surface 28 thermoplastic adhesive 30 upper surface 32 metal wire 34 40 window conductive layer 36 solder pad 38 lower surface 41 lead pad 42 sealing body 44 solder ball
518732 圖式簡單說明 100 BGA封裝結構 110 晶片 111 主動面 112 焊墊 120 封膠體 130 黏膠 140 基板 142 導接墊 143 電路層 144 上表面 145 下表面 146 窗口 148 黏晶區 150 金屬導線 160 焊球 170 點膠機518732 Brief description of the diagram 100 BGA package structure 110 Chip 111 Active surface 112 Solder pad 120 Sealant 130 Adhesive 140 Substrate 142 Leading pad 143 Circuit layer 144 Upper surface 145 Lower surface 146 Window 148 Sticky region 150 Metal wire 160 Solder ball 170 Dispenser
第12頁Page 12
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090126348A TW518732B (en) | 2001-10-22 | 2001-10-22 | A semiconductor packaging process for ball grid array (BGA) |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090126348A TW518732B (en) | 2001-10-22 | 2001-10-22 | A semiconductor packaging process for ball grid array (BGA) |
Publications (1)
Publication Number | Publication Date |
---|---|
TW518732B true TW518732B (en) | 2003-01-21 |
Family
ID=27801557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090126348A TW518732B (en) | 2001-10-22 | 2001-10-22 | A semiconductor packaging process for ball grid array (BGA) |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW518732B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101673720B (en) * | 2008-09-12 | 2011-07-20 | 力成科技股份有限公司 | Window-type semiconductor package structure that avoids delamination at the mold flow inlet |
US8592258B2 (en) | 2007-12-27 | 2013-11-26 | United Test And Assembly Center, Ltd. | Semiconductor package and method of attaching semiconductor dies to substrates |
-
2001
- 2001-10-22 TW TW090126348A patent/TW518732B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8592258B2 (en) | 2007-12-27 | 2013-11-26 | United Test And Assembly Center, Ltd. | Semiconductor package and method of attaching semiconductor dies to substrates |
CN101673720B (en) * | 2008-09-12 | 2011-07-20 | 力成科技股份有限公司 | Window-type semiconductor package structure that avoids delamination at the mold flow inlet |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100286591B1 (en) | Semiconductor integrated circuit device and its manufacturing method | |
TW546795B (en) | Multichip module and manufacturing method thereof | |
CN101221946B (en) | Semiconductor package and method for manufacturing system-in-package module | |
US7037756B1 (en) | Stacked microelectronic devices and methods of fabricating same | |
US20020109216A1 (en) | Integrated electronic device and integration method | |
TW200409252A (en) | Packaging process for improving effective die-bonding area | |
US20070080435A1 (en) | Semiconductor packaging process and carrier for semiconductor package | |
TW518732B (en) | A semiconductor packaging process for ball grid array (BGA) | |
US20080265393A1 (en) | Stack package with releasing layer and method for forming the same | |
CN101656246B (en) | Chip stack packaging structure with substrate with opening and packaging method thereof | |
CN101635280B (en) | Window type ball grid array package structure and manufacturing method thereof | |
JP5222508B2 (en) | Manufacturing method of semiconductor device | |
CN101241902A (en) | Multi-chip semiconductor package and manufacturing method thereof | |
TWI382506B (en) | Method and structure of multi-chip stack having central pads with upward active surfaces | |
TWI250597B (en) | Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips | |
TW200836306A (en) | Multi-chip stack package | |
CN201134426Y (en) | Chip packaging structure | |
JP4020594B2 (en) | Manufacturing method of semiconductor device | |
JP5234703B2 (en) | Manufacturing method of semiconductor device | |
TW200532873A (en) | Process for packaging and stacking multiple chips with the same size | |
TWI360852B (en) | Method for cutting and molding in small windows an | |
JPH0982846A (en) | Resin-sealed semiconductor device, manufacture thereof and lead frame to be used for that | |
TW200818442A (en) | Chip-on-film package to prevent voids resulted from film collapse | |
TW488046B (en) | A process for packaging a window BGA to improve the efficiency of forming solder balls | |
CN106784241A (en) | Chip on board method for packing and chip on board package system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |