TW497225B - Method for preventing polysilicon stringer in memory device - Google Patents

Abstract

In accordance with the present invention, a method for preventing polysilicon stringers in memory devices is disclosed. The key aspect of the present invention is the formation of a floating gate structure with multi-level oxidation rates the lower portion of the floating gate structure the higher oxidation rate, such as a floating gate structure with two polysilicon layers of different doping concentration or crystallinity the lower polysilicon layer the higher doping concentration, or the lower polysilicon layer the higher crystallinity. Therefore, in a later oxidation process a desired profile of the floating gate structure for etch process defining word lines is formed, that is from lower portion to higher portion of the floating gate structure an increasing width profile is formed. The width of the upper portion of the floating gate structure is bigger than that of the lower portion of the floating gate structure. Thus, the anisotropic etching process of isolating the word lines maintains an ideal etching result, in other words, the polysilicon stringers in the etched region which short out the word lines is eliminated.

Description

497225 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for avoiding the formation of polycrystalline silicon longitudinal beams on a memory element, in particular to a method for forming a floating gate structure with multiple oxidation rates to avoid A method for planarizing a memory cell to form a polycrystalline silicon stringer. 5-2 Background of the Invention: In data processing systems, memory components are of great importance for data storage. The well-known memory elements include, for example, random access memory (RAM), read-only memory (ROM), and other memory elements. Among them, non-volatile memory elements, especially commonly known as "flash memory (f 1 ash)" memory elements, are increasingly used in data storage applications. Generally, a flash memory cell array is formed on a semiconductor substrate in a series of columns and rows, and data is accessed via conductors of so-called word lines and bit lines. The first figure shows a top view of a part of the memory array 10. The second figure is a cross-sectional view taken along line 2-2 of the first figure. The general flash memory array layout is shown in the first figure, and the cross-section of the flash memory cell 100 structure is mostly shown in the second figure. Referring to the first and second figures, a method for forming each memory cell 100 on the semiconductor substrate 100 is as follows. Form source 110 and drain regions

497225 V. Description of the invention (2) Domain 1 12 and a channel between the source 1 10 and the drain 1 12 region. A channel oxide layer 1 1 4 or a gate dielectric layer (not shown in the first figure) is formed on the substrate 1 01 to connect the first polycrystalline silicon layer 1 16 or the floating gate layer to the source electrode. The I 1 0 and drain 1 12 regions are separated. The control gates 1 2 0 of individual cells are combined with the cell columns in a horizontal column manner to share a common word line (WL) 1 2 0. In other words, the second polycrystalline silicon layer 12 or the control gate layer is formed on the floating gate layer II 6 and is made of, for example, a silicon oxide / silicon nitride / silicon oxide (ONO) polysilicon dielectric layer 11 8 ( (Not shown in the first figure). Adjacent memory elements along the word lines are isolated by field oxide regions 102. In addition, for the purpose of improving the coupling ratio (c 0u ρ 1 ingrati 〇), an additional polycrystalline silicon layer 12 can be formed between the floating gate layer Π 6 and the polycrystalline silicon inner dielectric layer 1 1 8 to add The surface area of the large floating gate electrode 6 and the dielectric layer 1 2 2 are used as the isolation between the floating gate layers 116, as shown in FIG. 3A. FIG. 3A is a cross-sectional view of a unit cell with an improved floating gate structure, which is similar to the cross-sectional view taken along the tangent line 3-3 of the first figure. That is, when manufacturing a flash memory cell similar to the first figure, an extra layer of polycrystalline silicon is added to the floating gate layer. A strip-shaped first polycrystalline silicon layer 1 1 6 (or a first floating gate layer) is formed between the two field oxidation regions of the substrate 1 0 1 and is separated from the substrate 1 0 1 by a channel oxide layer 1 1 4 . In order to simplify the illustration, the field oxidation regions are not shown in the figure. Then, an oxidation process is performed to form a dielectric layer 1 2 2 to isolate the first polycrystalline silicon layers 116 adjacent to each other in a stripe shape. A second polycrystalline silicon layer 1 2 4 (a second floating gate layer) is formed on the first polycrystalline silicon layer 1 1 6. Next, an inner polycrystalline silicon dielectric layer 118 and a control gate layer 120 are formed to complete the fabrication of the memory cell. Public week

Page 7 497225 5. Description of the invention (3) It is known that it is very difficult to achieve perfect vertical contour control when manufacturing semiconductor components, especially the control of vertical contour after subsequent multiple oxidation processes is even more difficult to control. Because in the oxidation process, polycrystalline silicon near the surface usually has a faster oxidation rate than polycrystalline silicon far from the surface. Therefore, since the anisotropic etching process of the first floating gate layer 116 does not completely produce an ideal anisotropic profile, the vertical contour of the strip-shaped first floating gate layer 1 1 6 is controlled only to be approximately ideal status. Furthermore, after the subsequent oxidation process of forming the dielectric layer 12 2 and forming the polycrystalline silicon inner dielectric layer 1 18 such as the ONO layer, the inclined sidewalls of the floating gate layer 116 can no longer be ignored. When forming an array layout similar to the first figure, complex oxidation processes and non-idealized vertical contours can cause problems with polycrystalline silicon stringers. Because if the vertical perimeter of the floating gate is imperfect, when a memory cell is defined along the character line, a polycrystalline silicon stringer will be generated when the floating gate is etched. Furthermore, due to the formation of undesired vertical contours, the fault tolerance of the process is reduced, causing reliability problems, that is, loss of yield. When a part of the control gate layer 120 is anisotropically etched to form each character line in the memory element, a floating gate layer (about as shown in the first figure) Area 110), anisotropic etching is also performed at the same time to avoid short circuits between adjacent word lines. However, anisotropic etching cannot provide idealized anisotropic contours repeatedly, and the subsequent oxidation process makes it difficult to control the anisotropic contours of floating gates with inclined sidewalls. The non-idealized anisotropic etching contour results in the residue of the polycrystalline silicon gate layer 1 16, that is, the polycrystalline silicon stringer 1 2 6, such as the third B

Page 8 497225 V. Description of the invention (4) Figure. That is, when the floating gate layer 1 16 is sequentially etched, the inclined sidewalls are protected by the dielectric layer 1 2 2, and as a result, the polycrystalline silicon longitudinal beam 1 2 6 is generated. As shown in the fourth figure, it is a perspective view of the lower half of the etched area between the two bit lines. It can be clearly seen from the figure that the polycrystalline silicon stringer 1 2 6 generated in the etched area will cause the word lines to be short-circuited by the portions 1 2 8 and 1 3 0 respectively, causing reliability problems. That is, the etched areas do not completely isolate the word lines from each other at the areas 1 2 and 130. Instead, the polycrystalline silicon stringers 1 2 6 are bridged by the dielectric layer to protect the etched areas, which results in a gate-to-gate gap. Short circuit problem. Recently, a method of forming an inverted triangle polycrystalline silicon floating gate has been proposed. However, the etching process for forming the inverted polysilicon floating gate layer is very complicated and difficult to control, and it is not easy to debug through an appropriate online inspection step. However, when the technology of additional polycrystalline silicon layer is used to increase the surface area of the floating gate layer, the formation of a dielectric layer for isolation between the floating gate layers of the inverted triangle faces the problem of dielectric layer trench filling. Therefore, it is very necessary to avoid the formation of polycrystalline silicon stringers in the memory element and reduce the reliability problem caused by the shorting of the word lines. 0 5-3 Purpose and summary of the invention: In view of the above background of the invention, when traditionally forming a memory element Many shortcomings of the polycrystalline silicon stringer arise, and the object of the present invention is to provide a method for avoiding

Page 9 497225 V. Description of the invention (5) A method for forming a polycrystalline silicon stringer from a memory element. The main point of the present invention is to form a floating gate structure with multiple oxidation rates. The lower the floating gate structure, the higher the oxidation rate. For example, a floating gate structure is formed which has two polycrystalline silicon layers with different doping concentrations, or two polycrystalline silicon layers with different crystallinity, and the lower the polycrystalline silicon layer, the higher the doping concentration, or the lower polycrystalline silicon layer, the more its crystallinity. The higher. Therefore, in the subsequent oxidation process, the floating gate structure thus forms the contour required during the etching process, that is, a contour with an increasing width from the bottom of the floating gate structure is formed. The upper part of the floating gate structure is wider, and the lower part is narrower. Therefore, during the isotropic etching process of isolating the character lines, ideal contour control can be maintained, and the polycrystalline silicon stringers in the etched area that would cause the character line to short-circuit can be eliminated. Another object of the present invention is to provide a method for forming a polycrystalline silicon structure having a profile with increasing width, that is, the upper part of the polycrystalline silicon structure is wider and the lower part is narrower. It is still another object of the present invention to provide a multi-layered polycrystalline stone deposition method for controlling the vertical profile of a polycrystalline silicon layer etching process. According to the above-mentioned purpose, in a preferred embodiment, the present invention provides a method for avoiding the formation of polycrystalline silicon stringers in a memory device. The steps of the method of the present invention include at least forming a conductor structure with a vertical profile on a substrate, wherein the conductor structure includes at least two conductor layers each having a different oxidation rate, and these conductor layers vary from large to small according to the oxidation rate. order

Page 10 497225 V. Description of the invention (6) Arranged from the bottom up on the substrate. Then, an oxidation process such as a thermal oxidation process is performed on a part of the conductor structure, so that the vertical profile of the conductor structure is changed to a profile with an increasing width from the bottom to the top. The increasing profile of the conductor structure is helpful for the etching process control. The step of forming a conductor structure with a vertical profile at least includes forming a first conductor layer having a first oxidation rate on a substrate. Then, a second conductor layer having a second oxidation rate is formed on the first conductor layer, wherein the first oxidation rate is greater than the second oxidation rate. Next, a pattern-transferred photoresist is formed on the second conductor layer, and the pattern-transferred photoresist defines a conductor structure. Then, the photoresist of the pattern transfer is used as a mask, and the second conductor layer and the first conductor layer are anisotropically etched to form a conductor structure with a vertical outline, and the photoresist of the pattern transfer is removed. The first conductor layer is a first polycrystalline silicon layer having a first doping concentration, and the second conductor layer is a second polycrystalline silicon layer having a second doping concentration, wherein the first doping concentration is greater than the second doping concentration. concentration. The first conductor layer is a polycrystalline silicon layer, and the second conductor layer is an amorphous silicon layer. The method of the present invention further includes etching the conductor structure with increasing width to form a plurality of electrically isolated regions, thereby avoiding the formation of a conductor stringer. Detailed description of the invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents.

Page 11 497225 V. Description of the invention (7) The formation of a superimposed floating profile that re-oxidizes the crystallinity as soon as the doping rate is increased from the bottom line to the time domain will make the crystal concentration or the rate of polycrystalline Brake. It is also wide, and may be a polycrystalline silicon layer of a stringer or crystal in the embodiment of the character. The structure, that is, the degree is maintained to maintain a short circuit, the method of the present invention. Vietnam ’s silicon structure depends on the rate of oxidation. Through the follow-up, the wheel corridor of the present invention provides a well-known difference in the polycrystalline silicon engraved with the desired I. The oxidation rate is changed to a rate of σ. The obtained oxidation system provides a favorable result, and the faster the impurity concentration of the crystalline silicon layer is avoided due to the removal of seeds by the stringer. After different layers in a small order, the gate can float in the direction of the worm, and the memory of the oxidized Vietnam '. Therefore, the doping concentration forms the worm structure from the bottom, and the engraving process will be located at the body element rate due to the oxidation rate. The key points for the upward engraving which have the definition word I and the insect engraving area according to the method of the present invention will be described in conjunction with the fifth A to F charts. The cross-sectional views shown in Figs. 5A to 5F are similar to the tangential directions of the third picture. The formation of a flash memory cell similar to the third picture begins with the formation of field oxide regions on a semiconductor substrate such as a silicon substrate. The field oxidation region can be formed by using a region oxidation method (LOCOS) or a shallow trench isolation method (ST I). Referring to FIG. 5A, after forming a field oxidation region (not shown in the figure), a thin channel oxide layer 2 1 0 is formed on a silicon substrate 201 by a thermal oxidation process. Then, it is the main focus of the present invention to form a floating gate structure with multiple oxidation rates to facilitate the subsequent zigzag line isolation etching process.

Page 12 497225 V. Description of the invention (8) A first conductor layer 21 2 having a first oxidation rate is formed on the channel oxide layer 2 1 0. Then, a second conductor layer 2 1 4 having a second oxidation rate is formed on the first conductor layer 21 2, wherein the first oxidation rate is greater than the second oxidation rate. For example, the conductor layers of the polycrystalline silicon layers 2 1 2 and 2 1 4 can be formed by using a low pressure chemical vapor deposition (LPCVD) method, and different diffusion doping or ion implantation doping techniques are used to generate different doping concentrations or crystallinity. For example, in one embodiment, the first conductor layer is a first polycrystalline silicon layer 212 having a first doping concentration, and the second conductor layer is a second polycrystalline silicon layer 214 having a second doping concentration, wherein The first doping concentration is greater than the second doping concentration. That is, when a first polycrystalline silicon layer is formed, a gas dopant such as phosphine (PH 3) is added, and then the dopant gas is turned off to form an undoped second polycrystalline silicon layer 2 1 4. In addition, in another embodiment, the first conductor layer is a polycrystalline silicon layer 212, and the second conductor layer is an amorphous silicon layer 214. For example, a polycrystalline silicon layer 2 1 2 is formed at a higher temperature, and a non-crystalline non-crystalline silicon layer 2 1 4 is formed at a lower temperature. After forming the polycrystalline silicon layers 2 1 2 and 2 1 4, the two polycrystalline silicon layers are etched with an idealized anisotropy to form an electrically isolated region 2 1 8 (a first floating gate layer or a conductor structure). As shown in Figure 5B. The step of etching these two layers of conductor layers is to use the formed first pattern transfer photoresist 2 1 6 to define the conductor structure 2 1 8 and use it as an etching mask. After the etching is completed, the first pattern transfer photoresist 2 is removed. 1 6. In another embodiment, the step of forming the first floating gate layer (conductor structure) 2 1 8 includes at least forming a polycrystalline silicon layer, and then

Page 13 497225 V. Description of the invention (9) Enter the first doping concentration. A driver (d r i v e-i η) process is performed to drive the dopants into the lower layer of the polycrystalline silicon layer. Then, a second doping implantation is performed on the polycrystalline silicon layer, and the concentration is lower than the first doping concentration. Then through the pattern transfer process, a floating gate structure with multiple oxidation rates is formed, and the bottom part has an oxidation rate of Vietnam. Then, an oxidation process such as a thermal oxidation process is performed to form a lining oxide layer 2 2 0 on the conductor structure 2 18. Therefore, the vertical profile of the double-layered polycrystalline silicon structure 2 1 8 (the first floating gate layer) is changed from the bottom The profile (such as the shape of a torch) that increases in width to the previous one. In other words, due to the different oxidation rates, the lateral oxidation of the first polycrystalline silicon layer 2 1 2 is faster than the second polycrystalline silicon layer 2 1 4. The width of the second polycrystalline silicon layer 2 1 4 is wider than that of the first polycrystalline silicon layer 2 1 2. Next, an insulating layer 2 2 2 such as silicon dioxide is formed on the silicon substrate 201 to electrically isolate two adjacent first floating gate layers as shown in FIG. 5C. The method for forming the silicon dioxide layer 2 2 2 is, for example, a high-density plasma oxidation method, and a low-pressure TEOS (tetra-ethyl orthosilicate) method or a low-pressure O3 (ozone) -TEO S method. Then, the silicon dioxide layer 2 2 2 is planarized to expose the first floating gate layer 2 1 8, as shown in the fifth D diagram. The planarization step may be performed by, for example, a chemical mechanical polishing process or an etch-back process. Referring to the fifth figure E, in order to increase the coupling ratio, a third conductor layer 2 2 4 such as a third polycrystalline silicon layer is formed on the silicon dioxide layer 2 2 2 with an isolated polycrystalline silicon structure 2 1 2 to increase the floating gate. Surface area. Then, the third polycrystalline silicon layer 2 2 4 is etched with silver to form an electrically isolated region (second floating gate layer) 2 2 4 and

Page 14 497225 V. Description of the invention (ίο) Covers the isolated double-layered polycrystalline silicon structure 2 1 8. The step of etching the third polycrystalline silicon layer is to use the formed second pattern transfer photoresist (not shown) to define the second floating gate layer 2 2 4 as an etching mask. After the etching is completed, the second pattern transfer layer is removed. Photoresist. Therefore, a floating gate structure 2 2 6 having a profile with increasing width is formed, which includes a polycrystalline silicon layer 2 2 4 with an increased surface area and a double-layered polycrystalline silicon structure (first floating gate layer) 2 1 8. Then, an inner polycrystalline silicon dielectric layer 2 2 8 is formed on the third polycrystalline silicon layer 2 2 4. The inner polycrystalline silicon dielectric layer 2 2 8 is usually a silicon oxide / silicon nitride / silicon oxide (ONO) layer that completely covers the substrate 201. After that, a control gate layer 230 such as a fourth polycrystalline silicon layer is formed on the silicon oxide / silicon nitride / silicon oxide (ON0) layer to complete the stacking of the flash memory crystal package. After the formation of the control gate layer 230, due to the high etching selection ratio between the polycrystalline silicon layer and the silicon oxide layer, a self-aligned etching (SAE) process is used to define a plurality of word lines of the memory cell. The step of etching the control gate layer 230 is to use the formed third pattern transfer photoresist (not shown) to define the word line and use it as an etching barrier layer. After the etching is completed, the third pattern transfer photoresist is removed. The floating gate structures 2 2 6 located between adjacent word lines are also removed by anisotropic etching during etching. In the process of anisotropic etching of isolated word lines, since the width of the first floating gate layer 2 1 8 is increased in outline, the wider width of the second poly silicon layer 2 1 4 can be used to control the etching parameters to Produces ideal etching results, as shown in the fifth F diagram. In other words, the polysilicon stringers located in the etched areas that short the word lines can be eliminated because of the increasing width profile produced by the floating gate structure with multiple oxidation rates.

Page 15 497225 V. Description of the invention (11) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others that are completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below.

Page 497225 Brief description of the objects, features and advantages of the present invention can be clearly seen from the following detailed description and description of the drawings: The first diagram is a top view of a part of a memory array; the second diagram is along the first diagram A cross-sectional view of the unit cell of tangent line 2-2; Figure A is a cross-sectional view of a memory cell with an improved floating gate structure along the tangent line of the first figure 3-3 when the character line is traditionally formed; Figure B is a cross-sectional view of a memory cell with an improved floating gate structure along a tangent line similar to the first figure 3-3 when a polycrystalline silicon stringer is traditionally formed by a character line. The fourth figure is between two adjacent character lines of the traditional phase. Top view of the lower half of the etched area, which shows that the word lines are short-circuited due to the generation of polycrystalline silicon stringers; Figure 5A is the first pattern transfer photoresist when the flash memory cell of the present invention is formed with an improved floating gate A cross-sectional view of a multi-level floating gate is defined; FIG. 5B is a cross-sectional view of the present invention for forming a flash memory cell with an improved floating gate and forming a multi-level floating gate structure with multiple oxidation rates

Page 497225 Brief description of the fifth diagram c is a cross-sectional view of the multi-level floating gate structure oxidation process when the present invention forms a flash memory cell with an improved floating gate; the fifth D diagram is a rapid formation of the present invention. A cross-sectional view of a flash memory cell with an improved floating gate to flatten a multi-level floating gate structure; FIG. 5E is a diagram illustrating the formation of a flash memory cell with an improved floating gate after forming a third conductive layer Cross-sectional view; FIG. 5F is a cross-sectional view of the flash memory cell with the improved floating gate of the present invention, which defines the character line etching of the third conductor interlayer etching area after completion. Symbols of the main part ... 1 0 memory array 1 0 0 cell 1 0 1 substrate 1 0 2 field oxidation area 1 1 0 source 1 1 2 drain 1 1 4 channel oxide layer 1 1 6 floating gate Layer 1 1 8 polycrystalline silicon dielectric layer 1 2 0 control gate layer

Page 18 497225 Brief description of the drawings 1 22 Dielectric layer 1 2 4 Extra polycrystalline silicon layer 1 2 6 Polycrystalline silicon longitudinal beam 1 2 8 Etched area generated by the longitudinal beam 1 30 Etched area generated by the longitudinal beam 2 0 1 Substrate 2 1 0 Channel oxide layer 212 First conductor layer at first oxidation rate 214 Second conductor layer at second oxidation rate 2 1 6 Photoresist of first pattern transfer 2 1 8 First floating gate layer 2 2 0 Liner oxide layer 2 2 2 Insulating layer 2 2 4 Second floating gate layer 2 2 6 Floating gate structure 2 2 8 Polycrystalline silicon dielectric layer 2 3 0 Control gate layer

Claims (1)

497225 6. Application scope 1. A method for avoiding the formation of conductor longitudinal beams in the memory element, the steps at least include: forming a conductor structure with a vertical outline on a substrate, wherein the conductor structure includes at least two different The oxidation rate, the higher the bottom of the conductor structure, the higher the oxidation rate; and performing an oxidation process on part of the conductor structure, so that the vertical profile of the conductor structure is transformed into a profile with an increasing width from the bottom to the top, where the The increasing width profile of the conductor structure facilitates the etching process control. 2. The method according to item 1 of the patent application range, wherein the conductor structure includes at least a first conductor layer having a first oxidation rate and a second conductor layer having a second oxidation rate, wherein the first oxidation The rate is greater than the second oxidation rate. 3. The method according to item 2 of the patent application, wherein the step of forming the conductor structure with the vertical profile at least includes: forming the first conductor layer with the first oxidation rate on the substrate; forming the tool The second conductor layer of the second oxidation rate is on the first conductor layer, wherein the first oxidation rate is greater than the second oxidation rate; forming a first pattern transfer photoresist on the second conductor layer, wherein the The photoresist of the first pattern transfer defines the conductor structure; using the photoresist of the first pattern transfer as a mask, the second conductor layer and the first conductor layer are anisotropically etched to form the vertical contour Conductor structure; and Page 20 497225 6. Scope of patent application Remove the photoresist of the first pattern transfer. 4. The method of claim 3, wherein the first conductor layer is a first polycrystalline silicon layer having a first doping concentration. 5. The method according to item 4 of the patent application, wherein the second conductor layer is a second polycrystalline silicon layer having a second doping concentration, wherein the first doping concentration is greater than the second doping concentration . 6. The method according to item 3 of the patent application, wherein the first conductor layer described above is a polycrystalline stone layer. 7. The method according to item 6 of the patent application, wherein the second conductor layer is an amorphous stone layer. 8. The method according to item 1 of the patent application scope, wherein the step of performing the oxidation process at least includes performing a thermal oxidation process on part of the conductor structure. 9. The method of claim 1 in the scope of patent application further includes etching the conductor structure with the increasing width to form a plurality of electrically isolated areas so as to avoid the formation of conductors and longitudinal beams. 1 0. A method for avoiding the formation of a conductor stringer from a memory element, the steps of which include at least: 497225 6. The scope of the patent application forms a conductor structure with a vertical profile on a substrate, wherein the conductor structure includes at least two conductor layers each having a different oxidation rate, and the conductor layers are from large to small according to the oxidation rate. The order of the conductor structure is arranged on the substrate from bottom to top; and an oxidation process is performed on part of the conductor structure, so that the vertical profile of the conductor structure is transformed into a profile with an increasing width from the bottom to the top, where the conductor structure of the Increasing width contours help control the etching process. 1 1. The method according to item 10 of the scope of patent application, wherein the step of forming the conductor structure with the vertical profile at least includes: forming a first polycrystalline silicon layer with a first doping concentration on the substrate; Forming a second polycrystalline silicon layer with a second doping concentration on the first polycrystalline silicon layer, wherein the first doping concentration is greater than the second doping concentration; forming a first pattern transfer light Blocking on the second polysilicon layer, wherein the photoresist of the first pattern transfer defines the conductor structure; using the photoresist of the first pattern transfer as a mask, the second polysilicon is anisotropically etched Layer and the first polycrystalline silicon layer to form the conductive structure with the vertical outline; and removing the photoresist of the first pattern transfer. 1 2. The method according to item 10 of the scope of patent application, wherein the step of forming the conductive structure with the vertical profile at least includes: forming a polycrystalline layer on the substrate; Page 22 497225 6. The scope of the patent application forms an amorphous stone layer on the polycrystalline stone layer; forming a second pattern transfer photoresist on the amorphous silicon layer, wherein the second pattern transfer photoresist Define the conductor structure; use the photoresist transferred by the second pattern as a mask, and anisotropically etch the amorphous silicon layer and the polycrystalline silicon layer to form the conductor structure with the vertical outline; and remove the second pattern Photoresistance of transfer. 1 3. The method according to item 10 of the scope of patent application further comprises etching the conductor structure with the width increasing to form a plurality of electrically isolated regions so as to avoid the formation of a conductor stringer. 1 4. A method of forming a memory element without a conductor beam, the steps at least include: providing a broken substrate; forming a channel oxide layer on the substrate; forming a first substrate having a first oxidation rate A conductor layer on the channel oxide layer; forming a second conductor layer with a second oxidation rate on the first conductor layer, wherein the first oxidation rate is greater than the second oxidation rate; forming a first pattern transfer Photoresist on the second conductor layer, wherein the photoresist of the first pattern transfer defines a plurality of conductor structures; using the photoresist of the first pattern transfer as a mask, the second conductor is anisotropically etched Layer and the first conductor layer to form the vertical conductors P.23 497225 VI. The scope of the application for patented light-blocking transfer 45— Blueprint-No. 1 •, 2 = Mouth structure removes the knotted conductor, and the control profile changes the rotation to cause corrosion to be passed on, The degree-assisted structure widens the structure of the upper part of the structure, and the bottom part is increased. The structure of the structure is wider than the structure of the structure. In the middle of the system, make some of this 0-barrier electricity to use the upper layer to conduct the second layer at the edge of the layer-forming the first Hai = mouth exposed storm to eliminate the layer by the edge of the layer •, / 1 ;; the first layer of the above layer is conductive to the dielectric resistance of the second layer of the second layer of the transfer to the volume of the layer map of the electric layer of the first three of the first ^ into a shape A, which should be etched And to • "Isometric non-element" subtitle cover number is the meaning of complex resistance one light out, the second one of the light map of the transposition case, the second one of the case, and the second layer body guide of this case, the second layer body guide The second layer of the dielectric and the dielectric element, the "sub-layer body should lead into a three-shaped Body Guide-The first description of the above middle-level silicon-crystal method of multi-party one of the 4 of 1 1-| Degrees of the thick range and mixed range of doping a special application, please apply as one. It is 5 r-Η The second one is described above, the middle layer is silicon, and the crystal method is the second best. The degree of the item is 1 degree thick, the first impurity is mixed, the second impurity is mixed, the second is special, the first should be applied, and the first is to be applied. Page 497225 Page 25