484137 A7 B7 6622twf.doc/008 五、發明說明（(） 本發明是有關於一種積體電路之寬導線結構，且特 別是有關於一種記憶體之寬導線構裝。 在現今之積體電路之外觀逐漸縮小之際，隨之而來 的內部所包裹之金屬連線，也進一步的細微化，而此對電 路之效能產生負面的衝擊，顯著地降低晶片的效能。其中， 過度細微化的導線嚴重影響電源匯流排與接地匯流排之壓 降，也會產生關鍵訊號路徑的電阻-電容遲緩(RC delay)與 雜訊等問題。 請參照第1圖，其繪示習知記憶體結構示意圖。習 知記憶體之電路晶片1〇〇之製作，係將多個記憶體輸出電 路單元102、一輸出延遲電路單元104(output delay circuit)、一 記憶體時脈電路單元 106(memory clock)、一 電源匯流排108、一接地匯流排110、多個分支電源導線 112、多個分支接地導線114、多個輸出訊號導線116、多 個控制導線118、一時脈導線直接120完成於晶片100內， 而晶片100之表面具有一保護層118(Passivation layer)， 而保護層122暴露出電源焊墊124、接地焊墊126以及訊 號焊墊128。並且多個記憶體輸出電路單元102分別具有 一電源端130、一接地端132、一訊號端134、一控制端136。 其中，電源焊墊124與電源匯流排108電性連接，而電源 匯流排108與多個分支電源導線112電性連接，並且多個 分支電源導線112又分別與多個記憶體輸出電路單元102 之電源端130電性連接，因此使電源從電源焊墊124傳送 到多個記憶體輸出電路單元102之電源端130;接地焊墊 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------裝--------訂---------^9 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 484137 6622twf.doc/008 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（v) 126與接地匯流排110電性連接，而接地匯流排110與多 個分支接地導線114電性連接，並且多個分支接地導線114 又與多個記憶體輸出電路單元102之接地端132電性連 接；多個訊號焊墊128透過多個輸出訊號導線116分別與 多個記憶體輸出電路單元102之訊號端134電性連結，以 傳輸多個記憶體輸出電路單元102之訊號至訊號焊墊 128 ;而記憶體時脈電路單元106透過時脈導線120與輸 出延遲電路單元104電性連接；輸出延遲電路單元104透 過多個控制導線118分別與記憶體輸出電路單元102之控 制端136電性連接。在記憶體晶片內之導線所用之材料主 要爲鋁合金或鋁，並且在記憶體晶片內之薄膜導線的線寬 極小，使得當電流過大的時候，容易產生雜訊與電阻-電 容遲緩等問題。上述之問題對記憶體晶片造成嚴重的影 響，因爲在習知記憶體晶片100內之電源匯流排108與接 地匯流排110的線寬極細，使得電源匯流排108與接地匯 流排110無法有效率地驅動所有的記憶體輸出電路單元 102 〇 對於記憶體晶片而言，讀取一筆資料通常需要多個 記憶體輸出電路單元102來達成，爲加快讀取速度，常希 望這些動作是同步進行。然而，當資料量變大時，比如同 時需要讀取多個位元時，則會造成電源匯流排108與接地 匯流排110突然產生大量電流，而造成雜訊及讀取的錯誤。 因此習知係利用輸出延遲電路單元104來控制驅動多個記 憶體輸出電路單元102,而驅動的頻率透過記憶體時脈電 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝------丨丨訂------- (請先閱讀背面之注意事項再填寫本頁) 484137 6622twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（57) 路單元106來控制，而將資料批次(batch)進行讀取，一次 驅動較少記憶體輸出電路單元102，以避免過大電流。此 種作法實在不具效率性，並且電路的設計趨於複雜而增加 製作晶片的成本。 因此本發明的目的之一就是在提供一種記憶體寬導 線結構，可以一次驅動多個記憶體輸出電路單元，以增加 晶片處理的能力與速度。 本發明的目的之二就是在提供一種記憶體寬導線結 構，可以簡化電路設計。 本發明的目的之三就是在提供一種記憶體寬導線結 構，可以減少雜訊，以增加晶片處理的品質。 本發明的目的之四就是在提供一種記憶體寬導線結 構，可以減少電阻-電容遲緩，以增加晶片處理的品質。 本發明的目的之五就是在提供一種記憶體寬導線結 構，可以減少導線之電阻阻抗。 本發明的目的之六就是在提供一種記憶體寬導線結 構，可以降低成本。 爲達成本發明之上述和其他目的，提出一種記憶體 寬導線結構，包括一記憶體晶片以及一寬導線結構體。其 中記憶體晶片具有多個記憶體輸出電路單元、多個第一分 支電源導線、多個第一分支接地導線、多個第一訊號導線， 而記憶體輸出電路單元分別具有一電源端、一接地端、一 訊號端，其中第一分支電源導線分別與記憶體輸出電路單 元之電源端電性連接，第一分支接地導線分別與記憶體輸 5 -----------^裝--------訂---------^9 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 6622twf.doc/008 _B7_ 五、發明說明（+ ) (請先閱讀背面之注意事項再填寫本頁) 出電路單元之接地端電性連接，第一訊號導線分別與記憶 體輸出電路單元之訊號端電性連接，而且第一分支電源導 線之一端暴露於記憶體晶片的表面，第一分支接地導線之 一端暴露於記憶體晶片的表面，第一訊號導線之一端暴露 於記憶體晶片的表面。上述之寬導線結構體包括至少一聚 合物介電材質與一圖案化線路結構，圖案化線路結構交錯 於該聚合物介電材質之內，而圖案化線路結構包括至少一 寬電源匯流排、至少一寬接地匯流排、多個第二分支電源 導線、多個第二分支接地導線、多個第二訊號導線，其中 第二分支電源導線分別與記憶體晶片之第一分支電源導線 電性連接，第二分支接地導線分別與記憶體晶片之第一分 支接地導線電性連接，第二訊號導線分別與記憶體晶片之 第一訊號導線電性連接，並且第二分支電源導線與寬電源 匯流排電性連接，第二分支接地導線與寬接地匯流排電性 連接，此外寬電源匯流排之一端暴露出寬導線結構體的表 面，寬接地匯流排之一端暴露出寬導線結構體的表面，第 二訊號導線之一端暴露出寬導線結構體的表面。 經濟部智慧財產局員工消費合作社印製 依照本發明的一較佳實施例，在上述記憶體晶片之 表面還包括一第一保護層，第一保護層包覆多個第一電源 焊墊、多個第一接地焊墊、多個訊號焊墊之周圍。此外， 上述之寬導線結構體的表面還具有一第二保護層，第二保 護層容納至少一第二電源焊墊、至少一第一接地焊墊、多 個第二訊號焊墊之周圍。另外，在寬導線結構體內還包括 一埋入式電容，此埋入式電容具有一電源金屬板、一接地 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 484137 6622twf.doc/008 _B7_ 五、發明說明（〈） 金屬板、一電容介電層，而此電容介電層的材質包括五氧 化二鉬。另外，在上述寬導線結構體內之上述介電材質可 包括聚亞醯胺或苯基環丁烯。並且在上述寬導線結構體內 之圖案化線路結構之導電材質可包括銅、金、鎳、鋁、鎢。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知記憶體結構示意圖。 第2圖繪示本發明第一較佳實施例的一種記憶體寬 導線結構示意圖。 第3圖繪示本發明第二較佳實施例的一種記憶體寬 導線結構示意圖。 第4圖繪示本發明第二較佳實施例對應於第3圖中 埋入式電容290局部放大圖。 圖式之標示說明： 100、200 :晶片 102、202 :記憶體輸出電路單元 104 :輸出延遲電路單兀 106 :時脈記憶體電路單元 108 :電源匯流排 110 :接地滙流排 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 >^51 — — — — — — — — — — I I I I I I I I e i I I I I I I (請先閱讀背面之注意事項再填寫本頁) 484137 五、發明說明（t ) Π2 :分支電源導線 114 :分支接地導線 Π6 :輸出訊號導線 (請先閲讀背面之注意事項再填寫本頁) 118 :控制導線 120 :時脈導線 122 :保護層 124 :電源焊墊 126 :接地焊墊 128 :訊號焊墊 130、218 :電源端 132、220 :接地端 134、222 :訊號端 136 :控制端 204 :第一分支電源導線 206 :第一分支接地導線 208 :第一訊號導線 210 :第一保護層 212 :第一電源焊墊 214 :第一接地焊墊 經濟部智慧財產局員工消費合作社印製 216 :第一訊號焊墊 250 :寬導線結構體 252 :寬電源匯流排 254 :寬接地匯流排 256 :第二分支電源導線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 6622twf.doc/008 A7 B7 五、發明說明（)） 258 :第 260 :第二訊號導線 262 :第二保護層 264 :第二電源焊墊 266 :第二接地焊墊 268 :第二訊號焊墊 280 :聚合物介電材質 282 :圖案化線路結構 290 :埋入式電容 292 :電源金屬板 2 9 4 ·接地金屬板 296 :電容介電層 經濟部智慧財產局員工消費合作社印製 實施例 請先參照第2圖，其繪示依照本發明第一較佳實施 例的一種記憶體寬導線結構示意圖。首先提供一記憶體晶 片200，比如是動態隨機讀取記憶體(DARM)、靜態隨機讀 取記憶體（SRAM)等，在此記憶體晶片200之內部包含多 個記憶體輸出電路單元202、多個第一分支電源導線204、 多個第一分支接地導線206、多個第一訊號導線208，而 在晶片200之表層具有一第一保護層210，在第一保護層 210間容納多個第一電源焊墊212、多個第一接地焊墊 214、多個第一訊號焊墊216，並且多個記憶體輸出電路單 兀分別包括一電源端218、一接地端220、一訊號端222。 ---I------裝.-----丨丨訂----I-- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 A7 6622twf.doc/008 _____— 五、發明說明（1 ) 其中，第一電源焊墊212與第一分支電源導線204電性連 接，接地焊墊214與第一分支接地導線2〇6與電性連接’ 訊號焊墊216與第一訊號導線208電性連接。此外’多個 第一分支電源導線204分別與記憶體輸出電路單元202之 電源端218電性連接，多個第一分支接地導線206分別與 記憶體輸出電路單元202之接地端220電性連接，多個第 一訊號導線208分別與記憶體輸出電路單元202之訊號端 222電性連接。此記憶體晶片200係透過微影、鈾刻、化 學氣相沈積、濺鍍等方式之半導體前段製程（精度小於一 微米)而完成。 本發明的關鍵係爲在晶片200之上具有一寬導線結 構體250(精度約數十微米）。請參照第2圖，在記憶體晶 片200之保護層206上，具有一寬導線結構體_2奴，在寬 導線結構體內具有一聚合物介電材質280以及一圖案化線 路結構282，而圖案化線路結構282具有一寬電源匯流排 252、一寬接地匯流排254、多個第二分支電源導線256、 多個第二分支接地電源導線258、多個第二訊號導線260、 一第二保護層262、一第二電源焊墊264、一第二接地焊 墊266、多個訊號焊墊268。其中，在第二保護層間容納 第二電源焊墊264、第二接地焊墊266、多個第二訊號焊 墊268，使第二電源焊墊264、第二接地焊墊266、第二訊 號焊墊268之部分暴露於外。並且聚合物介電材質280包 覆著寬電源匯流排252、寬接地匯流排254、多個第二分 支電源導線256、多個第二分支接地電源導線258、多個 --------11 --------^« — — — — — — 1— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 6622twf.doc/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1) 第二訊號導線260。第二分支電源導線256與晶片200之 第一電源焊墊208電性連接，第二分支接地導線258與晶 片200之第一接地焊墊210電性連接，第二訊號導線260 與晶片200之第一訊號焊墊212電性連接。第二分支電源 導線256與寬電源匯流排252電性連接，第二分支接地導 線258與寬接地匯流排254電性連接。並且寬電源匯流排 252與第二電源焊墊264電性連接，寬接地匯流排254與 第二接地焊墊266電性連接，多個第二訊號導線260分別 與多個第二訊號焊墊268電性連接。 聚合物介電材質280可使用日立-杜邦公司（Hitachi-Dupont)所生產之聚亞醯胺（Polyimide) HD2732或 ^102734，亦可使用苯基環丁嫌(86112〇〇}^1〇1)1^116，6€6)。 聚亞醯胺的形成方式可以用旋塗固化的方式形成，旋塗後 之聚亞醯胺需在一真空環境中進行固化或在一氮氣環境下 進行固化，溫度保持在250度至400度之間，所需時間約 0.5至1.5個小時。其中，對於厚度較厚之聚亞醯胺結構， 可採用多層旋塗固化的方式形成。 圖案化線路結構282配置於聚合物介電材質280 間，而圖案化線路282利用微影、蝕刻方式定義而成，其 圖案化線路282的導電材質可包括銅、金、鋁、鎳、鎢等， 由於此製作寬導線結構體的精度（約數十微米）並不如半導 體前段製程（小於一微米）之精密，因此可使用低成本之製 程，如電鏟、無電電鑛之方式形成，亦可使用職渡（sputtering) 的方式。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 ϋ 1 ·ϋ ϋ 1 1· t emf i amt 1 ^11 I 言 484137 經濟部智慧財產局員工消費合作社印製 6622twf.doc/008 五、發明說明（（ύ ) 〆 比較本發明之記憶體寬導線製程與習知記憶體晶片 之導線製程，由於上述的記憶體寬導線結構屬於半導體後 段製程，亦即在晶片完成後才進行寬導線製程，故上述之 寬導線製程所要求的精度（約數十微米）比較低」，可使用較 低價格之製程設備的運用，在較低等級之無塵室即可完成 此寬導線之製程，而降低生產成本r而且上述之寬導線結 構可以利用電鍍、無電電鍍、濺鍍等方式，覆蓋上銅導線’ 如此相較於鋁，導電性增加許多。並且寬導線結構體內具 有寬電源匯流排以及寬接地匯流排，此寬電源匯流排與寬 接地匯流排具有低電阻阻抗、低電阻-電容遲緩的特性’ 故雜訊較少出現，並且可一次驅動多個記憶體輸出電路單 元，因此輸出延遲電路單元的功能便顯得多餘，可將輸出 延遲電路單元除去，而時脈記憶體電路單元可以設計得較 爲簡單，如此可以提高性能，簡化電路設計，並且可以降 低記憶體晶片的製造成本。除此之外，多個記憶體積體電 路可以透過寬導線結構體而將電路連結在一起。 請參照第3眉，其繪示本發明第二較佳實施例的一 種記憶體寬導線結構。並且參照第4圖，繪示對應於第3 圖中埋入式電夸^ 290(Embedded capacitor)之剖面不意圖。 此外，埋入式電容290亦可視需要使用。如第4圖所示， 埋入式電容290具有一電源金屬板292，一接地金屬板 294，以及一電容介電層296，其中，電容介電層296位於 電源金屬板292與接地金屬板294之間。並且電容介電層 296之材質必須是具有高介電係數之特性，比如是五氧化 ----------裝--------訂-------！· \ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 A7 B7 6622twf.doc/008 五、發明說明（l V) 二鉅(Ta205)。 如第3圖所示，在寬導線結構體250內，亦可加入 一埋入式電容290，其中埋入式電容290之電源金屬板292 與寬電源匯流排252電性連接，接地金屬板294與寬接地 匯流排254電性連接。如此增加埋入式電容290之裝置後’ 當驅動閘的同步切換或接地反彈所產生的雜訊與暫態電流 經電源與接地，提供最佳交流短路路徑於電源與接地之 間，進而減少訊號傳輸的失真，亦可以降低電源端與接地 端所產生的突波對整體電路系統之影響，防止突發信號造 成系統誤動作。而埋入式電容之設計可以將高頻所引起的 壓降引導至接地端而不影響負載，且可以降低諧波失真之 程度，同時亦可將電源端與接地端之旁通電流，以減少暫 態電流的迴路面積。 綜上所述，本發明至少具有下列優點： 1. 本發明之記憶體寬導線結構，可以一次驅動多個 記憶體輸出電路單元，以增加晶片處理的能力與速度。 2. 本發明之記憶體寬導線結構，可以簡化電路設計。 3. 本發明之記憶體寬導線結構，寬電源匯流排與寬 接地匯流排之設計，可以減少雜訊、.導線之電阻阻抗、電 阻-電容遲緩的情形發生，以增加晶片處理的品質。 4. 本發明之記憶體寬導線結構，可以在寬導線結構 體內鋪上銅導線，而增加導線之導電能力。 5. 本發明之記憶體寬導線結構，可以降低成本。 6. 本發明之記憶體寬導線結構’可以在寬導線結構 ----------裝--------訂 ί—.—I— (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484137 6622twf.doc/008 _B7_ 五、發明說明（\V) 體內增加一埋入式電容，以減少雜訊的產生。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 ----------裝—------訂---------^9 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）484137 A7 B7 6622twf.doc / 008 V. Description of the invention (() The present invention relates to the wide wire structure of an integrated circuit, and in particular to the wide wire structure of a memory. As the appearance gradually shrinks, the metal wires that are wrapped in the interior are also further refined, and this has a negative impact on the performance of the circuit, which significantly reduces the performance of the chip. Among them, the excessively fine-grained wires It seriously affects the voltage drop of the power bus bar and the ground bus bar, and also causes the resistance-capacitance delay (RC delay) and noise of the critical signal path. Please refer to FIG. 1 for a schematic diagram of a conventional memory structure. The production of the conventional memory circuit chip 100 is a combination of a plurality of memory output circuit units 102, an output delay circuit unit 104 (output delay circuit), a memory clock circuit unit 106 (memory clock), a Power bus 108, a ground bus 110, multiple branch power wires 112, multiple branch ground wires 114, multiple output signal wires 116, multiple control wires 118, The wires 120 are directly completed in the chip 100, and the surface of the chip 100 has a protection layer 118 (Passivation layer), and the protection layer 122 exposes the power pad 124, the ground pad 126, and the signal pad 128. There are multiple memories. The output circuit unit 102 has a power terminal 130, a ground terminal 132, a signal terminal 134, and a control terminal 136. The power pad 124 is electrically connected to the power bus 108, and the power bus 108 is connected to a plurality of branches. The power supply leads 112 are electrically connected, and the multiple branch power supply leads 112 are electrically connected to the power supply terminals 130 of the multiple memory output circuit units 102, respectively, so that the power is transmitted from the power supply pads 124 to the multiple memory output circuit units. Power end of 102 130; grounding pad 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------- installation -------- order- -------- ^ 9 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484137 6622twf.doc / 008 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics B7 V. Description of the invention (v) 126 and ground sink The bus 110 is electrically connected, and the ground bus 110 is electrically connected to a plurality of branch ground wires 114, and the plurality of branch ground wires 114 are electrically connected to the ground terminals 132 of the plurality of memory output circuit units 102; multiple signals The pads 128 are electrically connected to the signal terminals 134 of the multiple memory output circuit units 102 through multiple output signal wires 116 respectively, so as to transmit the signals of the multiple memory output circuit units 102 to the signal pads 128; The clock circuit unit 106 is electrically connected to the output delay circuit unit 104 through the clock lead 120; the output delay circuit unit 104 is electrically connected to the control terminal 136 of the memory output circuit unit 102 through a plurality of control wires 118, respectively. The material used for the wires in the memory chip is mainly aluminum alloy or aluminum, and the line width of the thin film wires in the memory chip is extremely small, so that when the current is too large, problems such as noise and resistance-capacity delay are prone to occur. The above problems have a serious impact on the memory chip, because the line width of the power bus 108 and the ground bus 110 in the conventional memory chip 100 is extremely thin, so that the power bus 108 and the ground bus 110 cannot be efficiently used. Drive all the memory output circuit units 102. For a memory chip, reading a single piece of data usually requires multiple memory output circuit units 102. To speed up the reading speed, it is often desirable that these actions be performed simultaneously. However, when the amount of data becomes large, such as when multiple bits need to be read at the same time, the power bus 108 and the ground bus 110 will suddenly generate a large amount of current, resulting in noise and reading errors. Therefore, the conventional system uses the output delay circuit unit 104 to control and drive multiple memory output circuit units 102, and the driving frequency is transmitted through the memory clock. 4 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Li) ----------- Install ------ 丨 丨 Order ------- (Please read the notes on the back before filling this page) 484137 6622twf.doc / 008 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (57) The circuit unit 106 is used to control the data batches to be read and the less memory output circuit unit 102 is driven at one time to avoid being too large. Current. This method is really inefficient, and the circuit design tends to be complicated, which increases the cost of manufacturing the wafer. Therefore, one of the objectives of the present invention is to provide a memory wide conductor structure that can drive multiple memory output circuit units at a time to increase the chip processing capability and speed. Another object of the present invention is to provide a memory wide wire structure, which can simplify circuit design. Another object of the present invention is to provide a memory wide wire structure, which can reduce noise and increase the quality of chip processing. The fourth object of the present invention is to provide a memory wide wire structure, which can reduce the resistance-capacitance delay and increase the quality of wafer processing. A fifth object of the present invention is to provide a memory wide wire structure, which can reduce the resistance resistance of the wire. A sixth object of the present invention is to provide a memory wide wire structure, which can reduce the cost. To achieve the above and other objects of the present invention, a memory wide wire structure is proposed, which includes a memory chip and a wide wire structure. The memory chip has a plurality of memory output circuit units, a plurality of first branch power wires, a plurality of first branch ground wires, and a plurality of first signal wires, and the memory output circuit unit has a power terminal and a ground, respectively. Terminal, a signal terminal, wherein the first branch power lead is electrically connected to the power terminal of the memory output circuit unit, and the first branch ground lead is connected to the memory 5 ----------- ^ -------- Order --------- ^ 9 (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) (Centre) 484137 6622twf.doc / 008 _B7_ V. Description of the invention (+) (Please read the precautions on the back before filling this page) The ground terminal of the circuit unit is electrically connected, and the first signal wire is separately connected to the memory output circuit unit The signal end of the first branch is electrically connected, and one end of the first branch power lead is exposed on the surface of the memory chip, one end of the first branch ground lead is exposed on the surface of the memory chip, and one end of the first signal lead is exposed on the memory chip. surface. The above-mentioned wide wire structure includes at least one polymer dielectric material and a patterned circuit structure. The patterned circuit structure is staggered within the polymer dielectric material, and the patterned circuit structure includes at least one wide power bus, at least A wide ground bus, a plurality of second branch power wires, a plurality of second branch ground wires, and a plurality of second signal wires, wherein the second branch power wires are electrically connected to the first branch power wires of the memory chip, The second branch ground wire is electrically connected to the first branch ground wire of the memory chip, the second signal wire is electrically connected to the first signal wire of the memory chip, and the second branch power wire is connected to the wide power bus. The second branch ground conductor is electrically connected to the wide ground bus. In addition, one end of the wide power bus exposes the surface of the wide conductor structure, and one end of the wide ground bus exposes the surface of the wide conductor structure. The second One end of the signal wire exposes the surface of the wide wire structure. Printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in accordance with a preferred embodiment of the present invention, the surface of the memory chip further includes a first protective layer, the first protective layer covers a plurality of first power pads, multiple Around a first ground pad and a plurality of signal pads. In addition, the surface of the above-mentioned wide wire structure has a second protective layer, and the second protective layer contains at least one second power pad, at least one first ground pad, and a plurality of second signal pads. In addition, the wide-conductor structure also includes an embedded capacitor. The embedded capacitor has a power metal plate and a ground. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). Printed by the Intellectual Property Bureau employee consumer cooperative 484137 6622twf.doc / 008 _B7_ V. Description of the invention (<) Metal plate, a capacitor dielectric layer, and the material of this capacitor dielectric layer includes molybdenum pentoxide. In addition, the dielectric material in the wide-wire structure may include polyimide or phenylcyclobutene. In addition, the conductive material of the patterned circuit structure in the wide wire structure may include copper, gold, nickel, aluminum, and tungsten. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Draw a schematic diagram of the structure of the conventional memory. FIG. 2 is a schematic diagram of a memory wide wire structure according to the first preferred embodiment of the present invention. FIG. 3 is a schematic diagram of a memory wide wire structure according to a second preferred embodiment of the present invention. FIG. 4 shows a partially enlarged view of the second preferred embodiment of the present invention corresponding to the embedded capacitor 290 in FIG. 3. Description of the diagrams: 100, 200: chip 102, 202: memory output circuit unit 104: output delay circuit unit 106: clock memory circuit unit 108: power bus 110: ground bus 7 This paper size applies China National Standard (CNS) A4 Specification (210 X 297 > ^ 51 — — — — — — — — — — — IIIIIIII ei IIIIII (Please read the notes on the back before filling this page) 484137 V. Description of the invention (t) Π2: Branch power line 114: Branch ground line Π6: Output signal line (please read the precautions on the back before filling this page) 118: Control line 120: Clock line 122: Protective layer 124: Power pad 126: Ground welding Pad 128: signal pads 130, 218: power terminals 132, 220: ground terminals 134, 222: signal terminals 136: control terminals 204: first branch power wires 206: first branch ground wires 208: first signal wires 210: First protective layer 212: First power pad 214: First ground pad Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 216: First signal pad 250: Wide wire structure 252: Wide power bus 254: Wide grounding bus 256: Second branch power supply wire This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 484137 6622twf.doc / 008 A7 B7 V. Description of the invention ()) 258: No. 260: second signal wire 262: second protective layer 264: second power pad 266: second ground pad 268: second signal pad 280: polymer dielectric material 282: patterned circuit structure 290: embedded Capacitor 292: power metal plate 2 9 4 • ground metal plate 296: capacitor dielectric layer printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics Please refer to FIG. 2 for an example of the first preferred implementation of the present invention An example of a memory wide wire structure. First, a memory chip 200 is provided, such as a dynamic random access memory (DARM), a static random read memory (SRAM), and the like. The memory chip 200 contains a plurality of memory output circuit units 202, multiple A plurality of first branch power wires 204, a plurality of first branch ground wires 206, and a plurality of first signal wires 208, and a first protective layer 210 is provided on the surface of the chip 200, and a plurality of first protective layers 210 are accommodated between the first protective layers 210; A power pad 212, a plurality of first ground pads 214, a plurality of first signal pads 216, and a plurality of memory output circuits each include a power terminal 218, a ground terminal 220, and a signal terminal 222, respectively. --- I ------ Packing .----- 丨 丨 Order ---- I-- (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 484137 A7 6622twf.doc / 008 _____ — V. Description of the invention (1) Among them, the first power pad 212 and the first branch power lead 204 are electrically connected, and the ground pad 214 and the first A branch ground wire 206 is electrically connected to the signal pad 216 and the first signal wire 208 is electrically connected. In addition, a plurality of first branch power wires 204 are electrically connected to the power terminal 218 of the memory output circuit unit 202, and a plurality of first branch ground wires 206 are electrically connected to the ground terminal 220 of the memory output circuit unit 202. The plurality of first signal wires 208 are electrically connected to the signal terminal 222 of the memory output circuit unit 202, respectively. This memory chip 200 is completed through a semiconductor front-end process (accuracy less than one micron) by lithography, uranium engraving, chemical vapor deposition, and sputtering. The key point of the present invention is to have a wide wire structure 250 (with an accuracy of about several tens of microns) on the wafer 200. Please refer to FIG. 2. On the protective layer 206 of the memory chip 200, there is a wide wire structure _2 slave, and within the wide wire structure is a polymer dielectric material 280 and a patterned circuit structure 282. The circuit structure 282 has a wide power bus 252, a wide ground bus 254, a plurality of second branch power wires 256, a plurality of second branch ground power wires 258, a plurality of second signal wires 260, and a second protection. Layer 262, a second power pad 264, a second ground pad 266, and a plurality of signal pads 268. Among them, a second power pad 264, a second ground pad 266, and a plurality of second signal pads 268 are accommodated between the second protective layers, so that the second power pad 264, the second ground pad 266, and the second signal pad A portion of the pad 268 is exposed. And the polymer dielectric material 280 is coated with a wide power bus 252, a wide ground bus 254, a plurality of second branch power wires 256, a plurality of second branch ground power wires 258, a plurality of ------- -11 -------- ^ «— — — — — — 1— (Please read the notes on the back before filling out this page) Printed on paper standards of the Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumer Cooperatives, Chinese national standards (CNS) A4 specifications (210 X 297 mm) 484137 6622twf.doc / 008 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Second signal wire 260. The second branch power wire 256 is electrically connected to the first power pad 208 of the chip 200, the second branch ground wire 258 is electrically connected to the first ground pad 210 of the chip 200, and the second signal wire 260 is connected to the first A signal pad 212 is electrically connected. The second branch power line 256 is electrically connected to the wide power bus 252, and the second branch ground line 258 is electrically connected to the wide ground bus 254. In addition, the wide power bus 252 is electrically connected to the second power pad 264, the wide ground bus 254 is electrically connected to the second ground pad 266, and the plurality of second signal wires 260 are respectively connected to the plurality of second signal pads 268. Electrical connection. The polymer dielectric material 280 can use Polyimide HD2732 or ^ 102734 produced by Hitachi-Dupont, or phenylcyclobutadiene (86112〇〇) ^ 1〇1) 1 ^ 116, 6 € 6). The polyimide can be formed by spin-coating. The polyimide after spin-coating needs to be cured in a vacuum environment or a nitrogen atmosphere, and the temperature is maintained between 250 ° C and 400 ° C. It takes about 0.5 to 1.5 hours. Among them, a thicker polyurethane structure can be formed by a multi-layer spin coating method. The patterned circuit structure 282 is disposed between polymer dielectric materials 280. The patterned circuit 282 is defined by lithography and etching. The conductive material of the patterned circuit 282 may include copper, gold, aluminum, nickel, tungsten, etc. As the precision (about tens of micrometers) of this wide wire structure is not as precise as that of the previous semiconductor manufacturing process (less than one micrometer), it can be formed using low-cost processes, such as electric shovel and electroless power ore. Use sputtering. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling this page) Decoration 1 · ϋ ϋ 1 1 · t emf i amt 1 ^ 11 I Printed by the Consumer Cooperative of the Intellectual Property Bureau, Ministry of Economic Affairs, 6622twf.doc / 008 V. Invention Description ((ύ) 〆 Compare the memory wide wire process of the present invention with the conventional wire process of memory chips. The wire structure belongs to the semiconductor back-end process, that is, the wide wire process is performed only after the wafer is completed. Therefore, the precision required for the above-mentioned wide wire process (about tens of micrometers) is relatively low. "Lower-priced process equipment can be used. The production process of this wide wire can be completed in a lower-level clean room, and the production cost is reduced. Moreover, the above-mentioned wide wire structure can be covered with copper wires using electroplating, electroless plating, sputtering, etc., compared to aluminum. , The conductivity increases a lot. And the wide wire structure has a wide power bus and a wide ground bus. The wide power bus and the wide ground bus have low resistance. Low-resistance-capacitance retardation ', so noise is rare, and multiple memory output circuit units can be driven at one time, so the function of the output delay circuit unit becomes redundant, and the output delay circuit unit can be removed, and the clock The memory circuit unit can be designed to be simpler, which can improve the performance, simplify the circuit design, and reduce the manufacturing cost of the memory chip. In addition, multiple memory volume circuit can pass the circuit through the wide wire structure. Please refer to the third eyebrow, which shows a memory wide wire structure according to the second preferred embodiment of the present invention. Referring to FIG. 4, it shows the embedded electric exaggeration corresponding to FIG. ^ 290 The cross section of the (Embedded capacitor) is not intended. In addition, the embedded capacitor 290 can also be used as needed. As shown in Figure 4, the embedded capacitor 290 has a power metal plate 292, a ground metal plate 294, and a capacitor dielectric. The dielectric layer 296, wherein the capacitor dielectric layer 296 is located between the power metal plate 292 and the ground metal plate 294. In addition, the material of the capacitor dielectric layer 296 must have a high dielectric strength. The characteristics of the coefficient, such as pentoxide ---------- install -------- order -------! · \ (Please read the precautions on the back before filling this page ) This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 484137 A7 B7 6622twf.doc / 008 5. Description of the invention (l V) Erju (Ta205). As shown in Figure 3, An embedded capacitor 290 can also be added to the wide wire structure 250. The power metal plate 292 of the embedded capacitor 290 is electrically connected to the wide power bus 252, and the ground metal plate 294 and the wide ground bus 254 are electrically connected. connection. After adding the device of the embedded capacitor 290 in this way, the noise and transient current generated by the synchronous switching of the driving brake or the ground bounce pass through the power and ground, providing the best AC short-circuit path between the power and ground, thereby reducing the signal. Transmission distortion can also reduce the impact of the surge generated by the power and ground terminals on the overall circuit system, and prevent sudden signals from causing system malfunction. The design of the embedded capacitor can guide the voltage drop caused by high frequency to the ground without affecting the load, and can reduce the degree of harmonic distortion. At the same time, it can also bypass the current between the power terminal and the ground to reduce Loop area of transient current. In summary, the present invention has at least the following advantages: 1. The memory wide wire structure of the present invention can drive multiple memory output circuit units at one time to increase the chip processing capacity and speed. 2. The memory wide wire structure of the present invention can simplify circuit design. 3. The memory wide wire structure, wide power bus and wide ground bus design of the present invention can reduce the occurrence of noise, wire resistance resistance, and resistance-capacitance retardation to increase the quality of chip processing. 4. The memory wide wire structure of the present invention can be covered with copper wires inside the wide wire structure to increase the conductive ability of the wires. 5. The memory wide wire structure of the present invention can reduce costs. 6. The memory wide wire structure of the present invention can be installed in a wide wire structure ------------------ I— (Please read the precautions on the back first (Fill in this page again.) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 484137 6622twf.doc / 008 _B7_ V. Description of Invention Add an embedded capacitor to reduce noise. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---------- Equipment ------- Order --------- ^ 9 (Please read the precautions on the back before filling this page) Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the cooperative applies the Chinese National Standard (CNS) A4 (210 X 297 mm)