TW483280B - Shared bus to allow use of one transport IC for multiple signals modulated using respectively different modulation schemes - Google Patents

Abstract

A multiple protocol receiver includes a demodulator section. The demodulator section includes a plurality of demodulators, each demodulator having a tri-state output terminal for generating demodulated digital data. The tri-state output terminals are coupled to a signal bus. The signal bus, in turn, is coupled to a signal processor, such as a transport processor, for processing the demodulated digital data.

Description

—-— 15. Description of the invention (1) _: Send: It is related to signals modulated according to different modulation architectures. For example, such as satellite signals and terrestrial broadcast high-quality signal processing, digital signals that carry programs. The providers of Zhu Zhuan Cong are in different formats, sometimes called =, two? In this system, all bearers are provided by satellite? It is said that the protocol is used to make the format. Similar to Λ High Book Quality ( HDTT) Seven Discipline IP Shita, Yama :, Also Broadcasting: Bei UiDTV) The situation is produced in accordance with the standards approved by the Advanced Television Standards Committee = ί United States Federal Commission Tao, = 广 _program signal use and use The agreement is to produce the format. The broadcast video (DVB) signal can be transmitted by satellite or via an electric arm, and the format is different according to European standards. $ «# D 、 digits 5 tiger in Different modulations on the carrier are used to transmit the weekly changes to the customer. For example, ^ ^ Menyi wooden structure (Qpsio modulation structure $% uses a ninety degree phase shift wheel-in (SB) modulation structure Come to modulate. DVB satellite side: Come to modulate 'and DVB cable signal one And = ~ Force wooden structure Nine + broken phase ^ ☆ Mo Zhen I- /, there are 4 or 2 5 6 points cluster

Ten-degree phase difference modulation (_) T-steps understand that even similar modulation architectures (eg; with different parameters, such as excessive bandwidth factor,: PSK) have different configurations of the demodulator using the number. 9 Requests for different QPSK messages. The guilds want to receive any bitcoin digital signal that is carried by the agreement ::; and the individual receiving agreement of the agreement that carries the program. ~ Then, the court needs to collect for each customs. . , The mother is contained in a separate package, various

Page 4 The vertical mounting hole is the top mounting box as shown. Modulation of each digital signal suitable for modulation = receiver, including a receiver is expensive for the customer, c. However, individual :: space, and inconvenient to use. For example: 卞, the top-mounting box requires the large-end remote end # Μ, which may be incompatible with other top-end page-mounting boxes [, therefore, provided in a single package and = 爰 box. Yes, it can be desirable to receive multiple protocol 2 receivers separately-each receiver must include-demodulate any of the two. In this way, the signals modulated by different modulation architectures are known. It can selectively and selectively transport decoder parts according to different parts. For such a demodulator part: to process the demodulated digits. The functions performed by the individual demodulator are accurate and accurate. The technical solution involves analyzing the requirements for all the different modulation architectures, a single suitable demodulator, and a demodulator part included to change its Inside, there are "functioning functional circuits." == Modulation selected before demodulation S: configured to respond to a control signal. Most or all modulation architectures have this function. Because there are some functional demodulators, which can be reassembled to solve the problem, this technology can provide-any feasible wheel to modulate. Week based on many predetermined modulations

US Patent No. 5, ^, = to Wt. Posted on September 23, 1997

Stewart Nos. 5, 717, 471 and 3j and ^ 9 were issued on February 10, 1998. Such systems include a single system. A demodulator on an integrated circuit (1C) chip can be configured on a single A to sub-demodulate an early signal according to different modulation frames. For example, U.S. Patent No. 5,6 1 7,253 describes a system capable of solving the problem of DVB and DVB satellite and cable signals, and U.S. Patent No. 483280 V. Invention Description (3) 5, 717,471 shows a demodulated satellite signal, The terrestrial broadcasting signal and the information are the same. In each of these systems, the functional circuit is provided on the regulator 1C for all the necessary functions of the different modulation architectures desired: a multiplexer in between to each Connect k rack 1 to reconfigure the circuit: the control signal is supplied to a proper state by a system controller. Even ... put its modulation architecture on the _ another, the first 4 technology solution to provide individual demodulation of the desired signal, and then provide a multiplexer to the desired demodulator and transport processing cry 0 1 9 9 9 ^ 10 ^ 26 a ^ Grimes ^ A 27, / = ㈣ Such a system. In 〇9 / 427,388, the multi-modulation center: The second one: The multiplexer, the demodulator demodulates according to many workers: ΐί ㈣ The signal is provided to the multiplexer to make the desired demodulator Connected to the appropriate shipping process cry. In the previous artisans, the mouth is expensive. The addition of an additional demodulator to the enemy is a new feature that is needed. The semi-fixed interpolation chip must be re-analyzed to determine the pre-existing circuit of the new electrical function, and receive the circuit and the charging system. The control processor of the machine must provide a U-shaped machine to increase the function of the promoter in the IC chip. It may be necessary to add two functions in the "chip :: an additional demodulation function circuit, and / or to increase the input_ / = External workers / workers to add additional multiplexers. This in turn makes additional and / or expanded lines. This may require additional work on the 1C chip as additional controllability and dispersal control. Signal., Pin, or additional 483280 of the system ~-------- 丨 V. Description of the invention (4) In the previous prior art solutions, ~, but it still needs to expand the demodulator The external demodulator can be added more easily. This may mean using a multiplexer that is available but connected to the shipping processor in a system that originally included three demodulation ^ use = multiplexer input endpoint. Available but unused in one multiplexer =, the fourth can be used in this way However, the fifth demodulation The addition of the multiplexer requires f four input endpoints to join. New design. In another case, the demodulation of the multiplexer circuit is completely out of the control signal and in the multiplexer: The additional complexity in the tool's spreading system. It is ridiculous to receive signals that are modulated by many, and architecture, or it ’s controversial control signals # ^ | 迗 and according to many corresponding adjustments It is easy and not expensive. The structure of the receiver makes the addition of a new demodulator in accordance with the principles of the present invention, the :: tuner section includes many demodulators, a solution; the demodulator section bus. The signal bus is then easily combined to the -signal operation. It is beneficial to process the demodulated digital data .... The demodulator part designed in the same way makes it easy to add _ 1 Tuning. The demodulator outside the jaw is only two and two outside the zygomatic, and is connected to the Feng, 2814, and other endpoints, as other buses are redesigned first. No suitable demodulator is needed In the figure, t has a multiplexer which needs to be expanded. = 2 f Wan demodulator portion of the same side, μ FIG month! Described demodulator portion of the receiver of Page 7483280

More detailed block diagram. FIG. 1 is a block diagram of a demodulator portion of a receiver according to the present invention. The "10" demodulator is coupled to the individual baseband modulation signals (","), which is modulated according to one of the different modulation architectures. ° 周杰 1 1 〇 (1) Decode the signal according to a modulation architecture (such as VSB for HDTV) to 2 1 〇 (2) Demodulate the signal according to different modulation architectures (such as QPSK for DVB). The remaining solutions The modulator demodulates the signal according to different tuning architectures (such as DVB's QPSK and QAM). The demodulator of the number two is coupled in a known way to the endpoint including data and control signals. The signal bus 20 of No. 2 is also coupled to the input endpoint of the Yunda processor 30. A system controller 40 provides control signals to the demodulator (and To other circuits not shown). Each of several demodulators includes two tri-state output buffers 12 to couple the signal from the demodulator to the signal bus 20. Each such tri-energy: The output buffer includes a control input endpoint QE. The system controller 40 provides a signal to each output of the tri-state buffer i 2 It can input endpoints. In operation, the system controller 40 provides an output enabling control signal to the tri-state buffer of the only selected one of the several demodulators. 2. For returning u ^, a control signal is The tri-state buffer in the selected demodulator 10 ^ ^ generates a logical size signal to represent the demodulated digits from the demodulator 丨 10 and the remaining (ie, unselected) reception of several demodulators The control signal disables the output of the one-state buffer 12 in response. In response to such a control signal, the output end point of the buffer is caused to exhibit a high output impedance. Therefore, 10 demodulators The selected one is coupled to ° 观 * 流 483483280 V. Description of the invention (6) Row 2 0 'at the same time among 10 demodulators. From 10 demodulation P ;, § fL bus 20 and bus 20 are supplied to the ship: the signal is therefore passed through the signal < 疋 ~ buried state 30 0. Ties; μ: Health 丨 丨 Μ t signal (not shown) for delivery When the processor 30 is in the form of one, two, two, and two, the transport processor 30 is locked into an a in an appropriate manner. The number of demodulation in response to the selected one is shown in ^: 10 demodulators), which is also known as-. In a sample receiver, it is possible to provide a solution such as "Γ_ 的In terms of numbers, the 1C crystal r does not need to design a suitable demodulator. FIG. 2 is a more detailed block diagram illustrated in FIG. I according to the present invention. The components of the% key part are given the same reference; Γ is used to simplify the figure, and only the two solutions ‘name two, two, and two are explained in detail. People can understand more than two; cry °: familiar with the art system. [Solution 3] The benefits of 3 weeks may be included in FIG. 2 according to the present invention. Each of the demodulated digits of 10 pouting demodulator demodulation digits two / four produces four bearers from a series of bitstreams. Type = Signal. In Figure 2: The 'f-bit' data is contained in a non-returning burn (NRZ) forest. A lean data signal (DATA) is generated, and-is generated. The number of pure meters demodulated on the other side of the bank / Shilie data stream allows clocking to the following circuit clock signal (CL0CK) * containing time information. For example, for DSS format information

$ 9 pages ^ 3280 5. Description of the invention (7) The material 'series data is generated at approximately 42 MHz, and for HDTV format data, the series data is generated at approximately 43 MHz. The format produces a series of data at different feed rates. The transport processor 30 is configured to be able to process a series of data at all data rates generated by a number of 10 demodulators. The further signals generated by the 10 demodulators are a packet correct signal (PACKET VALID) and a packet data signal (PACKET dATA).

When the data in the packet carried by Tianmubie on the signal bus 20 is correct, the packet correct signal (PACKET VALID) is adjusted to adopt a logical state, and the Tianmu beta packet has many errors that make the data unable to be correctly restored. Take f a logical state. When the shellfish material currently carried on the signal bus 20 represents the delivery data, adjust the packet data signal (PACKET to take a logical state, and when the signal bus 20 currently bears, queues the material Another logical state is adopted when representing the information of the influencing factors, where = false debt measurement and correction code information. The shipping processor 30 will ignore it.

VALID% lp ^ 5 ^ PACKET _ and PACKET DATA signals. These four signals are generated by 10 of the several Hu Hudian 5 ^ 土 #, the mother of the U solution with one known design & two :, a known way, and supply to individual: y. 5 _ + The individual outputs of the buffer state circuit 12 are connected to the bank 1% in the flood number bus 20 & Those skilled in the arts are more detailed and logical in Figure 2. There are several solutions in 10; crying: the characteristics of the flood number of two f, physical system controller 4. The mothers that produce pairs 10; ::: are all the same. The control signal of the modulator in each of the demodulator. The 10-digit & register 14 is coupled in a known way

483280

The system receives a control signal from the system controller 40. Control temporary storage The output terminal is shared and closed to the output of the tri-state buffer 12. The person skilled in the art will understand that the control signal can be controlled. ^ ^. Ten or more of them should be supplied in any one of many known architectures. The system control can be controlled by each of the microprocessors. The control sink that can be jointly connected to the microprocessor is a solution. :: Example of the month, 10 demodulators are made by a Phillips coffee platoon:-brother platoon-the known side to get together-micro-judgment, and it will make the hidden stream flood confluence Row 20 consists of four signal lines: the first

= :, and the second one is for the serial data clock signal cloc. "^ · Includes the data part of the signal bus 20. The third one is for the 1 signal (View ET VALID) and the fourth signal line. & = ^ 虎 PACKET DATA). The above-mentioned signal line includes the control part of the signal exchange ^ 枓 枓 2 0. The transport processor 3 0 is connected to L and if the packet is correct, and the current generation; The data is used to extract the required information, all in a known manner: In FIG. 2, the signal bus 20 is coupled to the transport processor 3 through a freely selectable buffer + 5, # shown in the dashed box in FIG. 2 ：：： Jie circuit 25 provides additional driving power for the signals in the signal bus 20. Right 10, several demodulators are not configured with a transport processor 30, this may be necessary. For example, if Ten demodulators are on one or more IC chips, and the processor is on a different chip, so the signal bus must be transmitted via a printed circuit board (PCB) route, for example. Sound 4832㈧ V. Description of the invention (9) Transmission requires buffer 2 5 In addition, the implementation of the description The 3.3-volt CMOS process is used to configure the same number of ^ demodulator circuits using a TTL process configuration. In this system, the system design ^ transport = 30 is a 5 volt specially designed power-on circuit to The power-on period is the circuit ^ Yishan includes the special shutdown. This prevents 10 demodulators I c ,, 'B word output end point holding point is unfavorably during power-on g = slice = 3.3 volt CMOS output The door lock stack processor 30-5 volt wheels are shown in Figure 2. Those who explain the signal bus art will understand that the other configuration is composed of 4 signal lines. Familiar technology; -5.::type r is in the position of the number r, the data of one group of ears is right. A sample with CLOCK in this configuration will be one bit and H data lines. The clock signal has a solution. Tuner and transport processing cry 3 (K cry t day guard). This increases the number of pins s necessary on the number of 10 S and 25 on each device, but reduces the number of tri-state buffers 12 required for signal two. Number. If shipping is provided; out, the element rate-for example, eight factors determine which data bit; (two degrees, additional circuits to monitor data And 1 phase, day 丨 ^ ^ (or Wu group) represents the transport data and which shaker μ iron = measurement and correction data, it is also possible to eliminate the packet da representative said: 地 丄 ^ By including the packet data itself :: Two :: to eliminate the PACKET VALID signal. Later, it may be replaced by — = :: material signal to replace the comfort of the illustrated embodiment ::! No. CL〇CK. So, the minimum-output endpoint, its 4 count ... Tender is possible. However, the illustrated two-body

Page 12 483280

Page 13 483280 Case No. 89114171 f / Year Last Month Schematic Description Schematic Symbol Symbol Description 10 (1)... 10 (N) 12 (1) ... 12 (N) 1 4 Control temporarily Register 2 0 signal bus 2 5 freely selectable buffer circuit 3 0 transport processor 4 0 system controller 91. 2.2 5jf positive January 1; j: > demodulator tri-state buffer

O: \ 65 \ 65023.ptc Page 14

Claims (1)

483280 Case No. 89114Π1 Amendment ♦ Sixth, the scope of patent application 1. A demodulator part in a multi-protocol receiver, including: Many demodulators, each with a tri-state output endpoint for demodulated data and a signal The bus is coupled between the individual outputs of many demodulators and a signal processor to process the demodulated data. 2. The demodulator part of the first patent application scope further includes a system controller which is coupled to many demodulators to determine a selected one of the many demodulations to pass demodulated data through the output endpoint to the signal. The bus determines the other of many demodulators to spread south impedance at individual output endpoints. 3. As for the demodulator part of the scope of the patent application, each of the plurality of demodulators includes a tri-state buffer with an output terminal coupled to the signal bus. 4. For example, the demodulator part of the patent application scope item 3, wherein: the tri-state buffer in each of many demodulators further includes a control input endpoint; and the demodulator part further includes a system control Modulator, which is coupled to the control input of the tri-state buffer in each of the plurality of demodulators to determine the tri-state buffer demodulation data in the selected one of the plurality of demodulators through the output endpoint To the signal bus, and determine the tri-state buffer in the other one of the many devices to its individual output endpoints; control the point to one of the demodulation points of a series of devices to control the demodulation Shows a high impedance. 5. As for the demodulator part of the patent application scope item 4, wherein: each of the many demodulators contains a number of tri-state buffers, which control them O: \ 65 \ 65023.ptc Page 15 483280 Amendment No. 89114171 Six. Patent application input terminals are commonly coupled to the system controller; and the signal bus contains many signal lines, which are respectively coupled to many tri-state buffers. Individual output endpoints. 6. As for the demodulator part of the patent application scope item 4, each of the many demodulators further includes a control register, which has an input terminal coupled to the system controller and a tri-state coupling The output endpoint of the buffer's control input endpoint. 7. The demodulator part of the first patent application scope further includes a buffer coupled between the signal bus and the signal processor. 8. For the demodulator part of the scope of patent application, the signal processor is a transport processor. O: \ 65 \ 65023.ptc Page 16