TW478064B - Method of plasma etching a polysilicon layer through a patterned SiO2 layer - Google Patents

Abstract

Disclosed herein is a method for dry etching a polysilicon layer formed on a thin SiO2 layer through a patterned SiO2 cap layer. According to the method, the structure is placed on the electrostatic chuck of a vacuum chamber of a high density plasma etcher provided with two RF generators to supply the TCP (transformer coupled plasma) and bias powers. Then, the exposed areas of the polysilicon layer are plasma etched through the patterned SiO2 cap layer down to the underlying thin SiO2 layer with a HBr/HeO2 based chemistry wherein the TCP/bias power ratio is (20, 50) and the HBr/HeO2 gas flow ratio is (1.9, 5) so that the polysilicon: cap SiO2 selectivity is greater than 10:1 to produce polysilicon lines with a substantially vertical profile.

Description

478064

FIELD OF THE INVENTION-The present invention relates to a method for manufacturing semiconductor integrated circuits (ICs) and more particularly to an improved plasma etching method for etching a polysilicon layer overlying a thin layer of Si02 by patterning the Si02 layer. The resulting polysilicon line has a vertical profile and is highly desirable in subsequent wafer manufacturing processing steps. Background of the Invention In manufacturing advanced semiconductor ICs, especially DRAM wafers, insulated gate field effect transistors (IGFETs) are widely used. In "^ chip /, a device memory element is composed of GFET and storage capacitor. The spacer formed by the metal separating the gate conductors from contact with the source / drain regions of each IGF ET is essential. Figure r-6 shows the structure of the necessary steps to form Lu Yixin through the insulating spacer of nitrided stone (importantly, it is necessary to point out that the diagram may not be drawn to scale). Figure 1 shows the structure of the initial stage of the forming process. A part of the silicon wafer is formed. Referring to FIG. 1 ′, the structure shown by 10 includes a silicon substrate 11 which is coated with a 5 · 2 f-thick silicon oxide (si 〇2) layer 1 2 and formed thereon. The so-called ^ GC stack 13. This Si02 thin layer 12 forms the gate dielectric of an iGFET, as known in the art, and will be referred to as s 丨 〇2gate layer 2 in the following. The G c Heap · $ 13 is typically composed of several overlapping layers of nanometer-thick undoped ^ Shi Xi bottom layer, 50 nanometer-thick Si02 pillar top layer 15 and 57 nanometer-thick anti-reflection top coatings. A 0. 5 micron thick layer of positive photoresist material is formed on the GC stack 13 standard. Xin ^ Stack 1 3Describes the process to make the photoresist layer 1 7 The process begins with the preparation of the desired photomask. Then, a two-step process is used in order, using a photoresist photomask i 7 = the exposed part of the bottom layer of the SixOyNz layer 16 and the top layer 15 of the Si02 pillar. Qian Engraved in Mark II rie etcher (by U.S. (^, Santa Corella

O: \ 64 \ 64647.ptc Page 5 478064 Case No. 89111050 Month Revision V. Description of the Invention (2) Tools sold by Applied Materials, a chemical company mainly based on CHF3) and the following process parameters. S i X 0 y N z nickname CHF 3 flow rate 02 flow rate pressure power duration nsccm: 60 seem: 10 seem: 20 millitorr (mTorr: 2 0 0 watt: 1 0 5 seconds means standard cubic centimeters per minute An optical spectrometer is turned on to detect the end of the etch by 3 8 6. 5 nm (CN). However, about 15% overetching (about 20 ^ seconds) can be performed for overall safety.

Si02 etching CHF3 flow rate Ar flow rate pressure power duration: 3 0 seem: 6 0 seem: 20 millitorr (mTorr): 2 0 0 watts: 90 seconds with an optical spectrometer to turn on 4 7 5.5 .5 nm irradiation (C0 ) Detect the end of etching. Likewise, over-securing can be performed for 30 seconds in terms of overall safety: the resulting structure is shown in FIG. 2. < Then the photoresist mask 17 is ashed in ozone to peel and the structure 10 is cleaned in a standard manner. SixOyNz layer 16 is now peeled in the same Mark II RIE reactor under the following operating conditions:

O: \ 64 \ 64647.ptc Page 6 4 / Excitation 4-^ 89111050 V. Description of Invention (3) "

Correction Fracture S i X 〇 y 卩 z C H F 3 Flow rate 〇2 Flow rate Pressure 60 seem 10 seem Power duration Borrowed light wind V V / 1 / point. Wei, 6 77 light e ten turns on 3 6 · 5 micron irradiation (C N) detection last name engraved end borrowed pattern ^ degree money engraved. The resulting structure is shown in FIG. 3. It is obvious from FIG. 3 that the polysilicon layer 14 is covered by the top layer 15 of the Si02 pillar. The etching step is to use the patterned Si02 pillar top layer 15 as an in-situ hard mask. This step is performed in a high-density LAM TCP 9 40 0 plasma reactor equipped with two standard master devices, with HBr :. Chemicals. This tool is pinned by the LAM laboratory of Fermon in the United States. 20 0 W 8 η Φ Wafer is placed on the column operating conditions HBr flow rate He02 pressure TCP power bias power RF frequency and applied to the electrostatic chuck in the vacuum chamber of the plasma etcher and applied : 2 1 0 seem •• 15 seem: 6 millitorr: 1 25 watts: 77 watts: at 13.56 MHz

This step uses optical spectrometer tracking to detect the interface of the polysilicon layer 14 / Si02 gate thin layer 12 (405 nm irradiation) as a standard. The resulting structure 10 is shown in FIG. 4. During this step, the entire surface of the structure 1

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Case No. 89111 (^ (1 V. Description of the Invention) (4) A thin film of Si02 material is formed on the surface. The oxygen thin film in the He02 flow, which is gated during the polysilicon etching period, is generated at b 1 Ux with 柞 A # I d Ϊ hi is then deposited on the surface of structure 10. It will be used as a screen to protect the 4 silicon structure. The remaining part of the polysilicon layer 14 is called the Gc line hereafter, and is still represented by the value 14. / quot; = iH 清洗 Clean in DHF solution to remove g10 line material 14 such as sl0x material film 18 and column top layer 15. 〇2 material see Si02 column top 15 still remains on the upper end of GC line U, which Has a reduction = 4 degrees thick and a rounded corner. The structure at this stage in the process of forming the Si3 & spacer is shown in Fig. 5 Finally, a Si3N4 spacer covering the side edges of the GC line 14 is formed. Finally, NHg is used / DCS (dichlorosilane) chemical in the LPCVD reactor, 75 nm of Si 3 N4 sidewall protection layer conforms to the structure on the structure 10. For example, SVGVTR 7 0 0 with the following operating conditions 0 + Reactor (sold by SVG-THERMC0, San Jose, USA) N N 3 Flow rate: 2 0 0 sccm DCS Flow rate '40 seem Pressure: 1 1 0 mTorr

Temperature: 7 2 0 ° C Next, the structure was built in the aforementioned AE 5200 RIE reactor, and an optical etching endpoint system was used to detect the Si 02 gate layer 12 exposure (3 8 6 · 5 nm irradiation), and each向 异性 地 # 刻. _ Suitable operating conditions are: CHF3 flow rate: 100 seem

He02: 14 seem pressure: 1 0 0 millitorr

O: \ 64 \ 64647.ptc Page 8 478064 _ Case No. 89111050 9C; π / month 75 ^ S Correction _ V. Description of the invention (5) Power: 50 0 Watt RF frequency: 1 3. 56 MHz This etching step Termination of the formation of S i 3N4 insulating spacers (which are indicated as 19 in FIG. 6). The step of anisotropically etching the polysilicon by using the patterned Si02 pillar top layer 15 as an in-situ hard mask is the most important and critical. First, since the formation of a Si02 thin film that can maintain the thickness integrity of the Si02 gate layer 12 and prevent the implantation of hydrogen atoms generated by HBr compounds in the silicon substrate 11 during this step, it is a positive situation. Unfortunately, this step cannot produce GC lines 14 with the required vertical profile, which is necessary to form suitable Si3N4 spacers in subsequent processing steps, but can determine the I GF ET velocity electrical parameters. During this step, significant corrosion of the top layer 15 of the Si 02 pillar is generated, which then causes the side wall of the layer 14 polysilicon material to invade, resulting in a typical GC line 14, as shown in FIG. In fact, since the Si 02 material of layer 15 is removed at the corner portion, the polysilicon material of layer 1 4 is not protected during the etching, causing parasitic polysilicon etching, which results in A tapered GC line of a typical base. This phenomenon can be explained by the poor polysilicon: pillar top Si02 selectivity (the ratio of polysilicon-and Si02 #etch rate) in the etching step of about 4.1. In addition, referring now to FIG. 5, it is necessary to understand that the angle 0 defined by the GC line 14 side edges and the substrate surface is not satisfactory because it is quite far from the vertical profile required for subsequent wafer processing steps, and especially the ion implantation. Steps to define diffusion (source / drain) regions. The following table I shows that the value of the angle 0 according to the GC line 14 is located at the edge or center of the wafer and the partition or nested area.

Table I Θ 1 Θ 2 Θ 3 Θ 4 Edge nesting Edge separation Center nesting Center separation 85 ° 83. 82. 80.

O: \ 64 \ 64647.ptc Page 9 478064 Amendment No. 89111050 V. Description of the Invention (6) The above-mentioned HBr / He02-based process suitable for producing the required SiOx protective layer is unacceptable because it cannot produce GC lines of the desired vertical profile. So far, several different chemicals have been developed for etching polysilicon materials related to the Si 02 material on the top layer 15 of the pillar, but they are somewhat relevant in forming the vertical profile of the Si Ox film 18 and / or the G C line. SUMMARY OF THE INVENTION® Therefore, the main object of the present invention is to provide a plasma etching improvement method for plasma-etching a polysilicon layer over a thin layer of Si 02 via patterned Si 02 pillar top plasma etching in a high-density plasma reactor. It is performed with HB r / He 02 gas mixture, among which TCP / bias power and HBr / He02 gas ratio are optimized. Another object of the present invention is to provide a plasma etching improvement method for plasma-etching a polysilicon layer over a thin layer of Si02 via patterned Si02 pillar top-plasma etching, which is-polysilicon: pillartop Si02 The selection rate is greater than 10: 1. Another object of the present invention is to provide a plasma etching improvement method for etching a polysilicon layer overlying a thin layer of Si 02 via a patterned Si 02 pillar top plasma, in which a polysilicon line has a vertical profile. φ Another object of the present invention is to provide an improved plasma etching method for etching a polysilicon layer over a thin layer of Si 02 via patterned Si 02 pillar top plasma etching, which has been found to be widely applicable to insulating spacer forming processes. . According to the present invention, a thin layer of Si 02 under a predetermined pattern is described.

O: \ 64 \ 64647.ptc Page 10478064 __NEW89111050--year f < month, correction_ V. Description of the invention (7) The method of dry etching a polysilicon layer includes the following steps: According to the predetermined pattern The patterned polysilicon layer is provided with a top layer of Si 02 pillars to form an in-situ hard mask. The resulting structure is placed in a high-density electrical circuit provided with two RF generators to provide TCP (transformer coupling plasma) and bias power. On the static * chuck in the vacuum chamber of the slurry etcher; the exposed area of the polysilicon layer is anisotropically etched to the bottom Si02 thin layer through the patterned Si02 pillar top chemical, mainly HBr / He02, where The TCP / bias power ratio is (2 0, 50) and the HBrVHe02 gas flow rate is (1.95), so the polysilicon: column top Si i 〇2 selectivity is greater than 1 〇 :; [, and Polysilicon lines with a substantially vertical profile. A method for forming a silicon nitride spacer on a polysilicon line according to the present invention includes the following steps: a polysilicon layer and a patterned Si02 pillar formed thereon are provided with a gate electrode Si02 thinly coated Layer of Shixi substrate; place the structure on an electrostatic chuck in a vacuum chamber equipped with two generators to provide TCP (transformer coupling plasma) and a high-density plasma etcher with bias power; The exposed area is anisotropically etched to the bottom Si02 gate thin layer through a patterned 3102 pillar top-centered chemical with a core of 1 " / 1 ^ 02, where the TCP / bias power ratio is ( 20, 50) and HBr / He02 gas flow rate is ❿ (1.9, 5), so the selectivity of polysilicon: 枉 top Si0 2 is greater than 10: 1, which results in polysilicon lines with a substantially vertical profile; during this etching Removing the S 1 02 pillar top material of the patterned layer and the Si 02 protective thin layer formed on the entire surface; and

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»I 478064 __Case No. 89111050 6 years / ° Month Day amendment_ V. Description of the invention (8) Deposit the cladding layer of Si 3N4 material on the structure and anisotropically etch this layer to the polysilicon line sidewall The desired Si3N4 spacer was formed on it. Preferably, the TCP / bias power and HBr / He02 gas flow rates are equal to about 28 and 2. 4 5 respectively, so the polysilicon: column top Si 02 selectivity is equal to about 2: 1. The lower bias power can increase the TCP / bias power ratio and therefore increase the polysilicon: Si i02 selectivity at the top of the pillar and the necessary etching anisotropy to produce polysilicon etching at the end of the etching step. GC lines with vertical outlines and square corners. The low He 02 gas flow rate increases the Br / H02 gas flow rate, further improving the verticality of all rounds passing through the wafer. This novel feature, which is believed to be a feature of the invention, is described in the scope of the patent application. However, the present invention and other objects and advantages can be more clearly understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings. A detailed description of a preferred specific example Referring to FIG. 4, the above-mentioned anisotropic etching step of polysilicon combines the positive and negative aspects. As mentioned earlier, it is obvious that the Si OX film is formed to protect the substrate from the hydrogen atom, and it is unsatisfactory to form GC lines with a base and a vertebral profile. The inventor of the present invention conducted several experiments to consider individually or consider each other in combination to determine the influence of each process parameter. If the state of the above-mentioned existing etching technology can be optimized instead of being completely novel, the goal can be determined. Experiments have shown that the ratio of coupling two process parameters is particularly important in this regard. TCP / bias power ratio and HBr / He02 gas flow rate. Xin has two RF generators, one generates TCP (Transformer Coupled Plasma) power and the other generates bias power. TCP power is used to generate chemical species, depending on the different gases introduced into the high density plasma reactor. Therefore, it determines the plasma chemical activation to adjust the etching rate and uniformity. Bias power

O: \ 64 \ 64647.ptc Page 12 478064 Amendment No. 89111050 V. Description of the invention (9) Plasma is more ionized and plasma density is increased. Because the plasma is more conductive in this example, it is also not conducive to faster etching of the top layer 15 of the patterned Si02 pillar, resulting in a lower polysilicon: Si02 selection rate at the pillar top. On the other hand, in the HBr / He02 chemical, Η B r is used to etch and remove the polysilicon of layer 14. He 02 is used to generate the oxygen molecules required to form the Si 10 X thin film 18 of the entire surface of the protective structure 10, and ′ especially maintains the thickness integrity of the Si 02 gate thin layer 12. The Si Ox thin film 18 avoids damage to the silicon substrate, which may be caused by hydrogen ions generated by the dissociation of HBr. As in the state of the prior art polysilicon etching step above, the high plasma density TCP / bias power ratio is equal to about 14 and the HBr / He 02 gas flow rate is equal to about 1.62, making this chemical very agglutinating, the fact Above, due to these operating conditions, the thickness of the patterned Si02 pillar top layer 15 is mainly consumed at the corner of the pillar top, as can be clearly seen in Figure 4. The inventors have unexpectedly confirmed that the TCP / bias power and H BiVHe02 gas flow rate significantly higher than the state of the prior art etching step described above can maintain the patterned Si 02 pillar top layer 15 thickness through the high uniformity of the wafer Holistic and relevant_ Improve this step locally. Although the number of oxygen molecules generated by the plasma will decrease due to the decrease in the flow rate of the He02 gas, the Si 0 X film 18 is still formed due to the relative decrease in the bias power. Now, according to the present invention, the bias power and He02 gas parameters have increased importance in the improved polysilicon etching process of the present invention. As a result, the G C line 1 4 ′ is no longer tapered and now has substantially vertical outlines in both the separated and nested areas, regardless of whether these areas are located at the wafer center or edge. The initial structure is identical to the structure of FIG. 3 in all associations. The method of the present invention reduces the implementation of the same LAM TCP 9400 etchant previously described for comparison and the following operating conditions.

O: \ 64 \ 64647.ptc Page 13 478064 Case No. 89111050 γ ○ Revised in May 5. Explanation of the invention (10) HBr flow rate Η E 0 2 flow rate pressure TCP power bias power RF frequency Now, in HBr / He02 gas selection The ratio is equal to the minimum polysilicon flow rate required to obtain the structure of Si02. The top of the column is 15 '. It can be noticed that the angle is 18 °. The following table II shows the angle comparison. 5 5 watts: 13.56 MHz In the above optimization process, the TCP / bias power ratio and volume flow rate are equal to 2 8 and 2. 4 5 respectively, so polysilicon: column top S i0: about 20: 1. However, in a more general example, in order to achieve the selection ratio value of 10: 1: column top Si02, the power ratio and gas type have been determined to be in the range of (2 0,50) and (1.99,5). . < Shown in Fig. 4A. As can be clearly seen in Fig. 4A, what is obtained now substantially maintains its original thickness with square corners. The Si Ox protective film also coated on the entire surface of the structure 10 'shows a dramatic improvement corresponding to the state of the etching step of the present technique as outlined in Table I by the method of the present invention.

Table I I Θ 1 Θ 2 Θ 3 Θ 4 Edge nesting Edge separation Center nesting Center separation 90. 88. ·· 88. 88. As can be seen in Table I, all angles are now close to 90 °. This novel power and gas flow rate has been found to dramatically limit the erosion of the patterned Si 02 pillar top layer 15 'to produce GC lines 1 4' with the desired vertical profile while still maintaining

II

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Year-old € month

Amendment 5. Description of Invention (11)

SiOx film to ensure its important size. As a result, the undesired conical shape and the base in the aforementioned GC line. The Si 3N4 spacer formation process is illustrated continuously in FIGS. 5A and 6A, but with reference to the same processes previously described with reference to FIGS. 5 and 6. The comparison of the structures 10 and 10 'in the phase A of Fig. 6 and Fig. 6 is explained by all correlations. In Fig. 6A, the vertical contour of the G C line 14 and the structure of the Si 3 N4 spacer 1 9 'are quite satisfactory for the subsequent manufacturing steps. Although the present invention is specifically described in terms of its preferred specific examples, those skilled in the art must understand that the foregoing and other changes to the state and details can be changed without departing from the spirit and scope of the invention, although the method of the invention as described above has been The development utilizes the LAM TCP 9400 etcher, but can be extended to other high-density plasma etchers with two RF sources. <

O: \ 64 \ 64647.ptc Page 15 478064 Case No. 89111050 9 ° year / c month is ^ day correction diagram Simple illustration Simple illustration Figure 1-6 shows the experience of the conventional S i 3 N 4 spacer formation process Of the semiconductor structure. Figures 4A-6A show the structure of the structure of Figure 3 undergoing the necessary steps of anisotropically cutting the polysilicon layer according to the present invention (directly corresponding to Figures 4-6). Description of Symbols of Schematic Elements 10 Structure 11 $ Substrate 12 Silicon Oxide (Si 02 0) Layer 13 GC Stack 14 Poly Silicon Layer 15 S i 0 2 Top Layer of Post 16 Dielectric Anti-Reflection Top Coating (SixOyNz) Layer 17 Photoresist Agent layer 18 S i Ox film 19 Insulating S i 3 N 4 spacer

〇; \ 64 \ 64647.ptc page 16

Claims (1)

478064 ^ 0! 〇, 25 Case No. 89111050 Amendment VI. Patent Application Scope 1. A method for dry etching to form a polysilicon layer on a bottom Si02 thin layer according to a predetermined pattern, including the following steps: patterning according to the predetermined pattern A Si 02 pillar top layer is provided on the polysilicon layer to form an in-situ hard reticle; the resulting structure is placed in a high-density power supply provided with two RF generators to provide TCP (transformer coupling plasma) and bias power. On the electrostatic chuck of the vacuum chamber of the slurry etcher; the exposed area of the polysilicon layer is anisotropically etched to the bottom S i 02 thin layer through the patterned Si02 pillar top chemical of HBr / He02, The TCP / bias power ratio is (2 0, 50) and the H Br / H e 02 gas flow rate is (1.9, 5), resulting in polysilicon lines with a substantially vertical profile. < 2. The method according to item 1 of the scope of patent application, wherein during the etching step, a protective Si Ox thin layer is formed to coat the entire surface of the structure. 3. The method according to item 1 of the scope of patent application, in which TCP / bias power and H Br / H e02 gas flow rates are equal to about 28 and 2. 45, respectively, so polysilicon: Si02 selection rate at the top of the column is equal to about 20 ·· 1. 4. The method according to item 1 of the scope of patent application, wherein the high-density plasma etcher is LAM TCP 9 400 and the operating conditions are: HBr flow rate H e 0 2 flow rate pressure TCP power bias power RF frequency 250 seem 9 seem 6 millitorr 1 35 watt 5 5 watt 13.56 MHz O: \ 64 \ 64647.ptc Page 17 478064 Amendment 1 ^ 89111050 6. Scope of Patent Application 5. — A method for forming silicon nitride spacers on polysilicon lines, including the Ding Lie step: using polysilicon layer and The top layer of the patterned Si02 pillar is formed thereon to provide a Shixi substrate coated with a thin layer of the gate Si02; the structure is placed on two RF generators to provide TCP (transformer coupling plasma) and Bias power on the electrostatic chuck of the vacuum chamber of the high density plasma etcher; the exposed area of the polysilicon layer is anisotropically etched to the bottom S i 02 via the patterned Si02 pillar top chemical, mainly HBrVHe02. Thin gate layer, where the TCP / bias power ratio is (2 0, 50) and Η B r / H e 02 gas flow rate is (1, 9, 5), resulting in a polymer with a substantially vertical profile Silicon lines; removing the Si 02 pillar top material of the patterned layer and the Si 02 protective thin layer formed on the entire surface during the etching; and depositing the cladding and anisotropy of Si 3N4 material on the structure This layer is etched to form the desired Si3N4 spacers on the sidewalls of the polysilicon line. 6. The method according to item 5 of the scope of patent application, in which TCP / bias power and Η B r / H e 02 gas flow rates are equal to about 2 8 and 2. 4 5 respectively, so polysilicon: column top S i 02 is selected The rate is equal to about 20: 1. 7. The method according to item 5 of the scope of patent application, wherein the high-density plasma etcher is a LAM TCP 9 40 0 etcher and the operating conditions are:: 2 5 0 seem: 9 seem: 6 millitorr: 1 3 5 watts HBr flow rate He 02 flow rate pressure TCP power O: \ 64 \ 64647.ptc Page 18 478064 O: \ 64 \ 64647.ptc Page 19