4 63 08 9 A7 B7 五、發明説明（1 ) 發明領域: (讀先間讀背面之注意事項再填寫本頁) 本發明係有關於一種微控制器架構及其方法，特別地 是，有關於一種内建可規晝成主要及快取兩用記憶體之微 控制器架構及其方法。 發明背景： ' 個人電腦之發展日新月異，以Pentium中央處理器爲例 ，内建有KB級之快取記憶體，來提昇系統之效能。而以目 前應用程式之複雜而言，動輒達數十MB，甚至上百MB大 小，因此内建之快取記憶體在未命中（miss)時，常常需要 與外部之L2快取記憶體或主記憶體更新資料，其中快取記 憶體係爲靜態隨機存取記憶體（SRAM)，而主記憶體則爲 動態隨機存取記憶體（DRAM)，故快取記憶體之存取速度 較主記憶體快上數倍。 經濟部中央標準局員工消費合作社印製 爲能簡單説明起見，在此不管快取記憶體爲寫回（write back)或窝透（write through)模式。以K B級之快取記憶體， 相對於日漸龐大之MB級應用程式，未命中（miss)的機率大 增，快取記憶則需頻頻透過匯流排與外部記憶體更新資料 ，而匯流排之有限頻寬又非專供記憶體獨用，使得系統效 能大幅降低。 習知技藝所提出之一解決方案，係爲於系統中提供一具 有高頻寬之記憶體匯流排（RAMBUS)給記憶體專用，如此 一來，則使得整個系統架構徹底改變，增加系統業者之成 本，並有相容性之問題；RAMBUS尚有一問題爲使CPU之 製造複雜度提高；因爲CPU要額外提供RAMBUS數十隻腳 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 463 08 3 A7 B7 五、發明説明（2 ) 位來傳輸資料，增加封裝CPU時之困難度，且RAMBUS須 有一與眾不同之專屬時脈與匯流排，增加主機板設計上之 複雜性。 L1快取記憶體因爲内建於CPU，所以效能及速度較必須 透過匯流排之CPU外部的L 2快取記憶體高，且SRAM又遠 較傳統DRAM快；但是由於天生製程上之限制，L1及L2快 取記憶體以目前技術之極限，僅能達到數百KB大小，依然 必須仰賴傳統DRAM來解決系統對記憶體之需求。更具體 而言，集積1個bit之SRAM則至少可以集積10 bits DRAM於 同一處，加以DRAM製程之成熟，使得市面上頂多看到一 顆256 Kb封裝之SRAM，但DRAM則可達一顆封裝64 Mb以 上。以Pentium CPU爲例，内部亦不過僅内建8 KB資料快 取記憶體及8 KB楫令快取記憶體（共I6 KB Cache)。半導 體製程的進步固然可使内建之快取SRAM增加，但因其爲 K B等級，幫助依然有限，對於未命中（miss)率之降低沒有 根本之改善。 經濟部中央標準局員工消費合作社印製 (請先聞讀背面之注意事項再填寫本頁) 本發明爲解決先前技藝之種種問題，揭示一種内建可規 晝成主要及快取兩用記憶體之微控制器架構及其方法。以 CPU爲例，CPU内建大量DRAM，當應用程式小時，可直接 當做内建之主記憶體，而不須仰賴外部記憶體，不僅不會 有未命中問題（即完全命中），並可享有猝發模式（burst mode)之快速優點；當應用程式大時，則指定内建之記憶 體配合一標籤記憶體來完成一快取記憶體架構，由於内建 之記憶體達數十MB规模，資料命中率十分高、大幅降低 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 46308 9 A7 B7 五、發明説明（3 CPU至外部記憶體抓取新資料之頻率，使得系統效能大幅 提昇，且能減少整個系統功率之消耗。 由於CPU内建之S己憶體已相當大，L2快取記憶體之設置 則顯得多此一舉，少了 L2快取記檍體則CPU之脚位大量減 少，或者可將多餘腳位用’於其他方面；如此一來，不僅降 低了 cpu之生產成本，並有多餘腳位供CPU設計更新之功 能，且能達到省電之目的；對主機板設計者而言，因架構 簡化，使5又s十上更谷易，並使成本降低，對使用者而言， 則是以更少的代價獲得更佳的系統性能。 以上之説明係爲方便了解而以個人電腦之中央處理器舉 例説明之’本發明之新穎架構可以廣泛運用於各式微控制 器（micro controller)中，而可使系統獲得絕佳之性能。 附帶説明的是，快取記憶體在設計上，目前有直接映射 (direct map)、雙路（two ways)映射及四路（four ways)映射 等架構，由於程式在執行時多少會有連續性與結構性，例 如：程式段本身於兩個4 K B大小之子程式作迴圈呼叫，而 資料段則爲兩個4KB之查表（l〇〇kup table)互相對應，這是 實際上常有的情形，故雙路映射及四路映射大體上來説命 中率會較南與直接映射相較來得合適而有效率。 發明概诚 本發明揭示一種内建可規畫成主要及快取兩用記憶體之 微控制器架構，該微控制器架構包含一微控制器；一暫存 器；—雙用途記憶體，内建於該微控制器之中，由該暫存 器之内容値來決定规晝該雙用途記憶體爲一主記憶體或一 -6 衣紙張尺度適用中_家標準（CNS ) A4規格（21〇X297公釐） ,I — I---0 裝—— (諳先聞讀背面之注意事項再填寫本頁) 訂. 鎚濟部中央襟準局員工消費合作社印製 4 63 08 9 A7 B7 五、發明説明（4 ) 快取記憶體；以及一標籤記憶體，由該暫存器之内容値來 決定致能或抑止該標籤記憶體之運作。 (請先聞讀背面之注意事項再填寫本頁) 本發明亦揭示一種内建一可规畫成主要及快取兩用記憶 體於一微控制器的方法，該方法包含備置一暫存器；以及 備置二標籤記憶體，由該暫存器之内容値來決定致能或抑 止該標籤記憶體之運作；其中，該兩用記憶體係由該暫存 器之内容値來決定規晝爲一主記憶體或一快取記憶體。 圖式簡單説明 圖1係本發明之方塊圖。 圖2係快取記憶體之直接映射架構。 圖3係快取記憶體之雙路映射架構。 圖4係四路映射架構中標籤記憶體之一較佳具體實施例 結構圖。 圖5係圖4中LRU欄之位元設定表之一實施例。 圖6係圖4中LRU攔之一解説表例。 圖7係本發明之另一具體實施例。 圖8係本發明之另一具體實施例。 圖9係本發明之另一具體實施例。 經濟部中央標準局員工消費合作社印製 圖式主要元件對照表 1 微控制器 21 快取記憶體 11 暫存器 22 標籤記憶體 12 雙用途記憶體 221 有效欄 13 標龜記憶體 222 高位址攔 14 訊號線 31 快取記憶體 -7- 本紙張又度適用中國國家標準（CNS ) A4規格（210'乂297公釐） 4 63 08 9 A7 B7 五、發明説明（5 ) 311 資料路0(快取記憶體0) 34 多工器 312 資料路1(快取記憶體1) 41 有效攔 32 標籤記憶體 42 高位址攔 321 有效搁1 43 LRU欄 322 有效櫊0 ' 71、 81、91 微控制器 323 高位址路1 711、 81 卜 911 雙用途記憶體 324 高位址路0 712 、82、93 標籤記憶體 325 最近使用記錄(LRU)攔 Ί1、 82、92 暫存器 331 匯流排 73、 83、94 訊號線 332 匯流排 (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 發明詳細説明 ' 如圖1所示，係本發明之一具體實施例的示意方塊圖， 其包含一微控制器（1); 一暫存器（11); 一雙用途記憶體 (12)，内建於該微控制器（1)之中，由該暫存器（11)之内容 値來決定規晝該雙用途記憶體（12)爲一主記憶體或一快取 記憶體；以及，一標籤記憶體（13)，由該暫存器（11)之内 容値來決定致能或抑止該標籤記憶體（1 3 )之運作。舉例説 明之，該暫存器（11)可爲一位元寬，其中該暫存器（11)爲 0 (或1)時，指定該控制器（1)進入一般模式而规晝該雙用 途記憶體（12)爲主記憶體，並抑止該標籤記憶體（13)之運 作，此時該微控器（1)内部之雙用途記憶體（12)係運作爲一 主記憶體架構；而當該暫存器（11)爲1 (或0 )時，指定該微 控制器（1)進入快取模式而規畫該雙用途記憶體（12)爲快取 記憶體，並致能該標籤記憶體（13)以配合該快取記憶體之 -8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 63 08, 9 經濟部中央標準局員工消費合作社印製 A7 B7___ 五、發明説明（6 ) 運作，而完成快取記憶體架構，該快取模式係可爲直接映 射、二路映射或四路映射架構。於微控制器（1)内所集積之 雙用途記憶體（12)可爲動態隨機存取記憶體、靜態隨機存 取記憶體或可重複抹除式記憶體等。以目前半導體製程技 術而言，於微控制器（1)中'集積大量動態隨機存取記體，將 可使該微控制器（1)在碰到大型應用程式而進入快取模式時 ，達到較高的快取命中率（Cache Hit Rate);當碰到中、小 型應用程式時，比較可能進入主記憶體模式，而完全不需 要任何外部記憶體來配合運作。 如圖2所示，係爲快取記憶體之直接映射（Direct Map)架 構，以根據本發明所實施之微控制器（1)内集積64 Mbit DRAM爲例，其相當於8M byte大小，此+爲目前DRAM製程_ 相當常見之技術。將該微控制器（1)視爲Pentium CPU定址 架構來解説，Pentium CPU位址腳位共32隻，定址能力達4 GB，即[3 1 : 0 ]，因爲pentium CPU爲32位元CPU，線大小 (Line Size)爲32 bytes，故快取記憶體（21)之X及Y定址可 爲 29x29(輸出 29x29x25bytes= 8M bytes);標籤記憶體（2 2 )包 含一用以記錄快取記憶體（21)中所儲存資料之高位址的位 址攔（222)及一代表該資料有效與否之有效（Valid)欄（221) ’標籤記憶體（21)之進入點（entry)爲218，代表絕對位址[22 :5 ] ’位址欄（222)則記錄資料之高位址部分[3 1 : 23]，共 9位元’加上直接映射模式之有效欄爲1位元，故標籤記憶 體（21)之大小爲2 1 8X 1 0 = 25 6Kx 1 0，以有效攔（221)爲1代 表資料有效，而〇代表資料無效；以上資訊可獲得快取記 -9- (請先聞讀背面之注意事項再缜寫本頁)4 63 08 9 A7 B7 V. Description of the invention (1) Field of the invention: (Read the precautions on the back and then fill out this page) The present invention relates to a microcontroller architecture and its method. In particular, it relates to A microcontroller architecture with built-in programmable main memory and cache dual-purpose memory and its method. Background of the Invention: '' The development of personal computers is changing rapidly. Take Pentium CPU as an example. It has KB-level cache memory built-in to improve the performance of the system. As far as the complexity of current applications is concerned, it can reach tens of MB or even hundreds of MB in size. Therefore, when the built-in cache memory is missed, it often needs to communicate with external L2 cache memory or main Memory update data, where the cache memory system is static random access memory (SRAM), and the main memory is dynamic random access memory (DRAM), so the cache memory access speed is faster than the main memory Several times faster. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs For the sake of simplicity, it does not matter whether the cache memory is write back or write through mode. With KB-level cache memory, compared to the increasingly large MB-level applications, the chance of miss is greatly increased. Cache memory needs to frequently update data through the bus and external memory, and the bus is limited. The bandwidth is not exclusively used by the memory, which greatly reduces the system performance. One of the solutions proposed by Xizhiyi is to provide a high-bandwidth memory bus (RAMBUS) in the system for the exclusive use of memory. In this way, the entire system architecture is completely changed and the cost of the system operator is increased. There is also a compatibility problem; there is still a problem with RAMBUS in order to increase the manufacturing complexity of the CPU; because the CPU needs to provide dozens of extra pins for RAMBUS -4- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ) 463 08 3 A7 B7 V. Description of the invention (2) Bits to transfer data, increasing the difficulty of packaging the CPU, and the RAMBUS must have a unique exclusive clock and bus, increasing the complexity of the motherboard design. Because the L1 cache memory is built into the CPU, the performance and speed are higher than the L 2 cache memory outside the CPU that must pass the bus, and the SRAM is much faster than the traditional DRAM. However, due to limitations in the natural process, L1 And the L2 cache memory is limited by the current technology, which can only reach hundreds of KB in size. It must still rely on traditional DRAM to solve the system's memory requirements. More specifically, at least 1 bit of SRAM can be integrated at least 10 bits of DRAM in the same place. The maturity of the DRAM process has made it possible to see at most one 256 Kb packaged SRAM on the market, but DRAM can reach one. Package over 64 Mb. Taking Pentium CPU as an example, it only has 8 KB data cache memory and 8 KB command cache memory (I6 KB Cache) built in. The progress of the semiconductor system process can certainly increase the built-in cache SRAM, but because it is a KB class, the help is still limited, and there is no fundamental improvement in reducing the miss rate. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page). The present invention is to solve various problems of the previous art, and to reveal a built-in programmable main memory and cache memory Microcontroller architecture and method. Take the CPU as an example. The CPU has a large amount of DRAM built-in. When the application program is small, it can be directly used as the built-in main memory instead of relying on external memory. The fast advantage of burst mode; when the application is large, the built-in memory is specified in conjunction with a tag memory to complete a cache memory structure. Since the built-in memory reaches tens of MB, the data The hit rate is very high, and the paper size is greatly reduced. The Chinese standard (CNS) A4 specification (210X297 mm) is applicable. 46308 9 A7 B7 V. Description of the invention (3 The frequency of CPU to external memory to capture new data, which makes the system performance greatly. Improve and reduce the power consumption of the entire system. As the internal memory of the CPU is already quite large, the setting of the L2 cache memory appears to be more than one move. Without the L2 cache memory, the CPU pins are greatly reduced. Or, you can use the extra pins for other purposes; in this way, not only reduces the production cost of the CPU, but also has extra pins for the CPU design update function, and can save power Purpose; For motherboard designers, because of the simplified architecture, it is easier to make 5s and 10s lower, and the cost is reduced. For users, it is better to obtain better system performance at less cost. The description refers to the central processing unit of a personal computer as an example for easy understanding. The novel architecture of the present invention can be widely used in various types of micro controllers, so that the system can obtain excellent performance. The design of the cache memory currently includes direct map, two ways mapping, and four ways mapping. Because the program has some continuity and structure when it is executed For example, the program segment itself makes a loop call on two 4 KB subprograms, and the data segment corresponds to two 4 KB lookup tables (100kup tables). This is actually a common situation. Therefore, the two-way mapping and the four-way mapping are generally more suitable and efficient than the south and direct mapping. Summary of the Invention The present invention discloses a built-in micro-memory that can be programmed into the main and cache memory. control Controller architecture, the microcontroller architecture includes a microcontroller; a register;-dual-purpose memory built into the microcontroller, the contents of the register determine the regulation of the dual-day Purpose memory is a main memory or a -6 paper size. Applicable in China_Home Standard (CNS) A4 specification (21 × 297 mm), I — I --- 0 installed— (谙 first read the back of the Note: Please fill in this page again.) Order. Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 4 63 08 9 A7 B7 V. Description of the invention (4) Cache memory; and a tag memory from the register Content to determine whether to enable or inhibit the operation of the tag memory. (Please read the notes on the back before filling this page) The present invention also discloses a built-in method that can be programmed into the main and cache dual-use memory in a microcontroller. The method includes preparing a register ; And prepare two tag memories, the content of the register determines whether to enable or inhibit the operation of the tag memory; wherein, the dual-purpose memory system is determined by the contents of the register to regulate the day to day Main memory or a cache memory. Brief Description of the Drawings Figure 1 is a block diagram of the present invention. Figure 2 shows the direct mapping architecture of cache memory. Figure 3 is a two-way mapping architecture for cache memory. FIG. 4 is a structural diagram of a preferred embodiment of a tag memory in a four-way mapping architecture. FIG. 5 is an embodiment of a bit setting table of the LRU column in FIG. 4. FIG. 6 is an explanatory table example of one of the LRU blocks in FIG. 4. FIG. 7 shows another embodiment of the present invention. FIG. 8 shows another embodiment of the present invention. FIG. 9 shows another embodiment of the present invention. Comparison table of main components printed by employees' cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 1 Microcontroller 21 Cache memory 11 Register 22 Tag memory 12 Dual-use memory 221 Valid column 13 Marker memory 222 High address block 14 Signal line 31 Cache memory-7- This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 '乂 297 mm) 4 63 08 9 A7 B7 V. Description of the invention (5) 311 Data path 0 ( Cache memory 0) 34 multiplexer 312 data path 1 (cache memory 1) 41 effective block 32 tag memory 42 high address block 321 effective hold 1 43 LRU column 322 effective 櫊 0 '71, 81, 91 micro Controller 323 high address path 1 711, 81, 911 dual-purpose memory 324 high address path 0 712, 82, 93 tag memory 325 recent use record (LRU) block 1, 82, 92 register 331 bus 73, 83, 94 signal line 332 bus (please read the precautions on the back before filling out this page) Detailed description of the invention printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs' As shown in Figure 1, it is a specific embodiment of the present invention Schematic block diagram of its package A microcontroller (1); a register (11); a dual-purpose memory (12), which is built into the microcontroller (1) and is derived from the contents of the register (11) It is determined whether the dual-purpose memory (12) is a main memory or a cache memory; and a tag memory (13) is determined by the contents of the register (11) to be enabled or disabled The operation of the tag memory (1 3). As an example, the register (11) can be one bit wide, and when the register (11) is 0 (or 1), the controller (1) is designated to enter the general mode and the dual-purpose is regulated. The memory (12) is the main memory and inhibits the operation of the tag memory (13). At this time, the dual-purpose memory (12) inside the microcontroller (1) operates as a main memory structure; and When the register (11) is 1 (or 0), designate the microcontroller (1) to enter cache mode and plan the dual-purpose memory (12) as cache memory, and enable the tag Memory (13) to match the cache memory -8- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 4 63 08, 9 Printed by A7 B7___ Fifth, the invention description (6) operation, and complete the cache memory architecture, the cache mode can be a direct mapping, two-way mapping or four-way mapping architecture. The dual-purpose memory (12) accumulated in the microcontroller (1) may be a dynamic random access memory, a static random access memory, or a re-writable memory. In terms of current semiconductor process technology, 'integrating a large number of dynamic random access memory in the microcontroller (1) will enable the microcontroller (1) to reach cache mode when it encounters large applications. Higher Cache Hit Rate; When encountering small and medium applications, it is more likely to enter the main memory mode without any external memory to cooperate with it. As shown in FIG. 2, it is a direct map architecture of the cache memory. Take the integrated 64 Mbit DRAM in the microcontroller (1) implemented as an example, which is equivalent to 8M byte. + Is a fairly common technology for current DRAM processes. Consider this microcontroller (1) as a Pentium CPU addressing architecture to explain. There are 32 Pentium CPU address pins and the addressing capacity is 4 GB, [3 1: 0], because the pentium CPU is a 32-bit CPU. The line size is 32 bytes, so the X and Y addresses of the cache memory (21) can be 29x29 (output 29x29x25bytes = 8M bytes); the tag memory (2 2) contains a record memory The address block (222) of the high address of the data stored in (21) and a valid (Valid) column (221) representing the validity of the data (221) 'The entry point of the tag memory (21) is 218, Represents the absolute address [22: 5] 'The address column (222) is the high address part of the recorded data [3 1: 23], a total of 9 bits' plus the effective column of the direct mapping mode is 1 bit, so the label The size of the memory (21) is 2 1 8X 1 0 = 25 6Kx 1 0, and the effective block (221) is 1 to indicate that the data is valid, and 0 means that the data is invalid; the above information can be cached-9- (please first (Read the notes on the back of this article before rewriting this page)
463 08 9 A7 B7 五、發明説明（7 ) 憶體中資料之位址[3 1 : 5 ]及其有效性；又快取記憶體之 運作係以線大小（Line Size)爲單位，pentium CPU之線大小 爲32 bytes(32=25)，故位址[4 : 0]可以被忽略。以此説明 直接映射模式之定址方式。若圖1中暫存器（i丨）指定Cpu進 入主記憶體模式，則8M iytes之記憶體（21)全部當做主記 憶體使用，並抑止標籤記憶體（22)之運作。 如圖3所示’係一快取§己憶體之雙路（tw〇 ways)映射架構 ，依圖2之假設，原來8M bytes之快取記憶體（3 1)被视爲兩 路：資料路0(311)及資料路1(312)，各佔4M bytes大小； 標籤記憶體（3 2)之高位址欄亦分別被視爲兩路：高位址路 0 (324)及高位址路1 ( 3 2 3 )，而與資料路〇 (3丨1)及資料路 1(3 12)相應配合；標籤記憶體（32)亦包含有效攔1(321)與 有效欄0 (322)，以分別相應表示資料路〇 (3 11)及資料路 經濟部中央標準局員工消費合作社印製 ---；------0裝—— (請先聞讀背面之注意事項再填寫本頁― 1 (3 12)中資料之有效性；標籤記憶體（32)尚包含一最近使 用欄（least recently used, LRU)，以代表快取記憶體（3 1)相 應資料的那一路（路0或路1)是最近被使用到，因爲往往最 近被使用到的資料，下次亦較可能被用到而予以保留，當 下次快取未命中（Cache miss)時，則優先剔除兩路中較不 常用之一路的資料；在此雙路映射架構下，LRU攔只須1 位元即可完整表示快取記憶體（3 1)之最近使用狀況。因爲 快取模式被設計爲雙路映射，故該等高位址路1 (323)、路 0 (324)及資料路〇 (3 11)、路1 (3丨2)之定址進入點（entry)皆 變爲217( 218 + 2 )，其代表位址[21 : 5 ]，而高位址欄所記 錄之高位址爲[3 Γ: 22]，較直接映射架構多一個位元。合 -10- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 63 08 9 經濟部中央標率局員工消費合作社印製 A7 B7 五、發明説明（8 ) 起來表不絕對位址之[3丨：5 ]，類似地，線大小（32 bytes) 所代表之[4 : 0 ]被忽略。於此例中，標籤記憶體（32)之 (321)〜（325)之欄寬合計爲（1 + 1 + ι〇+ι〇+ι)，故標籤記 隐 a豊（32)之大小爲 217x( ! + ! + i 〇 + 1 〇 + 】）=128 Κχ23。最後 cpu透過匯流排經由多工器（34)選擇快取記 憶體（3 1)兩路資料中所要的那—路資料。 更複雜的四路映射架構，亦可同理推知，快取記憶體 (21)將被等分爲四等分（路〇〜路y，各佔2M Bytes ;而標 籤记隐體（22)所包含的資訊，大致上有有效欄（41) v〇〜v 3 共4位兀、高位址攔〇〜3(42)及LRU攔（43)。比較特別的是 LRU欄於四路映射架構下，已無法用一個位元完整表示， 較佳者係以三個位元表示。 如圖5所示，係LRU欄相應於四路映射之位元設定表之 實施例’ X表保留（don，t care)，簡單説明之，LRU 2係有 關於路0〜路3，而以^； i則僅有關於路3及路2，LRu 〇則 僅有關於路1及路〇 ,試圖以最少的位元數代表最大資訊。 如圖6所示，以列表簡單説明LRu欄之運作；首先LRU 〇〜LRU 2被重置爲〇，當讀取路3時LRU 2及lru j設爲〇 ;接著讀取路2時，LRU 2設爲㈣！^ 1設爲丨；讀取路i 時’ LRU 2設爲1而LRU 0設爲0 ;讀取路〇時，LRU 2及 LRU 0皆設爲1;以此方式記錄四路映射架構中，四路資 料之最近使用狀況。 續前述，此例中之標籤記憶體進入點共+ 4)，代 表位址[20 : 5 ]，而圖4中高位址欄記綠高位址[3 j : 21]， ； ；--------◦裝-- (諳先閱讀背面之注意事項再填寫本頁)463 08 9 A7 B7 V. Description of the invention (7) The address of the data in the memory [3 1: 5] and its validity; the operation of the cache memory is based on the line size (Line Size) unit, pentium CPU The line size is 32 bytes (32 = 25), so the address [4: 0] can be ignored. This explains the addressing method of the direct mapping mode. If the register (i 丨) in Figure 1 specifies that the CPU enters the main memory mode, all the 8M iytes memory (21) is used as the main memory, and the operation of the tag memory (22) is inhibited. As shown in Figure 3, it is a two-way (tw〇ways) mapping structure of a cache § memory. According to the assumption of Figure 2, the original 8M bytes of cache memory (31) is considered as two ways: data Path 0 (311) and data path 1 (312), each occupying a size of 4M bytes; the high address column of the tag memory (32) is also considered as two paths: high address path 0 (324) and high address path 1 (3 2 3), and corresponding to data path 0 (3 丨 1) and data path 1 (3 12); the tag memory (32) also contains a valid block 1 (321) and a valid column 0 (322) to Respectively corresponding to the data road 0 (3 11) and the data road printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ---; ------ 0 Pack-(Please read the precautions on the back before filling this page ― The validity of the data in 1 (3 12); the tag memory (32) still contains a least recently used (LRU) column to represent the way of the corresponding data in the cache memory (3 1) (path 0 Or path 1) is used recently, because the data that is often used recently is more likely to be used next time and is retained. When the next cache miss, the two paths are preferentially eliminated. Less commonly used one-way data; under this two-way mapping architecture, the LRU block only needs 1 bit to fully represent the recent use of the cache memory (31). Because the cache mode is designed for two-way mapping Therefore, the address entry points of these high-address paths 1 (323), 0 (324), and data paths 0 (3 11) and 1 (3 丨 2) all become 217 (218 + 2). Its representative address is [21: 5], and the high address recorded in the high address column is [3 Γ: 22], which is one bit more than the direct mapping structure. He-10- This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 63 08 9 Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (8) The absolute address is not shown [3 丨: 5]. Similarly, the line size [4: 0] represented by (32 bytes) is ignored. In this example, the total column width of (321) ~ (325) of the tag memory (32) is (1 + 1 + ι〇 + ι〇 + ι), so the size of label tag a 豊 (32) is 217x (! +! + i 〇 + 1 〇 +)) = 128 Κχ23. Finally, the CPU selects the cache memory through the multiplexer (34) through the bus. (3 1) The more complicated four-way mapping structure can also be inferred from the two-way data. The cache memory (21) will be divided into four equal parts (way 0 ~ way y, 2M each). Bytes; and the information contained in the tagging hidden body (22) generally has a valid column (41) v0 ~ v3 with a total of 4 bits, a high address block 0 ~ 3 (42), and an LRU block (43). What is special is that the LRU column cannot be completely represented by one bit under the four-way mapping structure, and the better one is represented by three bits. As shown in FIG. 5, the LRU column corresponds to an embodiment of the four-way mapping bit setting table. 'X table is reserved (don, t care). For simplicity, LRU 2 is related to ways 0 to 3, and ^; I is only about Road 3 and Road 2, LRu 〇 is only about Road 1 and Road 0, trying to represent the largest information with the least number of bits. As shown in Figure 6, the operation of the LRu column is briefly explained with a list; first LRU 〇 ~ LRU 2 is reset to 〇, when reading Road 3, LRU 2 and lru j are set to 〇; then when reading Road 2, LRU 2 set to ㈣! ^ 1 is set to 丨; when reading path i, LRU 2 is set to 1 and LRU 0 is set to 0; when path 0 is read, both LRU 2 and LRU 0 are set to 1; in this way, the four-way mapping architecture is recorded. Recent usage of the four-way data. Continuing the above, the tag memory entry point in this example is + 4), which represents the address [20: 5], and the high address column in Figure 4 records the green high address [3 j: 21],;; ---- ---- ◦ Install-(谙 Read the precautions on the back before filling this page)
«J -訂-«J -Order-
經濟部中央標準局員工消費合作社印製 463 08 3 A7 A 7 ___B7 五、發明説明（9 ) 較雙路映設再多一個位元（共11位元），則圓4中（41)至（43) 之寬度爲（4 + 44+3)，故此例中四路映設架構之標鐵記憶 體爲2l6(4 + 44 + 3 ) = 64‘Kx5l bits。不論是幾路映射，均可 同理推知，只是LRU欄之設計略有差異。 故依照本發明圖1中微i制器（1)之不同設計架構，依暫 存器（11)之内容値指定規晝雙用途記憶體（12)爲—主記憶 體或快取記憶體；當指定爲快取記憶體時，配合適當之標 籤記憶體（13)完成直接映射或N路映射架構；當指定爲主 記憶體時，則抑止標籤記憶體（13、）之運作。 在實施本發明時，會有許多不同的實施方式，舉例説明 如下。於圖1中，亦可選擇性地將暫存器（11)或標籤記憶 體（13)移到微控制器（1)外，而不必同時集積於微控制器（1) 内部，只是當標籤記憶體（I3)被移到外部實施時，要選擇 速度能夠匹配内建之雙用途記憶體（12)者，同樣可完成本 發明所揭示内建可規畫成主要及快取兩用記憶體之微控制 器架構。 如圖7所示，係將暫存器（72)移出微控制器（71)外實施， 用以透過訊號線（73,)規畫内建之標籤記憶體（712)及雙用途 記憶體（711)之運作。 如圖8所示，係將標籤記憶體（82)移出微控制器（81)外實 施’暫存器（812)透過訊號線（83)规晝内建之雙用途記憶體 (S11)及外部標籤記憶體（S2)之運作方式，此時外部的標籤 記憶體（8 2 )爲能配合内建雙用途記憶體（8 1 u之速度，較 佳選擇宜爲靜態随機存取記憶體。 -12- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ：-' \ ----0裝II (請先聞讀背面之注意事項再填寫本頁) 訂 4 6308 9 A7 _._B7 ____ 五、發明説明（10 ) 如圖9所示’係將暫存器（92)及標籤記憶體（93)皆移出微 控制器（91)外實施，而僅内建雙用途記憶體（911)，暫存器 (92)透過訊號線（94)規畫標籤記憶體（93)及雙用途記憶體 (911)之運作方式。 前述眾多具體實施例中‘，雙用途記檍體、標籤記憶體及 暫存器皆可視應用情況選擇適用的動態隨機存取記憶體、 靜態隨機存取記憶體、同步動態隨機存取記憶體或可重複 抹寫式唯讀記憶體來實施，尤其外部設置之暫存器，更可 以是快閃式唯讀記憶體，以適合不同的應用情形。 本發明同時揭示一種内建一可規畫成主要及快取兩用記 憶體於一微控制器的方法，該方法包含備置一暫存器；以 及備置一標籤記憶體，由該暫存器之内容値來決定致能或 抑止該標籤記憶體之運作；其中，該兩用記憶體係由該暫 存器之内容値來決定規畫爲一主記憶體或一快取記憶體。 (請先鬩讀背面之注意事項再填寫本頁) 'M. 訂 經濟部中央標隼局員工消費合作社印製 -13 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 463 08 3 A7 A 7 ___B7 V. Description of the invention (9) There is one more bit (a total of 11 bits) than Shuangluying, then round 4 (41) to ( The width of 43) is (4 + 44 + 3), so in this example, the standard memory of the four-way mapping architecture is 2l6 (4 + 44 + 3) = 64'Kx5l bits. No matter how many mappings are, the same reasoning can be inferred, but the design of the LRU column is slightly different. Therefore, according to the different design architecture of the micro controller (1) in FIG. 1 of the present invention, according to the content of the temporary register (11), the designated dual-purpose memory (12) is designated as the main memory or the cache memory; When designated as cache memory, complete direct mapping or N-way mapping architecture with appropriate tag memory (13); when designated as main memory, the operation of tag memory (13,) is inhibited. In carrying out the present invention, there are many different embodiments, which are exemplified below. In FIG. 1, the register (11) or the tag memory (13) can also be selectively moved outside the microcontroller (1), instead of being integrated in the microcontroller (1) at the same time, only when the tag When the memory (I3) is moved to an external implementation, it is necessary to select a person whose speed can match the built-in dual-use memory (12), which can also complete the disclosed built-in memory that can be programmed as the main and cache memory. Microcontroller architecture. As shown in FIG. 7, the register (72) is moved out of the microcontroller (71), and is used to plan the built-in tag memory (712) and dual-purpose memory ( 711). As shown in Figure 8, the tag memory (82) is moved out of the microcontroller (81) to implement the 'register (812) through the signal line (83) to regulate the built-in dual-purpose memory (S11) and external The operation mode of the tag memory (S2). At this time, the external tag memory (8 2) is compatible with the built-in dual-purpose memory (the speed of 8 1 u). A static random access memory is preferred. -12- This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm):-'\ ---- 0 Pack II (Please read the precautions on the back before filling this page) Order 4 6308 9 A7 _._ B7 ____ 5. Description of the invention (10) As shown in Figure 9, 'the temporary register (92) and the tag memory (93) are both implemented outside the microcontroller (91), and only the dual-purpose memory is built in The body (911), the register (92) plan the operation mode of the tag memory (93) and the dual-purpose memory (911) through the signal line (94). In the foregoing specific embodiments, the dual-purpose memory bank , Tag memory and register can be selected according to the application of the appropriate dynamic random access memory, static random access memory, synchronous dynamic random access memory It can be implemented by accessing memory or rewritable read-only memory, especially the externally set register can be flash-only read-only memory to suit different application situations. The invention also discloses a built-in A method that can be programmed into a main and cache dual-use memory in a microcontroller, the method includes preparing a register; and preparing a tag memory, which is determined by the contents of the register to enable or Inhibit the operation of the tag memory; the dual-purpose memory system is determined by the contents of the register as a main memory or a cache memory. (Please read the precautions on the back before filling (This page) 'M. Order Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs -13-This paper size applies to China National Standard (CNS) A4 (210X297 mm)