TW459354B - Semiconductor chip with surface mounting components - Google Patents

Abstract

The present invention discloses a semiconductor chip with surface mounting components which is characterized by directly mounting the surface mounting components on the front surface of the semiconductor chip. The semiconductor chip comprises a plurality of metal pads on the front surface and the front surface of the semiconductor chip is configured with a plurality of circuits to be connected to the surface mounting components. Each circuit has a first end and a second end in which the first end is connected to one of the plurality of metal pads. The surface mounting components comprises two contact ends across the second ends of two of the plurality of circuits. Because the surface mounting components are directly mounted on the circuits on the front surface of the semiconductor chip, the surface mounting components can be configured as near as possible to the power supply or the ground of the semiconductor chip and without greatly increasing manufacturing cost.

Description

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A semiconductor wafer with components attached to the front of the semiconductor wafer. V. Description of the invention u) [Field of the invention] The present invention relates to a method which is characterized by directly displaying a table. [Prior art] Electronic package structures generally include a substrate. The active device is generally a crystal active device (made of a circuit). A chip package obtained by cutting = a single crystal moon package (SCM) with silicon, germanium arsenide, or gallium arsenide on the top. Containing only one component is called a multi-chip package (MCM). The packaging structure of three components is called as the electronic packaging structure is fascinated. The noise of the ground line will gradually become A = from the DC power line and often used passive components such as capacitors. S ~~ c — "... to reduce the power supply capacitance (d- ^ ,, '^' ^ 3il (power supply noise) (which = generated by the change in potential difference between the power supply voltage and the ground voltage). It may be placed close to the active component to increase its effectiveness. Generally speaking, the decoupling capacitor is connected to the power or ground as close to the active ~ as possible. The known depletion capacitor is generally a surface Next, the components are fixed on the substrate using surface-mount technology (SMT) at both ends (j contact). However, placing these capacitors directly on the substrate will greatly reduce their performance 'and it will Reduce the effective use area of the substrate and reduce the packaging efficiency. Some substrates have capacitors buried directly in them, but they also cannot significantly improve their% performance. Therefore, some wafers have capacitors built into each chip structure, thereby greatly improving Electrical performance. However, if the capacitor is to be directly

POG-m.ptd Page 4 459354 V. Description of the Invention (2)-Built in the wafer structure will complicate the wafer process and increase the cost. Therefore, it is necessary to find a method for directly mounting surface-mount components on the front side of a semiconductor wafer, so as to overcome or improve the aforementioned problems of the prior art. [Summary of the Invention] The main object of the present invention is to provide a semiconductor wafer having a surface bonding element, which is characterized in that the surface bonding element is directly mounted on the front surface of the semiconductor wafer, whereby the surface bonding element can be placed as close to the power or ground of the semiconductor wafer as possible. Without significantly increasing its manufacturing costs. Another object of the present invention is to provide a process for directly mounting a surface bonding element on a front surface of a semiconductor wafer, whereby the surface bonding element can be directly disposed on the front side of each wafer in the wafer without complicating the wafer process. , Which can control its manufacturing costs. The specific crystal of the preferred embodiment has multiple connections to the plurality of contacts across the surface and then the component and the surface are then arranged without substantially connecting the surface. 'It includes: U) The film according to the present invention, wherein the semiconductor And the semiconductor wafer is provided with a face-to-face component on the front side. Each of the lines has a first end tethered component having two ends and two ends. As the line on this side, the borrowed power supply or grounding device is provided in the manufacturing process of the present invention. Several metal pads are provided here, and the line is used to connect to the first end and the first. One of the two metal pads at the two ends. The surface ^ two of the plurality of lines j are directly mounted on the semiconductor wafer ^, may: as close as possible to the semiconductor crystal) increase its manufacturing cost. The component is mounted on the semiconductor wafer to form a metal layer on the semiconductor.

POO-lll.ptd Page 5 459354 V. Description of the invention (3) Front side of the wafer; (b) Selectively etching each line to have a first layer of a ° Λ ^ • layer to form a plurality of line end connections. To the semiconductor terminal at two degrees and the second end portion, (c) the conductive adhesive is placed on one of the plurality of metal pads; then the component is placed on the second end portion of the semiconductor line; (D) the surface contact) and the Li Zhao: round front side, so that the two ends (end and (e) of the cured strip line) are aligned with the second end of two of the conductive strip lines; Connection, f this table: the f element is fixed to the semiconductor, and the present invention provides = surface bonding element to the semiconductor wafer. / A process of mounting the surface bonding element on the semiconductor b b (waf er), Α Α 丁 守 瓶 a Yen g hi contains: (a) forming a metal layer on the front side of the wafer M; (b) logic lithium w 0 33: A 4 cattle conductor ^ Λ, selective silk engraving the metal layer and Form a complex U @ # The mother has a line with 篦 — 山 ^ ^, ^ X poles, > Λ Αϊή and the first M), should be φ flute (C) One of the plurality of metal pads on the front side of the eight-band Japanese yen, 70% of the "electrical layer" covers the front side of the semiconductor wafer to form a sheet, so that at least a part of the second end of each of the lines has a bare ^ ^ line; ^ d) coating the bonding substance on each of the circuits second: Zou]: ^ meaning; (e) placing a surface bonding element on the semiconductor σ 卩 ^ Lugan τ called BEa circle front, insert; θ ' 2. The two end contacts (endc ο ntact) are respectively aligned with the second end of the plurality of strips; and (f) the solder joint is re-soldered. ^ Both sides are fixed to the semiconductor wafer and electrically connected. The main ° Λ table J ^ L ^ * A surface is connected to the semiconductor wafer. l In order to make the above and other objects, features, and features of the present invention obvious, the following describes the preferred embodiment of the present invention, and the point of entry is made clearer. ^ 4 1 attached drawings, 1 review details described as follows.

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_ Case number 89117704 V. Description of the invention (4) [Explanation of the invention] The first figure discloses a semiconductor wafer 110 having a surface bonding element 100 according to a preferred embodiment of the present invention. As shown in the figure, the semiconductor wafer i i 〇 has a plurality of metal contacts 110 a provided on the front surface thereof. Generally speaking, the semiconductor wafer 110 includes a passivating layer 11〇b covering the top edge of the metal pad 11 Oa, leaving only the middle surface portion exposed on the protecting layer 11 Ob (see the third ®. The protective layer 110b may be a polyimide layer, a silicon dioxide layer, a silicon nitride layer, or other protective materials known in the industry. As shown in the first figure, the semiconductor The front surface of the chip 110 is provided with a plurality of lines 1 and 2 for connecting to the surface bonding element 100. Each of the lines 112 has a first end portion n2a and a second end portion 112b, where the first end portion 112a is connected to One of the plurality of metal pads i0a. The surface bonding element 100 generally includes two end contacts. The surface bonding element 100 according to the present invention is preferably a passive solution, The passive component can include a capacitor, a resistor, and a two-wave filter (fU ter) to suppress the noise supply of the t source and improve the operation speed of the chip. The surface bonding device 100 uses surface bonding technology (SMT). The contacts at both ends are fixed at Plural lines 丨 2 It has two second ends 4 112b. Since the surface bonding component is directly mounted on the front surface of the semiconductor wafer, the surface bonding component can be as close as possible to the power pad of the semiconductor wafer. Or the ground pad is provided without greatly increasing its manufacturing cost. The present invention further provides a process for mounting surface-attached components on a semiconductor wafer, wherein the semiconductor wafer has not been cut into individual crystals.

Page 7 459354 V. Description of Invention (5). The process includes: (a) sputter depositing a metal layer (such as an aluminum layer or a copper layer) on a protective layer on the front surface of a semiconductor wafer (including a portion of the metal pad exposed on the protective layer); (b) coating Photoresist and formation of a pattern structure (P a 11 erning) '(c) The metal layer exposed on the light group is carved to form a plurality of lines 1 1 2 (see the second and third figures), each of which has a first One end portion 1 1 2a and second end portion 1 1 2b, wherein the first end portion 11 2a is connected to one of the plurality of metal pads 11 Oa provided on the front surface of the semiconductor wafer; (j) removing the remaining light (㊀) point conductive pads (such as silver glue) at the second end 1 1 2 b of the plurality of lines n 2; (f) stick the surface to the component 100 = ί the front side of the body wafer , So that the contacts at its two ends are aligned with the complex number = the second end, respectively; and (g) 嶋 is electrically conductive, and preferably 二 is first mediated by a two-circle / understandable that the process is in step mask) or Interfering with w ^ s (for example, photo-imageable solder resist (so 1 der material: ==== bulk wafer front surface with Y-number dielectric layer imaging only in specific areas, and at 2:- The mask is used so that the agent will be removed, so that the freshness of the specific area is exposed to the dielectric layer after each step. At least part of the second end of the 4-way / metal layer preferably further includes— A layer of nickel-gold covers the nickel [understandably 2 or the copper layer and-layer: iron is deposited on the copper or copper layer, but the layer may be on the N layer in step ⑷. In addition, the nickel / gold layer It can also be deposited in the nickel

Nl / Au) method is deposited on the aluminum or copper layer that has been formed in the figure “Electrorless * structure” 4 5 9 35 4 V. Description of the invention (6) (patterned aluminum or copper layer). The present invention further provides a process for mounting a surface-adhesive element on a semiconductor wafer. The steps (a) to (d) are substantially as described above, and further include step (E) forming a dielectric layer to cover the The front side of the semiconductor wafer and the plurality of lines Π 2 such that the second end portion 11 2 b of each line is at least partially exposed to the dielectric layer; step (F) electrically bonds the bonding material. # (E 1 ectr 〇de ρ 〇siti ο η) or printed on the area where the second end of each line 1 1 2b is exposed on the dielectric layer (the bonding substance may be a conductive solder alloy containing tin, lead, bismuth, indium, and silver. (Eutectic solder); step (G) aligning the surface bonding component on the front side of the semiconductor wafer; and step (i) re-soldering the bonding material, thereby bonding the surface to the component Fixed to the semiconductor wafer and electrically connected to the surface bonding component Semiconductor wafer. According to the present invention, a semiconductor wafer with surface-connected components is characterized in that the surface-attached component is directly mounted on the front surface of the semiconductor wafer, whereby the # surface-attached component can be placed as close to the power or ground of the semiconductor wafer as possible without large Increasing its manufacturing cost. In addition, compared with the conventional technology of mounting surface-adhesive components on a substrate, the present invention directly mounts surface-adhesive components on a semiconductor wafer, thereby increasing the effective area of the substrate and improving packaging efficiency. The invention has been disclosed in the foregoing preferred embodiments, but it is not intended to limit the invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the invention is protected. The scope shall be determined by the scope of the attached patent application.

POO-111-ptd Page 9 ^ 4,5¾35 4 _Ά 89117704_ Year Month Revision _ Simple Description [Illustration] Figure 1: Semiconductor wafer with surface-bonding element according to a preferred embodiment of the present invention Top view; and FIG. 2: It is a view for explaining a method for manufacturing a semiconductor wafer having a surface-attached element according to FIG. 1 of the present invention; and FIG. 3: An enlarged partial cross-sectional view taken along line 2-2 of FIG. 2 . [Illustration of drawing number] 100 surface-attached component 110 semiconductor wafer 110a metal pad 110b protective layer 112 circuit 112a first end 112b second end

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Claims (1)

d 5 9 35 4 VI. Application for Patent Scope 1. A process for mounting surface-attachment components on a semiconductor wafer (wafer). The semiconductor wafer has a plurality of metal contact pads on the front side. The manufacturing process includes: forming a metal layer on the front surface of the semiconductor wafer; selectively etching the metal layer to form a plurality of traces, each of which has a first end portion and a second end portion, wherein the first end portion is Connected to one of the plurality of metal pads; placing a conductive adhesive on the second end of the plurality of lines; placing a surface-adhesive component on the front surface of the semiconductor wafer such that the ends of the two ends are connected (e nd c ο ntact) are respectively aligned with the second ends of two of the plurality of lines; and curing the conductive adhesive to fix the surface contact element to the semiconductor wafer and electrically connect the surface and the element to the semiconductor wafer. 2. According to the process of mounting a surface-adhesive component on a semiconductor wafer according to item 1 of the scope of the patent application, the surface-adhesive component is a passive component. 3. According to the process of mounting a surface-attached component on a semiconductor wafer according to item 2 of the scope of patent application, the passive component is a capacitor. 4. According to the process of mounting a surface-attached component on a semiconductor wafer according to item 2 of the scope of the patent application, the passive component is a resistor. 5. Mount surface-mount components on semiconductors according to item 2 of the scope of patent application POO-llLptd Page 11 459354 6. Scope of Patent Application Wafer manufacturing process, in which the passive component is an inductor. 6. The process of mounting surface-adhesive components on a semiconductor wafer according to item 1 of the scope of the patent application, wherein the metal layer includes a layer of aluminum or copper, a layer of nickel covering the layer of aluminum or copper, and a layer of gold covering the nickel layer . 7. According to the process of mounting a surface-attached component on a semiconductor wafer according to item 1 of the scope of patent application, before the conductive adhesive is dispensed, it further includes forming a dielectric layer to cover the front surface of the semiconductor wafer and a plurality of lines, so that The second end of each line is at least partially exposed from the dielectric layer. 8. A process for mounting a surface-attachment component on a semiconductor wafer, the semiconductor wafer having a plurality of metal pads disposed on a front surface thereof, the process comprising: forming a metal layer on the front surface of the semiconductor wafer; The metal layer is selectively etched to form a plurality of traces, each of which has a first end portion and a second end portion, wherein the first end portion is connected to one of the plurality of metal pads; forming a The dielectric layer covers the front side of the semiconductor wafer and the plurality of lines, so that the second end portion of each line is at least partially exposed to the dielectric layer; the bonding substance is applied to the exposed portion of the second end portion of each line. Part; placing a surface bonding component on the front side of the semiconductor wafer such that the contacts at both ends thereof are respectively aligned with the second end portions of two of the plurality of lines; and re-soldering the bonding substance, thereby bonding the surface Component fixed to semiconductor POO-111.ptd Page 12 45 9 354, * * VI. Patent Application Scope Wafer and electrically connect the surface and the component to the semiconductor wafer. 9. The process of mounting a surface-adhesive component on a semiconductor wafer according to item 8 of the scope of patent application, wherein the surface-adhesive component is a passive component. 10. The process of mounting a surface-attached component on a semiconductor wafer according to item 9 of the scope of patent application, wherein the passive component is a capacitor. 11. The process of mounting surface-attached components on semiconductor wafers according to item 9 of the scope of patent application, wherein the passive component is a resistor. 1 2. According to the process of mounting a surface-attached component on a semiconductor wafer according to item 9 of the scope of the patent application, the passive component is an inductor. 1 3. According to the process of applying a surface-attached component to a semiconductor wafer according to item 8 of the scope of the patent application, the bonding substance is solder. 14. The process of mounting surface-attached components on a semiconductor wafer according to item 8 of the scope of the patent application, wherein the metal layer comprises a layer of aluminum or copper, a layer of nickel covering the layer of aluminum or copper, and a layer of gold covering the nickel Floor. 15. A semiconductor wafer having a surface bonding element, the semiconductor wafer having a plurality of metal pads disposed on a front surface thereof, the front surface of the semiconductor wafer being provided with a plurality of lines, each line having a first end portion and a second end portion POO-lU.ptd Page 13 VI. Patent Application Scope Department, where the first end is connected to one of the plurality of metal pads, and the surface bonding element has two end contacts across the plurality of lines. t two second ends. 16. A semiconductor wafer having a surface-attached component according to item 15 of the scope of patent application, wherein the surface-attached component is a passive component. 17. A semiconductor wafer having a surface-attached component according to item 16 of the scope of patent application, wherein the passive component is a capacitor. 18. A semiconductor wafer having a surface-attached element according to item 16 of the scope of patent application, wherein the passive element is a resistor. 19.Semiconductor with surface-attached element according to item 16 of the scope of patent application POO-lll.ptd Page 14