TW459351B - CMOS semiconductor devices and method of formation - Google Patents

Abstract

In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.

Description

459351 _Case No. 88110328 Year / Month $ Amendment_ V. Description of the Invention (1) Reference materials of previous applications in the United States This application was registered as the 0th in the patent application on June 30, 1998 9/1 0 7, 9 6 3. Scope of the invention The present invention relates to semiconductor devices, and more particularly to complementary metal oxide semiconductor devices and methods of forming the same. BACKGROUND OF THE INVENTION In the context of high-performance semiconductors, there is a trend toward using metal gates to overcome the problem of polysilicon depletion. The semi-conductive nature of polycrystalline silicon gates causes curved bands or potential wells in the gates. The carrier is limited to a size equivalent to its wavelength. The corresponding charge distribution in the polycrystalline silicon layer causes the finite deviation dependence of the gate capacitance (CP), and the polycrystalline silicon depletion effect occurs. When the gate oxide becomes thinner, the complementary metal oxide semiconductor (CMOS) technology is used at the same time to increase the gate oxide capacitance (CQX) so that CQX is equivalent to a polycrystalline silicon gate close to the device's threshold voltage gate deviation capacitance. This results in an unnecessary overall reduction in the overall gate capacitance (c G). When operating in an operation reversal mode, the effect of the semiconductor device is even more severe, and if the carrier density of the polysilicon gate is less than 102 ° / cm3, the overall skin capacitance may be reduced by about 30%. Excessive dopants (such as dopants for P + electrodes) may increase CP and cause unstable threshold voltage (Vt). It is known to use a metal gate to eliminate the depletion effect of polycrystalline silicon. It is also known that polycrystalline silicon gates have a high resistivity, resulting in the need to silicide the gate to reduce the overall resistivity. In some design environments, it is not possible or necessary to silicide all gates (such as SRAMs where not all parts are silicided because of the need for a metal interconnect layer). The polysilicon gate has a high resistivity of

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459 351 __Case No. 88110328 V. Description of the invention One disadvantage of the FDSOI technology. In addition, when the optimum Vt is reached using an insulator polycrystalline silicon gate, the actual SOI thickness and high permittivity (high k value) metal cannot be used. In addition, polysilicon gates are often used more than 3.9.) Inconsistent uses of oxide gate dielectrics (where high k = the metal oxide reacts to cause contamination when there is silicon from the polysilicon). Therefore, it affects the high-k value of specially dyed metal oxide gate dielectrics. Shishi and P + polycrystalline silicon are used in CMOS technology, respectively. And PM0S device gate. W ,: operating function. Current device size crystalline silicon 4 · 1 eV and P + polycrystalline silicon 5. 2 e hybrid agent to avoid short-frequency path effect. Needs more than 1E17 / cubic centimeter of broken frequency metal operation function. . Xiguo. Instead of the double-doped silicon gate, "/ this has allowed the NM0s and" 〇3 known methods have chosen this metal, so six 'ten, ft ^ ^ ^ ^ ^ device symmetrical vtS _ Equal-gap operation function. ^ ^ M 4111 The need to avoid short-frequency effects causes the equal-gap golden eyebrows in Vts to be quite large for low-voltage, low-power, high-performance devices. Therefore, it is necessary to have Both PMOS devices provide a method for low Vts. One object of the present invention is to Provides a low threshold voltage (V ts) that can be applied to NMOS and PMOS devices. The present invention includes a structure and a method. The structure of the present invention is a semiconductor device having a semiconductor substrate, a first gate and a first gate. The function values of the two and one regions and the first region. The compound layer and the interrogation electrode. The first gold second gate package of the semi-second conductivity type is characterized by a conductive substrate and a second region which is a nitride. The layer includes a first conduction region and a first conduction region. The first gate is characterized by an energy value in two regions. One of the second electrical types has a first pole covered with a first second metal nitrogen function value less than

4 59 35 1 _Case No. 88110328 eve φ year / month 9 __ V. Description of the invention (3) First function value. The method of the present invention obtains a semiconductor device by performing the following steps. A semiconductor substrate is provided having a first region of a first conductivity type and a second region of a second conductivity type. A conductive layer covering the semiconductor substrate is formed, which has a first portion covering one of the first regions and a second portion covering one of the second regions. A first portion of the conductive layer is nitrided to form a conductive nitride layer on the first region. The conductive nitride layer is patterned to form a first gate electrode on the first region. The conductive layer is patterned to form a second gate electrode on the second region. The method and structure of the present invention can be applied to NMOS and PMOS to achieve a low threshold voltage (Vts). Figures Legends--Figures to to Jane 18 8-sided drawing. Figure cut-out view cut-out step-by-step parts of the body guide semi-finished hair form to use the display of the step of the TMMJ entity to display other parts of the hair form to show the sign symbol 3 yuan 5 W 5 8 2 4 A 11 1—- ΟΛ- 06 copies of Rukou ’s layered structure, electrical placement, dielectric field, polar region, gate gate, gate gate Layered boundary edge ionization zone insulation layer Nitrogen II Second-field conductive plant electricity Conductive semiconducting conductor O: \ 59 \ 59047.ptc Page 8 2001.01.09. 008 459 35 Correction layer layer object body isolation Intercrystalline and interlayer and surface nitrogen electric cover wall electrode two electric one two cover side source guide No. 6 8 0 0 2 8 0 2 2 3 4 4 4 5 Case No. 88110328 V. Description of the invention (4) 25 Second gate 27 First transistor 29 Second transistor 34 Source-drain region 4 1 Nitrogen ion 4 7 Gate 4 9 Interrogation of the preferred embodiment Detailed description of the semiconductor device shown in FIG. 1 is one of the specific examples of the present invention Structure part 1 0. The semiconductor device structure includes a first region 3 having a first conductivity type, a second region 5 having a second conductivity type, an electric field insulation region 12, a first gate dielectric layer 14 and a second gate dielectric layer 16. Semiconductor substrate. In a specific example, the semiconductor substrate is a single crystal silicon substrate. Alternatively, the semiconductor substrate may be a silicon-on-insulator substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-sapphire substrate, and the like. In a specific example, the electric field insulation region 12 is a trench insulation region formed using conventional etching and chemical mechanical polishing techniques. Alternatively, the electric field insulating region 12 may be an electric field oxide region, which is formed using conventional techniques, such as local silicon oxidation (LOCOS), poly-buffered LOCOS (PBL), polycrystalline silicon sealed local oxidation (PELOX), and the like. In a specific example, the gate dielectric layer 14 and the gate dielectric layer 16 are thermal silicon dioxide layers, which are formed by thermally oxidizing a portion of the first region 3 and the second region 5 respectively. The electrical layer 14 and the gate dielectric layer 16 may be a layer of silicon nitride, a layer of silicon oxynitride, a layer of chemical vapor deposition, a nitride oxide layer, a high-k dielectric material, such as a kind of

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......-..--. __ ·--..... II V. Description of the Invention (5) Metal oxide or its composition. It must be understood that the gate dielectric layer 14 and the gate dielectric layer 16 may be formed at the same time. Alternatively, the gate dielectric layer 14 and the gate dielectric layer 16 may not be formed at the same time and with different gate dielectric materials. In FIG. 2, the first region 3 and the second region 5 are covered to form a conductive layer 18. In one specific example, the conductive layer 18 is a metal layer * such as tantalum, tungsten, molybdenum, hafnium, indium, vanadium, chromium, niobium, titanium, and the like. Alternatively, the conductive layer 18 may be a metal silicide layer, such as a silicide button, tungsten silicide, molybdenum silicide, titanium silicide, and the like. The conductive layer 18 may be formed using conventional chemical vapor deposition techniques or sputtering techniques. In FIG. 3, a mask layer 20 is formed by covering the conductive layer 18. In one specific example, the mask layer 20 is a silicon nitride layer deposited using rapid thermochemical vapor deposition. Alternatively, the masking layer 20 may be a photoresist layer or a polycrystalline silicon layer. In FIG. 4, a wiring pattern is formed for the mask layer 20 to expose the first portion of the conductive layer 18 and leave a portion of the mask layer 20 covering the second portion of the conductive layer 18. The exposed portion of the conductive layer 18 is then nitrided to form a conductive nitride layer 24 covering the first region 3. In one specific example, nitrogen ions 2 2 are implanted in the exposed portion of the conductive layer 18 to form a conductive nitride layer 24. It must be understood that the remaining portion of the masking layer 20 prevents nitrogen ions from implanting into the second portion of the conductive layer 18. After implanting nitrogen, the semiconductor device structure is annealed to form a conductive nitride layer 24. The semiconductor device structure may be annealed using a conventional furnace or a rapid thermal annealing system. It must be understood that if a photoresist is used to form the mask layer 20, it must be removed before annealing. Alternatively, the exposed portion of the conductive layer 18 may be annealed in a nitrogen environment (such as ammonia) or the exposed portion of the conductive layer 18 may be exposed to a plasma including nitrogen to form the conductive nitride layer 24. Note that if the conductive layer 18 series button, tungsten, molybdenum,

O: \ 59 \ 59047.ptc Page 10 459351 _ Case No. 88110328 Decade / Month 7__ V. Description of the invention (6) Zirconium, hafnium, vanadium, chromium, niobium or titanium layer, then the conductive nitride layer 2 4 are respectively nitrided nitride, gasified tungsten, nitrided turn, gasification fault, nitrided to, gasification information, chromium nitride, niobium nitride or titanium nitride layer. Similarly, if the conductive layer 18 is a silicon silicide button, tungsten silicide, molybdenum silicide, or titanium silicide, the conductive nitride layers 24 are tantalum silicon nitride, tungsten silicon nitride, molybdenum silicon nitride, or titanium silicon nitride. In 圊 5, a cover layer 26 is formed on the conductive nitride layer 24 and the remaining portion of the conductive layer 18. In one specific example, the capping layer 26 is a silicon nitride layer deposited using rapid thermochemical vapor deposition. Alternatively, the capping layer 26 may be a polycrystalline silicon layer that is also deposited using rapid thermochemical deposition. Note that if polycrystalline silicon is used to form the cover layer 26, a barrier layer (such as titanium nitride) can be formed between the polycrystalline silicon and the underlying conductive nitride layer 24 and the conductive layer 18 to avoid the polycrystalline silicon layer and the underlying conductive metal. Silicide between the layer 18 and the conductive nitride layer 24. It is also necessary to understand the use of the cover layer 26 to avoid oxidation of the conductive nitride layer 24 and the remaining portions of the conductive layer 18 during subsequent processing. In FIG. 6, a wiring pattern is formed for the conductive nitride layer 24 to form the first gate electrode 2 3 covering the first region 3, and a wiring pattern is formed for the remaining portion of the conductive layer 18 to form the second region 5. Of the second gate electrode 2 5. As shown in FIG. 6, a part of the covering layer 26 is left to cover the first gate electrode 23 and the second gate electrode 25 is left. Care must be taken to form wiring patterns for the remaining portions of conductive nitride layer 24 and conductive layer 18 using conventional etching techniques at the same time or in separate steps. In FIG. 7, sidewall spacers 28 are formed along the sidewalls of the first gate electrode 23 and the second gate electrode 25. In one of the specific examples, the sidewall spacer 28 is a silicon nitride sidewall spacer, which is formed using a rapid thermochemical vapor deposition and a conventional etching technique. It must be understood that the side wall spacers 28 prevent the first and second gates 23 and 25 from being oxidized during subsequent processing steps. In addition, in the first zone 3

O: \ 59 \ 59047.ptc Page U 4 59 35 1 Amendment No. 88110328 5. In the description of the invention (7), a source drain region 3 0 having a second conductivity type is formed, and in the second region 5 is formed The source-drain region 34 of the first conductivity type forms a first transistor 27 in the first region 30 and a second transistor 29 in the first region 5. It must be understood that gate 23 has a different operating function than gate 25. For example, if the first region 3 has an N-type conductivity and the second region 5 has a P-type conductivity, the operation function of the gate electrode 23 will be greater than that of the gate electrode 25. Fig. 8 shows another embodiment of the present invention, in which the masking layer 20 shown in Fig. 4 is removed after the conductive nitride layer 24 is formed. Then, a second mask layer 40 is formed on the conductive nitride layer 24 to expose the remaining portion of the conductive layer 18. In one specific example, the mask layer 40 is a silicon nitride layer deposited using rapid thermochemical vapor deposition. Alternatively, the masking layer 40 may be a layer of photoresist or a layer of polycrystalline silicon. After the mask layer 40 is formed, the remaining portion of the conductive layer 18 is then nitrided to form a conductive nitride layer 42. In one specific example, a nitrogen ion 41 is implanted into the remaining portion of the conductive layer 18, and then the semiconductor structure 15 is annealed to form a conductive nitride layer 42. Alternatively, the conductive nitride layer 42 may be formed by annealing in a nitrogen environment such as ammonia, or exposing the remaining portion of the conductive layer 18 to a plasma including nitrogen. Note that if the conductive layer 18 is a layer of tungsten, tungsten, molybdenum, tungsten, hafnium, vanadium, chromium, niobium, or titanium, the conductive nitride layer 42 is a nitride nitride, a SL chemical, a nitride nitride, or a nitride nitride. Wrong, gasified, nitrided, chromium nitride, niobium nitride or titanium nitride layer. Similarly, the rhenium conductive layer 18 is a silicon silicide button, tungsten silicide, molybdenum silicide, or titanium silicide, and the conductive nitride layer 42 is tantalum silicon nitride, tungsten silicon nitride, molybdenum silicon nitride, or titanium silicon nitride. In Fig. 9, the mask layer 40 is removed and processing is continued as described previously in Figs. 5-8. This forms a first transistor 48 covering the first region 3 and a second transistor 50 covering the second region 5. It must be noted that the gate 47 of the transistor 48 includes a part of the

O: \ 59 \ 59047.ptc Page 12 4 5 9 35 Case No. 88110328 Amendment V. Description of the invention (8) The electro-nitride layer 2 4 and the electrode 49 include a part of the conductivity value. For example, crystal 48 may be formed and have a second P-type conductivity coefficient, and the first operation function of the transistor 50 tantalum nitride gate will be a conductive nitrogen electrode with different nitrogen concentrations. In particular, because the concentration of one nitrogen is small, the foregoing condensed description is inclusive of this, and it has been disclosed to use a capable CMOS device structure. Therefore, it is clear that CMOS devices have advantages. The present invention, but the present invention will be understood and changed by those skilled in the art. Therefore, the changes and improvements in this issue. Gate of body 50 0 Operation function Gate electrode of crystal 50. The second region 5 has a large functional gate nitride gate to form a gas gate having a gate gate nitride. point. The special device has a first operating function value, the transistor nitride layer 42, and the electric region 3 having a second operating function value tantalum nitride operating function value tantalum nitride gate electrode has an N-type conductivity, The functional value of the gate operating electrode of the nitride group of the transistor No. 48. Note that the conductivity is increased. Therefore, a non-chemical equivalent metal-rich metal conductive operation function with a lower operating function than a chemical equivalent conductive layer can be formed by forming a compound layer to illustrate the advantages of the present invention. Although the foregoing requirements have been described and illustrated with reference to specific specific examples, they are not limited to these exemplary specific examples. Modifications can be made without departing from the spirit of the invention, including all such patent applications in the appendix.

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Claims (1)

459351 _ Case No. 88110328 ^. Year / Month 7 _ίΜ: _ VI. Patent Application Scope1. A method for forming a semiconductor element, which includes the following steps: preparing a semiconductor substrate having a first region of a first conductivity type and a first region and A second region of a second conductivity type; forming a conductive layer covering the semiconductor substrate, the conductive layer having a first portion covering the first region and a second portion covering the second region; A portion to form a nitride layer covering the first region; patterning the conductive layer to form a first gate electrode covering the first region; and patterning the conductive layer to form a second gate covering the second region pole. 2. The method according to item 1 of the patent application scope, wherein the conductive nitride layer is further characterized by a metal-rich nitride layer. 3. The method according to item 1 of the patent application scope, wherein the conductive nitride layer is further characterized by a chemically equivalent nitride layer. 4. The method according to item 1 of the patent application, wherein a wiring pattern is formed on the conductive nitride layer and the conductive layer at the same time. 5. The method according to item 1 of the patent application, wherein the conductive layer is further characterized by a la layer. 6. A semiconductor element comprising: a semiconductor substrate having a first region of a first conductivity type and a second region of a second conductivity type; a first gate electrode including a first region A first metal nitride layer, the first gate having a first operating function value, and a second gate including a second metal nitride covering the first region O: \ 59 \ 59047.ptc Page 15 459 35 1 Amendment No. 88110328 6. The scope of the patent application, the second gate has a second operating function value, wherein the second operating function value is less than the first operating function value. 7. The semiconductor device according to item 6 of the application, wherein the first metal nitride layer is further characterized by a first nitrogen concentration. 8. The semiconductor device according to item 7 of the application, wherein the second metal nitride layer is further characterized by a second nitrogen concentration, which is less than the first nitrogen concentration. 9. The semiconductor device as claimed in claim 6 in which the first metal nitride layer is further characterized by a first tantalum nitride layer. 1 ◦ The semiconductor device according to item 9 of the patent application scope, wherein the second metal nitride layer is further characterized by a second tantalum nitride layer. O: \ 59 \ 59047.ptc Page 16