TW455987B - Deep trench structure with large surface area and its manufacturing method - Google Patents

Abstract

A kind of method for manufacturing a deep trench is suitable for use in a substrate having a pad layer structure and, additionally, a trench deep into the substrate is formed at a certain position. At first, the first insulating layer is formed to cover the pad layer structure and fill up the trench. Then, the first insulating layer is etched to a certain depth of the trench in order to make the bottom insulating-layer remain inside the trench. On top of the bottom insulating-layer, a pad oxide layer is grown on the sidewall of the substrate. After that, the second insulating layer is formed so as to conformably cover the pad oxide layer, the pad layer structure and the bottom insulating-layer surface. The second insulating layer is etched in order to form a collar insulating layer in the pad layer structure inside the trench and the pad oxide layer sidewall. The bottom insulating-layer is removed, and an etching process is performed onto the sidewall of substrate inside the trench in order to make sidewall surface inside the trench rugged such that surface area of the trench sidewall is increased.

Description

455987 V. Description of the Invention (1) The present invention relates to a semiconductor integrated circuit manufacturing process, and particularly relates to a deep trench structure having a large surface area and a manufacturing method thereof. In recent years, with the increase of the integration degree of integrated circuits, the design of semiconductor processes has also developed toward reducing the size of semiconductor components to improve the density. Currently, widely used dynamic random access memory (DRAM: dynamic; random access memory) As an example, the 64M DRAM process has been switched from 0.35um to below 0.3m, while 128M DRAM or 256M DRAM is moving towards 0.2um, or even below 0.15um. The capacitor is basically composed of two conductive layer surfaces (ie, electrode plates) separated by an insulating substance, and the ability of the capacitor to store charge is determined by three physical characteristics, namely (1) the thickness of the insulating substance: (2) the electrode plate Surface area; and (3) the electrical properties of the insulating substance. In order for the memory circuit to contain a large number of memory cells, the base area of the memory cells must be continuously reduced to increase the density. At the same time, the electrode plate portion of the memory cell capacitor must still have sufficient surface area to store sufficient charge. Generally speaking, high-density memory systems have two different capacitor formation technologies, one of which is a three-dimension stacked capacitor cell (STC) and the other is a trench capacitor. For example, a crown-shaped stacked capacitor structure uses the space above the access device in a silicon wafer to form a capacitor electrode plate, and a trench capacitor is formed using a deep trench in the active regi on Capacitor storage area. The technology of the present invention is an extension of the trench capacitor technology. However, as the DRAM process continues to shrink, the diameter of deep trenches is large

455987 V. Description of the invention (2) J will also be reduced accordingly. When the aspect ratio of the trench has exceeded 1, the depth of the trench as a storage area of the valley will be limited. In addition, because the capacitance is It is proportional to the surface area of the capacitor electrode plate, and the surface area of the electrode plate of the trench capacitor is the product of the depth of the trench and the circumferential area of the trench. The trench: circumferential area is related to the aperture of the trench, in other words, when the process technology is good. When 17um is reduced to 0 · Mum, the hole diameter of the trench will become smaller, which makes it difficult for the trench capacitor to obtain a sufficient surface area to maintain the required capacitance. Furthermore, to form deep trenches with a smaller critical dimension, it is necessary to choose a method of etching with a high aspect ratio. At the same time, the smaller the critical dimension of the trench, the more difficult it is to maintain the vertical profile of the trench. The aperture system tends to become narrower as the bottom of the substrate (shown in Figure 1). This is also a challenge faced by current etching technologies. Take the traditional process as an example, 'It uses dry etching technology to directly etch the bottom of the substrate to form a deep trench'. However, because the dry etching process is limited by the surface diameter of the trench and the depth of the trench, it can only form a tapered deep trench. Bottle-shaped deep trenches that can increase the surface area of the capacitor storage area cannot be formed. At the same time, there are no examples showing that dry-etching techniques can be used to form bottle-shaped deep trenches, and the process cannot be extended to below 0.15um. In addition, a traditional bottle-shaped capacitor manufacturing process was proposed by T. Ozaki et al. (1995), where the manufacturing method of the bottle-shaped capacitor is as follows, firstly, a collar oxide layer with a thickness of about 80 nm is formed on the upper part of the trench, then

45598? V. Description of the invention (3) Capacitive processes such as the removal of the oxide mask and the native oxide layer are performed. At this time, the thickness of the ring-shaped oxide layer is reduced to about 50 nm. Then a polycrystalline silicon layer is deposited, and Phosphorus ions are doped in the same environment, and then phosphorus ions are doped into the sidewall of the capacitor portion of the trench through the thermal annealing process of the furnace tube. A ring-shaped oxide layer can prevent phosphorus ions from being doped into the trench. Chemical dry etching is used to remove the polycrystalline silicon layer. At the same time, the diameter of the trench under the ring-shaped oxide layer is also enlarged. However, the problem of the conventional technology just mentioned is that 'the etch selection ratio of the dream substrate and the doped polycrystalline silicon layer is not better than other materials such as oxide layers'. Therefore, the precision of semiconductor devices is shrinking. The degree does not meet the requirements, and the manufacturing process is relatively complicated. The purpose is to make a specific step in its manufacturing method, the bottom side wall; engraving, to increase the trench side wall by 100%. In the first embodiment, a substrate and a groove include a cushion structure. Table 1 shows a predetermined depth process. In view of this, the present invention provides a deep trench structure and a trench that penetrates into the substrate. The insulation layer is then exposed to expose the structure. The bottom of the side wall of the base substrate is roughened by etched surface, thereby increasing the surface area of the base wall of the groove. The area of the electric valley storage area is accordingly adapted according to one of the present invention to form a trench deep into the substrate with a cushion structure system— The first insulation layer covers the insulation layer engraved from the first insulation layer to the trench, and then implements thermal oxygen to solve the above-mentioned problems, and mentions that it is mainly formed first by removing the already formed bottom of the trench, and then The surface area of the bottom of the sidewall of the substrate in the groove in the groove. Therefore, in order to manufacture a deep trench in a trench capacitor structure, a predetermined position of the pad structure is as follows. First, a surface is formed and fills the trench ’and then etched to leave a bottom in the trench, a substrate above the bottom insulating layer

455987 ~ ----------------— V. Description of the invention (4) A pad oxide layer is formed on the bottom side wall; then, a second insulating layer is formed to cover the pad with $ response. The oxide layer, the pad structure and the bottom insulation layer surface are then "engaged" with a second insulation layer to form the pad structure in the trench and the side wall of the pad oxide layer-an insulating collar (c ο Π ar) Then, the bottom insulating layer is removed, and then the substrate sidewall in the trench is etched to roughen the surface of the substrate sidewall in the trench, thereby increasing the surface area of the trench sidewall. Compared with the traditional bottle-shaped deep trench, in order to increase the surface area of the trench, a step of increasing the diameter of the trench is required. However, 'the point of the present invention is that the step of increasing the diameter of the groove is not required. The present invention mainly uses an anisotropic etching solution, which has a high etching rate for the [11 〇] lattice plane and a low shoe engraving rate for the [n 丨] lattice plane. According to the present invention, an anisotropic etching and an appropriate time control 'can be used to etch a rough surface with unevenness on the side wall of the substrate in the groove. With this, the present invention can increase the surface area of the trench (side wall) by more than two-fold without increasing the diameter of the trench. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, hereinafter, a preferred embodiment is described in detail with the accompanying drawings as follows: The drawings are briefly described: 1 to 9 FIG. Is a cross-sectional view of a semiconductor structure showing an embodiment of a method for manufacturing a deep trench according to the present invention. [Symbol description] 100 ~ base; 120'120 '~ pad oxide layer; 140 ~ pad nitride layer; 160 ~ oxide layer; 160' ~ bottom oxide layer; 180 ~ nitride

Page 7 455987 V. Description of the invention (5) --- * layer; 180 '~ nitriding collars; 150 ~ substrate sidewall: 200 ~ deep groove: 2 3 0 ~ upper groove; 2 5 0 ~ Bottom of the trench; S ~ sidewall; 廿 1 ~ first depth; d2 ~ second depth. / An embodiment: First, please refer to Figs. 1 to 9 ', which shows a manufacturing process of an embodiment of the present invention. Figure 1 'shows the initial steps of the present invention. Among them, the bottom 100 is made of a semiconductor material, for example, it is composed of a silicon material (for example, silicon). For the convenience of description, a Shi Xi substrate is used as an example here. First, the initial step is to sequentially form insulating layers 120 and 140 on the surface of the substrate 100, where the insulating layers 120 and 140 form a cushion structure 11 (). For example, this step can sequentially form a pad oxide layer 'with a thickness of about 20 A and a pad nitride layer with a thickness of about 2000 A on the surface of the active region of the silicon substrate 100. For example, the material of the pad oxide layer 120 may be composed of silicon dioxide, and the beans are manufactured by a thermal, long (thermal oxide) process; the pad nitride layer 14 may be formed by depositing: chaotic material, such as SiH2Cl2 and ammonia are called reactants, and are produced by low pressure chemical vapor deposition (LPCVD) process. Its material can be used as a etching mask in the subsequent process. Secondly, referring to FIG. 2, this step is to use a lithography process and etching to define the pad structure Π 0 and the substrate 100 to form a trench 丨 30. For example, a photoresist pattern is defined before the position of the active area of the silicon substrate 100 (not shown =, followed by anisotropic dry etching, such as fluorocarbon trifluoromethaneΗ3). Plasma is the main etching reaction. Reactive ion etching

455987 5. Description of the invention (6) (RIE: reactive ion etch) sequentially etches the pad structure 11 to a predetermined depth of the substrate 100 to form a trench 130. In this embodiment / the depth of the trench to be etched Approximately 7.5 um 'The opening size of the surface of the trench 1 30 is approximately 0 2 um, and the width of the bottom of the substrate 100 in the trench 130 is approximately 0 · lum. Secondly, referring to FIG. 3 ', this step is to form an insulating layer 16o to cover the surface of the cushion structure 110 and fill the aforementioned deep trench 13o. For example, a chemical vapor deposition (CVD) process may be used to deposit an oxide layer 160 made of a material group of dioxide, having a thickness of about 2000 A, to cover the pad nitride of the hafnium layer structure 110. The surface of the layer 140 and fills the trenches 30. ° Continuation, please refer to FIG. 4. This step is to etch one of the predetermined depths of the insulating layer 160 to the trench 130 formed previously, so as to leave the bottom insulating layer 160 'in the trench 130, where the predetermined depth is away from the trench The surface of 130 is approximately in the trench 130. The area above about lum is used as the interface with the component, and the area below lum is used to make the capacitor storage area of the capacitor. For example, the etching step 16 performed on the oxide layer 16 made of silicon dioxide material is performed by selecting a type of oxide material and a nitrogen cutting material, and a J-type process with a high selection. Among them, a hydrogen buffer is selected. Liquid to carry out the wet rice engraving step, and can quickly react with the stone dioxide at room temperature = the substrate made of the material of the stone evening. Here, in terms of the hydrofluoric acid buffer solution, the etching selection ratio of silicon monoxide to silicon nitride is 20: or higher. Secondly, please refer to the figure. This step ^ forms—the oxide sound 120 ′, and then forms an insulating layer 180 to cover the surface of the insulating layer U0. For example, first implement a thermal oxidation process

Part of the insulating layer 160, and a pad oxide layer i2〇 ’is formed on the upper side wall of the substrate.

Page 9 4 5 5 9 8 7 The description of the invention (7) The degree is about 50 A. As for the insulating layer 1 80, it can be formed by depositing a silicon nitride material. For example, two gas silicon fane SiHsCI2, ammonia NHS is The main reactant is produced by a low pressure chemical vapor deposition (LPCVD) process to conformally cover the rhenium layer structure 110 and the bottom oxide layer 160 'surface' with a thickness of about 2000 A. Please refer to FIG. 6 '. The subsequent step is to perform an etching on the insulating layer 1 80 to form a pad structure 110 and a pad oxide layer 120 in the trench 130, and the side wall forms a protective collar shape. The nitride layer is 180 °. For example, the horizontal portion of the nitride layer 180 covering the surface of the pad structure 11 is removed by dry etching to leave the nitride oxide layer 180 and the pad structure 11 within the trench 130. 〇 The vertical portion of the sidewall forms a protective nitride s 180 ′. Next, please refer to FIG. 7. This step is to remove the bottom insulating layer 160 to violently produce the substrate sidewall 150 in the trench 130. For example, a hafnium nitride layer 140 and a nitride collar 180 'are used as an etch protection layer, and the aforementioned bottom oxide layer 160 formed in the trench 130 is completely removed by a wet etching process. One of them can be selected. The silicon oxide material has a high etching selectivity ratio of the hydrofluoric acid buffer to the Shixi material and the nitride stone material to perform the oxide removal step. In order, please refer to FIG. 8. This step is to use an alkaline buffer solution. The substrate sidewall 150 in the trench is anisotropically wet-etched to roughen the surface of the substrate sidewall 150 in the trench, thereby increasing the surface area of the sidewall of the trench. For example, using 2% hydroxide The potassium (KOH) solution was etched at a temperature of 70 ° C to the substrate sidewall 15 in the trench. For the [110] lattice plane, the etching rate of the above potassium hydroxide was about 500 A / mm. '♦ For the [1H] lattice plane, the above-mentioned corrosion of potassium hydroxide

Page 10 455987 V. Description of the invention (8) The etching rate is about 11 A / m i η. According to the present invention, an anisotropic etching is performed using a potassium argon halide solution, and with appropriate time control (for example, 1 minute), an uneven rough chain surface can be etched on the side wall of the substrate in the groove. If the silicon substrate is etched with potassium hydroxide for 1 minute, it is sufficient to produce an average surface roughness of about 200 A on the substrate sidewall 150. As a whole, it is equivalent to folding the surface of the substrate side wall 150 by two-fold, and the surface area of the substrate side wall 150 is also increased by 00%. Please refer to FIG. 9, which is a step of removing the insulating collar 180 and removing the hafnium oxide layer 120 ′; to form the bottom wall of the trench bottom 50. A deep trench 200 having a coarse sugar surface. For example, the wet-etching method can be used to remove the nitride collar 180 'with a hot-dish acid solution, and a part of the hafnium nitride sound 14 0 is also etched. Then, a wet etching method, such as an argon-fluoric acid buffer etching solution, is used to etch and remove the pad oxide layer 12 0 ′. However, in the subsequent process of forming a deep trench capacitor, such as: the step of implanting the same ion to form the first conductive electrode plate, and the step of depositing a conductive substance to form the first conductive electrode plate, The nitrided collars described above can be retained as part of a deep trench capacitor. The deep trench formed in accordance with the foregoing embodiment has a structure including:-a semiconductor substrate 100 formed with a deep trench 200 deep within the semiconductor substrate 100, the deep trench 200 having a first depth dl such as about 7. Sum And a trench width w that varies with the first depth dl. And a side wall s formed by the semiconductor substrate 100 around the trench 200, which is distinguished into an upper part 2 3 0 and a bottom part 2 50 from a second depth d2 such as about "ium"; where the bottom of the side wall 250 has a rough surface with unevenness, and the second depth center is smaller than the first-depth

455987 V. Description of the invention (9) Degree dl. The bottom 25 of the trench sidewall below the position of the second depth d2 has a trench width that decreases with decreasing depth. In addition, the width of the groove on the surface of the aforementioned substrate is about 0.25 μm or less, and the aspect ratio is about 15 or more. In addition, after the completion of the deep trench 2000 of the foregoing embodiment, the conventional semiconductor processes such as the fabrication of semiconductor components can be continued. For example, the bottle-shaped deep trench 200 can be used to form a trench capacitor structure. Capacitor storage area. And since the bottom 25 of the deep trench 200 of this embodiment has a roughened surface, the surface area of the side wall of the substrate surrounding the trench is increased by about 1%, so the area of the capacitor storage area of the trench capacitor structure also follows. Increase about above. Since the deep trench manufacturing method of the present invention can effectively increase the surface area, the trench capacitor structure thus formed can also meet the memory requirements of the next generation 'and even reach more than two generation processes of 0.13 um. Therefore, the capacitor structure of the present invention can be applied to dynamic random access memory (DRAM), which can greatly increase the equivalent capacitor capacity under a limited memory cell area. At the same time, the material materials used in the present invention are not limited to those cited in the examples, they can be replaced by various materials and forming methods with appropriate characteristics, and the structural space of the present invention is not limited to the dimensions cited in the examples. . "The invention has been disclosed as follows in a preferred embodiment, but it is not intended to limit it. Anyone skilled in the art," without departing from the spirit of the invention, "can do a few changes and retouching." Therefore, the protection of the invention

455987

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Claims (1)

455907 ---- Six patent application scope The method includes the following 1.- a method for increasing the surface of a deep trench, the steps are as follows: wall;. (A) a deep trench is formed in a substrate, and a side is formed in the deep trench Forming a first insulating layer, the third insulating layer filling the trench; c etching the first insulating layer to a predetermined depth of the trench and exposing. Then the upper half of the wall leaves a bottom insulating layer in the trench; (d) forming a second insulating layer to cover the surface of the bottom insulating layer with compliance; (e) engraving the second insulating layer, An insulating collar is formed in the upper half of the sidewall in the trench; (0) the bottom insulating layer is removed, and the lower half of the sidewall in the trench is exposed; (g) anisotropic etching To roughen the surface of the lower half of the sidewall in the trench, thereby increasing the surface area of the trench. 2. The method as described in item 1 of the scope of patent application, wherein, in step (b), the first The insulating layer is formed of an oxide material. 3. The method as described in item 2 of the scope of the patent application, wherein in step (c) 'the predetermined depth is used to mark the start of the deep trench to be formed. 4. Such as The method described in claim 3 of the patent scope, wherein, in step (d), the second insulating layer is formed of a nitride material. 5. The method described in claim 4 of the patent scope, wherein Step (f) is to remove the bottom insulating layer by a wet etching method. The method according to item 5, wherein, in step 455987, the scope of patent application (f) 'is to remove the bottom insulating layer by etching with a hydrofluoric acid buffer etching solution. 7. As described in item 1 of the scope of patent application The method, wherein in step U) ′, the lower half of the sidewall in the trench is etched by an anisotropic wet etching method. 8. The method according to item 7 of the scope of patent application, wherein in step (g) 'the trench D 9 is etched with an experimental buffer solution, the method according to item 8 of the scope of patent application, where' In step (g) ', a 2% component potassium hydride solution is used to etch the groove 1 groove at a temperature of 70 ° C. 10. —A manufacturing method for increasing the surface area of a deep trench, which is suitable for increasing the capacitance value of a capacitor storage area, including the following steps: (a) providing a silicon substrate with an active area; (b) sequentially in the silicon The substrate surface is formed with a first pad oxide layer and a first pad nitride layer, which are used to form a pad structure; (c) defining the pad structure and the substrate to form a trench in the active region (D) forming a second oxide layer covering the surface of the stacked layer and filling the trench; (e) etching the second oxide layer to a predetermined depth of the trench so as to be within the trench The bottom oxide layer is left; (f) performing a thermal oxidation process to form a pad oxide layer on the sidewall of the substrate above the bottom insulating layer; (g) forming a second nitride layer to cover the pad with compliance Oxide layer, hafnium layer structure and surface of the bottom oxide layer; page 15 455987 (h) etching the second nitride layer to form a collar in the trench and the side wall of the pad oxide layer; layer structure (i) wet-etching to remove the substrate in the bottom oxide layer; and exposed The substrate in the trench (j) is wet-etched, and the surface of the substrate is roughened to increase the surface / area in the trench. 11. The method as described in item 10 of the scope of the patent application, further comprising the step of sequentially removing the pad oxide layer and the collar by wet etching as follows for a deep trench having a large surface area in a capacitor storage area. The method described in item 10 of the scope of patent application, wherein the trench is etched with an alkaline buffer solution in step (] ')'. 13. The method according to item 12 of the scope of patent application, wherein in step (j) ', the groove is engraved with a 2% potassium hydroxide solution at a temperature of 70 t. 1 4 · A deep trench structure includes: a semiconductor substrate formed with a trench deep in the semiconductor substrate; the trench has a first depth and a trench width that varies with the first depth; S-sidewall The semiconductor substrate is formed around the trench, and is divided into an upper portion and a bottom portion according to a second depth. The bottom of the side wall has an uneven surface, and the second depth is smaller than the first depth. 15. The structure according to item 14 of the scope of the patent application, wherein the groove has a substrate surface with a groove width of less than 0.2 5 um ′, and the groove has an aspect ratio greater than 15. Page 16 455987 6. Scope of patent application 16. The structure described in item 14 of the scope of patent application, wherein the second / clothing degree is about 1UB1 from the surface of the substrate. 17. The structure according to item 14 of the scope of the patent application, wherein the bottom of the sidewall of the trench has a trench width that decreases with depth. 5 u m。 18. The structure described in item 丨 4 of the scope of patent application, wherein the first depth is about 7. 5 u m from the surface of the substrate. 19. A manufacturing method for increasing the surface area of a deep trench, applicable to a substrate. The method includes the following steps: (a) providing first and second insulating materials capable of being selectively etched; (b) forming a trench deep into the substrate A trench having a sidewall; (c) forming a first insulating layer composed of the first insulating oblique to fill the trench; (d) etching the first insulating layer to a predetermined depth 'to Forming—a bottom insulating layer below the predetermined depth; (e) forming a collar made of the second insulating material on the sidewall of the trench; (f) using the collar as a cover to remove the bottom insulation Layer to expose the bottom sidewall; (g) anisotropically etch the bottom sidewall to roughen the surface of the bottom sidewall, thereby increasing the surface area of the bottom sidewall. 20. The method according to claim 19, wherein the first insulating material is an oxide material, and the second insulating material is a nitride material. 2 1 · The method as described in claim 20, wherein the collar shape Page 17 455987 The method for forming a patented application includes: depositing a nitride layer using a chemical vapor deposition process and filling the trench; and using an anisotropic etching process to form a trench sidewall. A nitride collar 'exits part of the bottom insulating layer surface. 22. The method as described in claim 21, wherein before depositing the nitride layer, a method of forming a pad oxide layer is further included. 23. The method according to claim 19, wherein in step (g) ', the bottom sidewall is etched by a wet etching method. 24. The method according to item 23 of the scope of patent application, wherein in step (g) ', the bottom sidewall is etched with an alkaline buffer solution. 25. The method according to item 24 of the scope of patent application, wherein in step (g), the bottom side wall is etched with a 2% potassium hydroxide solution at a temperature of 7 (rc). Page 18