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TW455826B - Radio frequency identification tag circuit chip having printed interconnection pads - Google Patents

Radio frequency identification tag circuit chip having printed interconnection pads Download PDF

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Publication number
TW455826B
TW455826B TW88115650A TW88115650A TW455826B TW 455826 B TW455826 B TW 455826B TW 88115650 A TW88115650 A TW 88115650A TW 88115650 A TW88115650 A TW 88115650A TW 455826 B TW455826 B TW 455826B
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TW
Taiwan
Prior art keywords
radio frequency
frequency identification
material layer
patent application
item
Prior art date
Application number
TW88115650A
Other languages
Chinese (zh)
Inventor
Noel H Eberhardt
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Motorola Inc
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Publication of TW455826B publication Critical patent/TW455826B/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405Shape
    • H01L2224/24051Conformal with the semiconductor or solid-state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Details Of Aerials (AREA)
  • Burglar Alarm Systems (AREA)

Abstract

A radio frequency identification tag circuit chip (10) includes a circuit chip (11) having a surface (18) and at least one interconnection pad (12, 14) formed in the surface (18). A layer (24) of insulting material is deposited on the surface and about the at least one interconnection pad (12, 14), and a layer of conductive material (26) is deposited on the insulating material and coupling to the interconnection pad (12, 14).

Description

455826 五、發明說明(υ 發明之範圍 本發明關於射頻識別標記及射頻識別電路晶片,包括但 不限於具有印刷互連焊墊之射頻識別標記電路晶片。 發明之背景 ‘· 射頻識別標t己與射瀕識別標記象.統久已知名並有許多用 途。例如,射頻識別標記常被用於自動門入口之人員識別 用,以保護安全大樓及區域。在射頻識別標記上儲存之資 訊可識別欲進入安全大樓之人·員。一射頻識別標記系統可 方便的提供利用射頻(RF)資料發射技術在短距離,自射頻 識別標記讀出資訊。通常,使用人僅手持或將射頻識別標 記置於一基地臺,其發射一激勘信號至射頻識別標記内之 電源電路。此電路響應此激勵信號將儲存之資料與基地臺 通信,該臺接收並將資訊解碼。 通常,射頻識別標記有能力保留 > 發射實質量之資訊-足夠之資訊以獨特的識別人員,包裹,設備等。射頻識別 標記亦能接收及儲存資訊。在讀出/寫入應用中,基地台 不僅能送出激勵信號及接收自射頻識別標記之響應,並能 發出資料,或寫入信號至射頻識別標記。射頻識別標記接 收寫入之信號,其中可能含有儲存於標記中之資料。視寫 入信號之型別而定,射頻識別標記根據儲存之資料響應或 收到指令時動作。 在基地台與射頻識別標記之間耦合感應或靜電信號時, 標記必須包括含有至少一及常為二天線元件。一標記電路 晶片與天線通常為電耦合並接在_標記基體上。標記可包括455826 V. Description of the invention (υ Scope of the invention The present invention relates to radio frequency identification marks and radio frequency identification circuit chips, including but not limited to radio frequency identification mark circuit chips with printed interconnection pads. BACKGROUND OF THE INVENTION '· RFID Identification Marks The radio frequency identification mark has a long-known name and has many uses. For example, radio frequency identification marks are often used to identify people at the entrance of automatic doors to protect security buildings and areas. Information stored on radio frequency identification marks can identify intended entry. People and members of the security building. A radio frequency identification tag system can easily provide information from radio frequency identification tags at short distances using radio frequency (RF) data transmission technology. Generally, users only hold or place the radio frequency identification tag on a The base station transmits a survey signal to the power supply circuit in the RFID tag. This circuit responds to the stimulus signal to communicate the stored data with the base station, and the station receives and decodes the information. Usually, the RFID tag has the ability to retain & gt Launch quality information-sufficient information to uniquely identify people, packages, equipment, etc .; Radio frequency identification tags can also receive and store information. In read / write applications, the base station can not only send excitation signals and receive responses from radio frequency identification tags, but also send data, or write signals to radio frequency identification tags. Radio frequency The identification mark receives the written signal, which may contain the data stored in the mark. Depending on the type of the written signal, the radio frequency identification mark responds to the stored data or receives an instruction. The base station and the radio frequency identification mark When coupling inductive or electrostatic signals between them, the marker must include at least one and often two antenna elements. A marker circuit chip and antenna are usually electrically coupled and connected to the _ marker substrate. The marker may include

45 582 6 五、發明說明(2) --- 額外之組件,例如,電阻器,電容器及電或器 電耦合至標記電路晶片及/或天線。#統標記益設計提其供 T 基體上之導電軌跡’標記電路晶#,組件及天線則連接至 基體上,並電耦合至導電執跡。導線接合為一通常技術‘·以 提供在標記電路晶片-上之互連焊鸯及/或組件與導電軌跡 間之電耦合。或者,"倒"裝晶片技術在標記電路晶片(盘 電組件相似)上提供升高之導電區域(緩揸墊)。倒裝晶片 在裝配期間反轉並位於晶片上,並與緩揸墊對齊,及0電耦 合至導電軌跡。可利用導電膠合劑在緩撞墊與導電軌跡之 間,以保證良好之電耦D ,及提供標記電路晶片與基體間 之機械勝合。 二 吾人了解*在標s己電路晶片上之較大互連焊整可提供更 多面積以將標記電路晶片與導電執跡間耦合。此外,在標 記電路晶片上之較大互連焊墊可使榡記電路晶片與導電軌 跡容易對齊。但較大互連焊熱頗為昂貴。例如,利用光屏 蔽’電鍍(有電極或無電極)及相似金屬化技術以形成較大 互連焊墊,其成本可能在每—晶片晶圓$50-$150之間。等 於自晶圓分開時,每一標記電路晶片值2 - 5美分。 在許多射頻識別標記應用中’射頻識別標記之設計為― 簡單用途及可拋棄裝置。例如,電子物件監視應用中,射 頻識別標記連接並保留在每一被追蹤之用品上。成千上萬 貨品利用電子物件追蹤技術於商店中’百貨店及倉庫中。 並且有建議利用射頻識別標記技術於郵件或包裹遞送追蹤 應用上。僅美國郵政服務及每4處理超過六億件之郵件。45 582 6 V. Description of the invention (2) --- Additional components, such as resistors, capacitors and electrical or electrical devices, are electrically coupled to the marking circuit chip and / or antenna. # 统 标 益 设计 offers the conductive track on the substrate of the T′labeled circuit crystal #, and the component and the antenna are connected to the substrate and electrically coupled to the conductive track. Wire bonding is a common technique 'to provide electrical coupling between interconnect pads and / or components and conductive tracks on a marked circuit wafer. Alternatively, " inverted " chip mounting technology provides a raised conductive area (relief pad) on a marked circuit wafer (similar to a panel assembly). Flip-chips are inverted and located on the wafer during assembly, are aligned with the cushions, and are electrically coupled to the conductive tracks. A conductive adhesive can be used between the bump pad and the conductive track to ensure a good electrical coupling D, and to provide a mechanical bond between the marked circuit chip and the substrate. 2. I understand that * larger interconnect welds on standard circuit chips can provide more area to couple the labeled circuit chip to the conductive tracks. In addition, larger interconnect pads on the marker circuit wafer allow the marker circuit wafer to be easily aligned with the conductive tracks. But larger interconnect soldering heat is quite expensive. For example, the use of light-shielding 'electroplating (with or without electrodes) and similar metallization techniques to form larger interconnect pads may cost between $ 50- $ 150 per wafer. Equal to 2-5 cents per marked circuit chip when separated from the wafer. In many radio frequency identification tag applications, the radio frequency identification tag is designed for simple use and disposable devices. For example, in electronic object surveillance applications, radio frequency identification tags are attached and retained on each tracked item. Hundreds of thousands of items use electronic object tracking technology in stores ’department stores and warehouses. It has also been suggested to use RFID tagging technology for mail or parcel delivery tracking applications. The US Postal Service alone handles more than 600 million mail items every four.

第5頁 455826 五、發明說明(3) 儘管以最低估計每一射頻識別標記電路晶片,約為2美分, 利用已知電鍍技術增加互連焊墊之尺寸為成本不容許之 事。 因此,有一需求即必須有一改進之射頻識別標記電路;‘晶 片。 . -、. 圖式簡略說明 圊1為本發明較佳具體實例之一射頻識別標記電路晶片 之立體組裝之透視圖。 、 圖2為圊1中所示之射頻識別標記電路晶片之平面圖。 圖3為取自圖2之線3**3之剖面圖。 圖4為併入本發明較佳具體實=則之射頻識別標記電路晶 片之射頻識別標記之平面圖。 圖5為取自圖4之線5-5之剖面圖。 圖6為併入本發明另一較佳具體實'_'例之射頻識別標記電 路晶之射頻識別標記一部份之平面圖。 圖7為取自圖6之線7-7之剖面圖。 圖8為與圖7相似之剖面圖,說明根據本發明另一較佳具 體實例之射頻識別標記之一部份。 較佳具體實例之詳細敘述 根據本發明之較佳具體實例,及參考圖1,圖2及圖3, 一射頻識別標記電路晶片10由·一電路晶片11製成’該晶片 係以已知技術自一守晶圓所製。電路晶片1 1之形成尚包括 至少一互連焊墊,及第一互連焊墊12及第二互連焊墊14如 圖示。第一互連焊墊12及第二毛連焊墊14與表面18在同一Page 5 455826 V. Description of the Invention (3) Although the minimum estimate of each RFID circuit chip is about 2 cents, it is not cost-effective to increase the size of interconnect pads using known plating techniques. Therefore, there is a need for an improved radio frequency identification tag circuit; -,. Brief description of the drawings 圊 1 is a perspective view of the three-dimensional assembly of a radio frequency identification marking circuit chip, which is one of the preferred embodiments of the present invention. Figure 2 is a plan view of the radio frequency identification tag circuit chip shown in Figure 1. FIG. 3 is a cross-sectional view taken from line 3 ** 3 of FIG. 2. Fig. 4 is a plan view of a radio frequency identification mark incorporated in the radio frequency identification mark circuit chip of the preferred embodiment of the present invention. FIG. 5 is a cross-sectional view taken from line 5-5 of FIG. 4. FIG. FIG. 6 is a plan view of a portion of a radio frequency identification mark incorporated in a radio frequency identification mark circuit crystal of another preferred embodiment of the present invention. FIG. 7 is a cross-sectional view taken from line 7-7 of FIG. 6. FIG. FIG. 8 is a cross-sectional view similar to FIG. 7 and illustrates a part of a radio frequency identification mark according to another preferred embodiment of the present invention. Detailed description of the preferred specific examples According to the preferred specific examples of the present invention, and with reference to FIG. 1, FIG. 2 and FIG. Made from Ichimori wafer. The formation of the circuit wafer 11 further includes at least one interconnect pad, and the first interconnect pad 12 and the second interconnect pad 14 are shown in the figure. The first interconnect pad 12 and the second woolen pad 14 are on the same surface as the surface 18

4 5 5 8 2 6 五、發明說明(4) ' ; '— ----- 表面形成。吾人了解第一互連焊執 自表面18陷入或凸墊12與第二.互連焊墊14可 路曰片"内,2 致有悖本發明之範圍。電 表面22,其方向與表面2 =古及第—側表面20及第二側 '、乃门興表面18成垂直,如圖示。 κ 繼續參考圖1,圖2及囷3,一絕 18上,於第一互連焊墊12及 \枓層24沉積在表面 24與第一孔陏21及坌 χ 一互&焊墊14之四週。即層 第-L = 孔隙2 3分別圍繞第-互連焊㈣及 住;ί二此方'式,層24實質上將表面18蓋 “可形成為一獨立層在焊二14暴露出。層 印刷枯Γ 幕,油印,墊轉移或相似之 不以層24宜由選自不導電之聚合物, I宅之油墨或不導電之膠合劑等材料形成。 導層導電材料,導電材料第-層⑸及 η入孔隙21内,及耗合至第一互連谭塾】 部 :延過層24至電路晶片"之全長度。同理,層28丄 亦延:入孔隙23内1並•合至第二互連谭塾1[第二層26. =層24’以實際上延伸電路晶月^全好, 料形成層26及層28之材料應選自包括導電涵墨, 物及導電移合劑…1用營幕,油印,焊整 將=相似印刷技術印刷沉積在層24之上。精於此技藝人士 恃11解事實上任何精確之印刷技術均可利用,而不致有 4明之範圍。吾人亦了解'24之大小僅需能保證使第4 5 5 8 2 6 V. Description of the invention (4) ';'------ Surface formation. I understand that the first interconnect pad is trapped in the surface 18 or the bump 12 and the second interconnect pad 14 are within the range "2, which is contrary to the scope of the present invention. The direction of the electrical surface 22 is perpendicular to the surface 2 = the first and second side surfaces 20 and the second side ', and the Naiming surface 18, as shown in the figure. κ Continuing to refer to FIG. 1, FIG. 2, and 囷 3, a first 18, on the first interconnect pad 12 and the 枓 layer 24 are deposited on the surface 24 and the first holes 陏 21 and 坌 χ a mutual & All around. That is, the layer -L = the pores 2 and 3 surround the -interconnect solder joints respectively; in the second way, the layer 24 substantially covers the surface 18 "can be formed as a separate layer and is exposed at the solder 14" layer. The printing layer, screen, mimeograph, pad transfer or similar non-layer 24 should preferably be formed of a material selected from non-conductive polymers, inks or non-conductive adhesives. Conductive layer conductive material, first layer of conductive material ⑸ and η enter the pore 21, and consume to the first interconnect Tan 塾] Department: Extend the layer 24 to the full length of the circuit chip. Similarly, the layer 28 延 also extends: into the pore 23 1 and Combined to the second interconnect Tan 1 [the second layer 26. = layer 24 'to actually extend the circuit crystal moon ^ all good, the materials forming the layer 26 and layer 28 should be selected from the group consisting of conductive ink, material and conductive Transfer agent ... 1 using camping, mimeographing, welding and finishing = similar printing techniques to print and deposit on layer 24. Those skilled in this art will understand that virtually any precise printing technique can be used, and there is no scope of 4 I also understand that the size of '24 only needs to be guaranteed

# 7頁 4 5 582 6 五、發明說明(5) 一層2 6及第二層2 8可自電路晶片1 1絕緣即可.。 吾人應了-解某些應用上,並不需要絕緣層24,因此,在 此等應用上可以省略。至少一個絕緣層在每一較佳具體實 例均予討論。絕緣層最好能提供至少二優點。苐一,絕緣 層2 4使苐一層2 6及苐々層.2 8升高而與電路晶片1 1隔離,以 便使其間之電容耦合最小。第二點,絕緣層2 4可提供一額 外之障礙物以使第一層26或第二層28與電路晶片11短路之 機會最小。 、 第一層2 6及第二層2 8在電路晶片11上限定至少一印刷互 連;tp塾’分別與第一印刷互連焊塾及第二印刷互連焊墊對 應。此外’第一層26及第二層钟共同組成較互連焊墊12及 互連谭塾14為放大之互連焊墊在電路晶片丨丨上,供耦合至 射頻識別標記天線上◊利用本發明擬想可獲得大於2 〇 :丨增 加之互連焊墊面積《估計互連焊墊-面積之增加可在每一電 路晶片少於1美分之下獲得。 參考圖4及5’射頻識別標記1〇〇包括一基體3〇及包括在 表面34上形成之天線32。如圖所示’天線32包括含第一耦 合區38之第一天線元件,及含第二耦合區42之第二天線元 件4 0。吾人了解*天線3 2可由第—及第二接線之線圈天線 形成,而不致有悖本發明範圍。射頻識別標記電路晶片24 固定在表面34上,及位於第一耦合區38與苐二耦合區42之 間。 如圊5所示,第一層26經由導電材料層44耦合至第一耦 合區38*同理,苐二層28經由曼電材料層46耦合至第二耦# 7 页 4 5 582 6 V. Description of the invention (5) The first layer 2 6 and the second layer 2 8 can be insulated from the circuit chip 1 1. I should understand-for some applications, the insulating layer 24 is not needed, so it can be omitted in these applications. At least one insulating layer is discussed in each preferred embodiment. The insulating layer preferably provides at least two advantages. First, the insulating layer 2 4 makes the first layer 26 and the second layer .2 8 rise to isolate the circuit chip 1 1 so as to minimize the capacitive coupling therebetween. Secondly, the insulating layer 24 can provide an additional obstacle to minimize the chance of the first layer 26 or the second layer 28 being short-circuited with the circuit chip 11. The first layer 26 and the second layer 28 define at least one printed interconnection on the circuit wafer 11; tp 塾 'corresponds to the first printed interconnection pad and the second printed interconnection pad, respectively. In addition, the first layer 26 and the second layer clock together constitute an interconnect pad that is larger than the interconnect pad 12 and the interconnect Tan 14 on the circuit chip 丨 for coupling to the RFID tag antenna. The invention is intended to achieve an increase in interconnect pad area greater than 2 0: 丨 Estimated interconnect pad-area increase can be obtained at less than 1 cent per circuit chip. Referring to Figs. 4 and 5 ', the RFID tag 100 includes a base body 30 and an antenna 32 formed on a surface 34. As shown, the 'antenna 32 includes a first antenna element including a first coupling region 38 and a second antenna element 40 including a second coupling region 42. I understand that the * antenna 32 can be formed by the coil antennas of the first and second wires without departing from the scope of the present invention. The radio frequency identification tag circuit chip 24 is fixed on the surface 34 and is located between the first coupling region 38 and the second coupling region 42. As shown in Figure 5, the first layer 26 is coupled to the first coupling region 38 via the conductive material layer 44 * Similarly, the second layer 28 is coupled to the second coupling via the Mann material layer 46

45582 6 五、發明說明(6) 合區42。 _· 如上所述,由於利用印刷技術形成第一層及第二層,每 層均可實質上較在電路晶片11上利用光屏蔽’電鍍及相似 技術形成放大之金屬互連焊墊之成本較少°吾人相信第‘·一 層26及苐二層28可在-每一電路晶片成本少於1美分之下形 成。因此,可獲得互連焊墊面積之實質增加’而與利用現 有科技形成之放大金屬焊墊相較之成本則降低。 圖6及圖7顯示與一射頻識別·_標記1 〇 2之一部份相關之另 一較佳射頻識別標記電路晶片1 1 〇。射頻識別標記1 0 2與射 頻識別標記1 0 0為相似之結構並包含一形成於基體1 04上之 天線。天線包括一或多個天線天件,如圖式,尚包括第一 轉合區106及第二耦合區108。 射頻識別標記電路晶片1 1 0固定在基體1 04上,與耦合區 1 0 6及耦合區1 〇 8之間。射頻識別標ί己電路晶片11 〇包括電 路晶片111,其:包括第一互連焊墊112及第二互連焊塾114 於表面118上。電路晶片111尚包括第一側表面120及第二 側表面1 2 2,實質上與表面11 8成垂直安排。第一絕緣層 124包括一孔隙125包圍第一互連焊墊1 12在電路晶片ill形 成。第一絕緣層1 24延伸過表面1 1 8及向下過第一側表面 120貫質上為電路晶片111全長。同理’包括孔隙127包圍 第二互連焊墊11 4之第二絕緣層1 2 6在射頻識別標記電路晶 jU〇上形成。第二絕緣層126延伸過表面118及向下過第 ~~側表面1 2 2 ’實質上為電路晶片1 1 1之全長。 導電材料之第一層128及導電j料之第二層13〇各在每一45582 6 V. Description of invention (6) Joint area 42. _ · As mentioned above, since the first layer and the second layer are formed by using printing technology, each layer can be substantially more expensive than forming an enlarged metal interconnection pad on the circuit wafer 11 by using light shielding 'plating and the like. I believe that the first layer 26 and the second layer 28 can be formed at a cost of less than 1 cent per circuit chip. Therefore, a substantial increase in the area of the interconnect pads can be obtained, and the cost is reduced compared to the scaled-up metal pads formed using existing technology. Figures 6 and 7 show another preferred RFID tag circuit chip 1 1 0, which is related to a part of a RFID tag 1 02. The radio frequency identification mark 1 0 2 and the radio frequency identification mark 1 0 0 have a similar structure and include an antenna formed on the substrate 104. The antenna includes one or more antenna antennas, as shown in the figure, and further includes a first turning region 106 and a second coupling region 108. The radio frequency identification marking circuit chip 110 is fixed on the base body 104, and is between the coupling region 106 and the coupling region 108. The radio frequency identification circuit chip 110 includes a circuit chip 111, which includes a first interconnect pad 112 and a second interconnect pad 114 on the surface 118. The circuit wafer 111 further includes a first side surface 120 and a second side surface 1 2 2, which are arranged substantially perpendicular to the surface 118. The first insulating layer 124 includes a hole 125 formed on the circuit wafer ill to surround the first interconnection pad 112. The first insulating layer 1 24 extends across the surface 1 1 8 and downwards through the first side surface 120 to substantially the entire length of the circuit chip 111. In the same way, a second insulating layer 1 2 6 including a hole 127 surrounding the second interconnection pad 114 is formed on the radio frequency identification mark circuit jU0. The second insulating layer 126 extends across the surface 118 and downward through the ~~ side surface 1 2 2 ′, which is substantially the entire length of the circuit wafer 1 1 1. The first layer 128 of conductive material and the second layer 13 of conductive material are each on each

455826 五、發明說明(7) 第一絕緣層124及第二絕緣層126上形成。第一層128包括 一部份1 2 9-延伸通過孔隙1 2 5並耦合至第一互連焊塾丨丨2。 第一層128亦包括一部份132在表面128上蓋住地_絕緣層 124及一部份134延伸過第一側表面120。第二層i3Q包括.一 部份131延伸通過孔隙丨27及耦合至第二互連焊墊丨14。第 二層包括一部份136在表面118上蓋住第二絕緣層126,及 一部份13 8延伸第二側表面1 2 2。 圖7可清楚看到,射頻識別標記電路晶月11 〇固定在基體 104上之後,部份134及部份138在鄰近第一耦合區1〇6及第 二耦合區108分別對齊。導電材料層140及導電材料層142 為印刷沉積,並分別耦合部份1节4至第一耦合區1〇6,及將 部份138輕合至第二搞合區108。以此方式,射頻識別標記 電路晶>1110被有效的耦合至基體104上之天線。 參考圖8,其中顯示射頻識別標記'電路晶片1 1 〇搞合至本 發明另一較佳真體實例之基體204。基體204包括表面 206,天線(未示出)即在其上形成。基體2〇4之形成包括一 凹隙208 ’射頻識別標記電路晶片即固定其内。天線包 括第一耦合區210及第二耦合區212。每一第一耦合區210 以及第二耦合區212延伸進入凹隙208及鄰近部份134及部 份138。溝道214及溝道2 16於是在部份134與第一耦合區 21 0之間及在部份1 3 8與第二耦合區2 1 2之間分別建立。導 電材料層218及導電材料層220分別沉積進入溝道214及溝 道216。層218耦合部份134至第一耦合區210,層220輛合 部份138至第二耦合區21 2。較佳^之導電材料包括導電油455826 V. Description of the invention (7) The first insulating layer 124 and the second insulating layer 126 are formed. The first layer 128 includes a portion 1 2 9- extending through the aperture 1 2 5 and coupled to the first interconnect pad 丨 丨 2. The first layer 128 also includes a portion 132 covering the ground-insulating layer 124 on the surface 128 and a portion 134 extending across the first side surface 120. The second layer i3Q includes a portion 131 extending through the aperture 27 and coupled to the second interconnect pad 14. The second layer includes a portion 136 covering the second insulating layer 126 on the surface 118, and a portion 138 extends the second side surface 1 2 2. It can be clearly seen in FIG. 7 that after the radio frequency identification marking circuit wafer 110 is fixed on the substrate 104, the portions 134 and 138 are aligned adjacent to the first coupling region 106 and the second coupling region 108, respectively. The conductive material layer 140 and the conductive material layer 142 are deposited by printing, and respectively couple a portion 4 to the first coupling region 106 and a portion 138 is lightly closed to the second coupling region 108. In this way, the radio frequency identification tag circuit crystal> 1110 is effectively coupled to the antenna on the substrate 104. Referring to FIG. 8, there is shown a radio frequency identification tag 'circuit chip 1 10' that is coupled to a substrate 204 of another preferred embodiment of the present invention. The base body 204 includes a surface 206 on which an antenna (not shown) is formed. The formation of the substrate 204 includes a recessed 208 'radio frequency identification circuit chip which is fixed therein. The antenna includes a first coupling region 210 and a second coupling region 212. Each of the first coupling region 210 and the second coupling region 212 extends into the recess 208 and adjacent portions 134 and 138. The channel 214 and the channel 2 16 are then established between the portion 134 and the first coupling region 2 10 and between the portion 1 38 and the second coupling region 2 12 respectively. A conductive material layer 218 and a conductive material layer 220 are deposited into the channel 214 and the channel 216, respectively. The layer 218 couples the portion 134 to the first coupling region 210, and the layer 220 couples the portion 138 to the second coupling region 212. Preferred conductive materials include conductive oil

O:\60\60346.PTD 第10頁 455826 五、發明說明(8) 墨’導電聚合物及膠合劑之一組材料。導電膠合劑除能電 輕合射頻識別標記電路晶片1 1 〇至天線外,尚可提供增加 之機械應力之優點,以保留射頻識別標記電路晶片1 1 0於 凹隙208中。凹隙208最好有一深度,俾射頻識別標記電‘路 晶片能配置在表面2 0—6之下,因此、.保護射頻識別標記電路 晶片110不致與基體204脫離。凹隙208亦可消除或降低在 覆蓋層之電路晶片造成之突起部,並可降低在隨後之堆積 程序中之應力。凹隙208最好由基體204之局部壓縮形成。 此種局部壓縮部份可用沖壓或鑄造形成。凹隙2 〇 8可由固 定在基體204上之薄片形成’形成之薄晶片含一孔隙β 總結而論’並參考圖1 ’圖2多圖3,一射頻識別標記電 路晶片10包括一具有表面U及至少一互連焊墊12及在表面 1 8上形成互連焊墊1 4之電路晶片u。絕緣材料層24沉積在 表面上及鄰近至少一互連焊墊,導電材料層26沉積在絕緣 材料上並搞合至互連焊塾。 參考圖4及5 ’射頻識別標記1 〇 〇包括一射頻識別標記電 路晶片10固定在基體30上《基體3〇之形成包含—天線32 , 及射頻識別標記電路晶片1 〇之形成包括至少—印刷互連焊_ 墊。此印刷互連焊墊為導電材料層2 β , 2 8 ’印刷沉積在電 路晶片11之表面18上,並耦合至在表面18中形成之互連焊 墊1 2,14並耦合至天線32。 參考圖6及7,射頻識別標記} 〇2包括固定在基體i 〇4上之 射頻識別標記電路晶片丨丨〇。基體1 〇 4形成後包括一天線, 射頻識別標記電路晶片1 1 〇之形_^包括至少—印刷之互連O: \ 60 \ 60346.PTD Page 10 455826 V. Description of the invention (8) Ink 'conductive polymer and a group of adhesive materials. In addition to the light conductive RFID tag circuit chip 110 to the antenna, the conductive adhesive can also provide the advantage of increased mechanical stress to keep the RFID tag circuit chip 110 in the recess 208. The recess 208 preferably has a depth. The radio frequency identification tag circuit can be disposed below the surface 20-6. Therefore, the radio frequency identification tag circuit chip 110 is not separated from the base body 204. The recess 208 can also eliminate or reduce the protrusions caused by the circuit wafer of the cover layer, and can reduce the stress in the subsequent stacking process. The recess 208 is preferably formed by local compression of the base body 204. Such a locally compressed portion can be formed by stamping or casting. The recess 2 08 can be formed by a sheet fixed on the base body 204. 'The formed wafer contains a void β. In summary' and referring to FIG. 1, FIG. 2 and FIG. 3, an RFID circuit chip 10 includes a surface U And at least one interconnect pad 12 and a circuit chip u forming the interconnect pad 14 on the surface 18. An insulating material layer 24 is deposited on the surface and adjacent to at least one interconnect pad, and a conductive material layer 26 is deposited on the insulating material and bonded to the interconnect pad. Referring to FIGS. 4 and 5, the radio frequency identification mark 100 includes a radio frequency identification mark circuit chip 10 fixed on a base 30, and the formation of the base 30 includes an antenna 32, and the formation of the radio frequency identification circuit chip 100 includes at least printing. Interconnect solder_ pad. This printed interconnection pad is a layer of conductive material 2 β, 2 8 'printed deposited on the surface 18 of the circuit wafer 11 and is coupled to the interconnection pads 12, 14 formed in the surface 18 and coupled to the antenna 32. Referring to FIGS. 6 and 7, the radio frequency identification mark} 〇2 includes a radio frequency identification mark circuit chip 丨 丨 0 fixed on the substrate i 〇4. After the base body 104 is formed, it includes an antenna, and the shape of the radio frequency identification tag circuit chip 1 1 10 includes at least-printed interconnections.

4 5 582 6 五、發明說明(9) 焊墊。此互連焊墊為導電材料之層1 2 8,1 3 0,印刷沉積在 電路晶片1-41之表面118,120,122上,並耦合至在電路晶 片Π1上形成之一互連焊墊112,114。此印刷互連焊墊又 耗合至天線。 '‘ 參考圊8,射頻識別標記2 0 2包抵固定在基體2 0 4中形成 之凹隙2 0 8之射頻識別標記電路晶片1 1 0。基體2 0 4之形成 包括一天線,射頻識別標記電路晶月1 1 0之形成包括至少 —印刷互連焊墊。此印刷互連‘·焊墊為導電材料層128, 1 3 0,以印刷沉積在電路晶片11 1之表面1 1 8,1 2 0,1 2 2 上,並耦合至在電路晶片上形成之互連焊墊112,114。印 刷之互連焊墊又耦合至天線。二 印刷之互連焊墊可提供實質上較大之射頻識別標記之耦 合面積。利用印刷技術及導電油墨,導電聚合體或導電膠 合劑可優異的使互連焊墊之面積增茄而不增加電路晶片之 成本。相較之下,根據本發明較佳具體實例形成之印刷互 連焊墊可以每電路晶片少於1美分之成本形成。 與已知科技產生之金屬化焊墊相較,較大之印刷互連焊 墊亦可簡化製造方法。較大焊墊易於與在基體材料上形成 之天線元件對齊。 許多額外之改變與修正均屬可行而不悖本發明之範圍與 精神。某些改變之範圍已討論如上。其他範圍將可自所附 之申請專利範圍變為更清晰。4 5 582 6 V. Description of the invention (9) Solder pad. This interconnect pad is a layer of conductive material 1 28, 130, printed and deposited on the surfaces 118, 120, 122 of the circuit wafer 1-41, and is coupled to an interconnect pad formed on the circuit wafer Π1. 112, 114. This printed interconnect pad is dissipated to the antenna. '' Reference 圊 8. The radio frequency identification mark 2 0 2 covers the radio frequency identification mark circuit chip 1 1 0 formed in the recess 2 0 8 formed in the base body 2 0 4. The formation of the base body 2 0 4 includes an antenna, and the formation of the radio frequency identification marking circuit 1 10 includes at least-printed interconnect pads. This printed interconnect '· pad is a conductive material layer 128, 1 3 0, which is printed and deposited on the surface 1 1 8 1 2 0, 1 2 2 of the circuit wafer 11 1 and is coupled to the circuit wafer 11 Interconnect pads 112, 114. The printed interconnect pads are coupled to the antenna. 2. The printed interconnect pads can provide a substantially larger coupling area for RFID tags. Using printing technology and conductive inks, conductive polymers or conductive adhesives can significantly increase the area of interconnect pads without increasing the cost of circuit chips. In contrast, a printed interconnect pad formed in accordance with a preferred embodiment of the present invention can be formed at a cost of less than one cent per circuit wafer. Larger printed interconnect pads can also simplify manufacturing methods compared to metallized pads produced by known technologies. Larger pads are easier to align with antenna elements formed on the base material. Many additional changes and modifications are possible without departing from the scope and spirit of the invention. The scope of some changes has been discussed above. Other scopes will become clearer from the scope of the attached patent application.

第12頁Page 12

Claims (1)

455826 六、申請專利範圍 1. 一種射頻識別標記電路晶片包含: 一電路晶·片具有一表面及至少一在表面上形成之互連烊 墊:及 —導電材料層實質上較至少一互連焊墊為大,及沉積‘在 表面上並耦合至至少:一互連焊墊。ί 2. 如申請專利範圍第1項之射頻識別標記電路晶片,尚 含一絕緣材料層·,沉積在表面與導電材料層之間。 3. 如申請專利範圍第2項之射頻識別標記電路晶片,其 中導電層為印刷在絕緣材料層上。 4. 如申請專利範圍第2項之射頻識別標記電路晶月,其 中絕緣材料層包含非導電聚合物,非導電油墨及非導電膠 合劑之一。 5. 如申請專利範圍第2項之射頻識別標記電路晶片,其 中絕緣材料層係印刷在表面上,導ΐ材料層係印刷在絕緣 材料層上。 6. 如申請專利範圍第1項之射頻識別標記電路晶,其 中導電材料包含導電油墨,導電聚合物及導電膠合劑之 -— 。 7. 如申請專利範圍第1項之射頻識別標記電路晶月,其 中之表面尚含電路晶片之一側表面。 8. 如申請專利範圍第1項之射頻識別標記電路晶月,其 中之電路晶片係固定在基體上 > 基體之形成包括一天線, 天線耦合至導電材料層。 9. 如申請專利範圍第8項之射|員識別標記電路晶片,尚455826 VI. Application for Patent Scope 1. A radio frequency identification mark circuit chip includes: a circuit crystal chip having a surface and at least one interconnect pad formed on the surface: and—a layer of conductive material is substantially more solderable than at least one interconnect The pad is large, and is deposited on the surface and is coupled to at least: an interconnect pad. ί 2. For example, the radio frequency identification marking circuit chip of the scope of patent application No. 1 still contains an insulating material layer, which is deposited between the surface and the conductive material layer. 3. For the radio frequency identification marking circuit chip of item 2 of the patent application scope, wherein the conductive layer is printed on the insulating material layer. 4. For the radio frequency identification marking circuit crystal moon in the second patent application scope, the insulating material layer includes one of a non-conductive polymer, a non-conductive ink, and a non-conductive adhesive. 5. For the radio frequency identification mark circuit chip of the second patent application range, the insulating material layer is printed on the surface, and the conductive material layer is printed on the insulating material layer. 6. For the radio frequency identification marking circuit crystal of item 1 of the patent application scope, wherein the conductive material includes conductive ink, conductive polymer and conductive adhesive--. 7. If the radio frequency identification marking circuit crystal moon of item 1 of the patent application scope, the surface thereof also includes one side surface of the circuit chip. 8. If the radio frequency identification tag circuit crystal moon of item 1 of the patent application scope, wherein the circuit chip is fixed on the substrate > The formation of the substrate includes an antenna, and the antenna is coupled to the conductive material layer. 9. If the application of the scope of the patent No. 8 shooting | identifying the circuit chip, 第13頁 45582 S 六、申請專利範圍 含一導電膠合劑將導電材料耦合至天線。--1 0 . —種射頻識別標記電路晶片包含: 一電路晶片具有第一互連焊墊及第二互連焊墊; 一絕緣材料層配置在電路晶片之一表面,此形成之絕‘‘緣 材料層包括第一孔隙-及第二孔隙第一孔隙及第二孔隙可 將第一互連焊墊及第二互連焊墊通過絕緣材料層予以暴 τΤγ· * 路 ) 一苐一導電材料層配置在絕·緣#料層上,及耗合至第一 互連焊墊;及 一第二導電材料層配置在絕緣材料層上,及耦合至第二 互連焊墊。 二 1 1.如申請.專利範圍第1 0項之射頻識別標記電路晶片, 其中絕緣材料層係印刷在表面上。 1 2.如申請專利範圍第1 0項之射頻^識別標記電路晶>;, 其中第一導電材料層及第二導電材料層係印刷在絕緣材料 層上。. 1 3.如申請專利範圍苐1 0項之射頻識別標記電路晶另, 其中之表面尚含第一側表面及第二側表面。 1 4.如申請專利範圍苐1 3項之射頻識別標記電路晶片, 其中之絕緣材料層包含第一絕緣材料層配置在第一側表面 上,及第二絕緣材料層配置在第二側表面上。 1 5.如申請專利範圍第1 4項之射頻識別標記電路晶月, 其中第一導電材料層配置在第一絕緣材料層上及第二導電 材料層配置在第·二絕緣材料層4。Page 13 45582 S VI. Scope of patent application Contains a conductive adhesive to couple conductive materials to the antenna. -1 0.-A radio frequency identification tag circuit chip includes: a circuit chip having a first interconnection pad and a second interconnection pad; an insulating material layer disposed on a surface of the circuit wafer, and the formation of the insulation chip '' The edge material layer includes first pores and second pores. The first pores and the second pores can expose the first interconnect pads and the second interconnect pads through the insulating material layer. ΤΤγ · * Road) One conductive material And a second conductive material layer is disposed on the insulating material layer and is coupled to the second interconnection pad. 2 1 1. If you apply, the radio frequency identification mark circuit chip of item 10 of the patent scope, wherein the insulating material layer is printed on the surface. 1 2. The radio frequency identification tag circuit crystal according to item 10 of the patent application, wherein the first conductive material layer and the second conductive material layer are printed on the insulating material layer. 1 3. According to the patent application scope of item 10 of the RFID circuit, the surface also includes the first side surface and the second side surface. 14. The radio frequency identification mark circuit chip according to item 13 of the patent application, wherein the insulating material layer includes a first insulating material layer disposed on the first side surface, and a second insulating material layer disposed on the second side surface. . 1 5. The radio frequency identification marking circuit crystal moon according to item 14 of the scope of patent application, wherein the first conductive material layer is disposed on the first insulating material layer and the second conductive material layer is disposed on the second and second insulating material layer 4. 第Μ頁 45 5B2 6 六、申請專利範圍 1 6.如申請專利範圍第1 0項之射頻識別標記電路晶片, 其中導電枒料包含導電油墨,導電聚合物及導電膠合劑之 -— 。 1 7.如申請專利範圍第1 0項之射頻識別標記電路晶片,s 其中絕緣材料含非導-電聚合物,非導電油墨及一非導電膠 合劑之一。 1 8.如申請專利範圍第1 0項之射頻識別標記電路晶片, 其中電路晶片係固定在基體上:,基體形成包括具有第一耦 合區及第二耦合區之天線,第一導電材料層耦合至第一耦 合區,第二導電材料層耦合至苐二耦合區。 1 9,如申請專利範圍第1 8項之=射頻識別標記電路;片, 尚含一導電膠合劑將第一導電材料層及第二導電材料層耦 合。 2 0 . —種射頻識別標記包含: :: 一基體,基體含在其表面上形成之天線;及 —射頻識別標記電路晶片固定在基體上,射頻識別標記 電路晶片至少一印刷互連焊墊形成,及至少一印刷互連焊 墊耦合射頻識別標記電路晶月至天線β 2 1.如申請專利範圍第2 0項之射頻識別標記,其中至少 一印刷之互連焊墊含一導電材料層印刷在電路晶體之一表 面上,及耦合至基體上形成之一互連焊墊上。 2 2.如申請專利範圍第2 1項之射頻識別標記,其中至少 一印刷互連焊墊含一絕緣材料層配置在導電材料層與表面 之間。 -Page M 45 5B2 6 6. Scope of patent application 1 6. If the radio frequency identification mark circuit chip of item 10 of the patent application scope, the conductive material includes conductive ink, conductive polymer and conductive adhesive--. 1 7. The radio frequency identification marking circuit chip according to item 10 of the patent application scope, wherein the insulating material contains one of a non-conductive polymer, a non-conductive ink, and a non-conductive adhesive. 1 8. The radio frequency identification tag circuit chip according to item 10 of the patent application scope, wherein the circuit chip is fixed on the substrate: the substrate is formed to include an antenna having a first coupling region and a second coupling region, and the first conductive material layer is coupled To the first coupling region, the second conductive material layer is coupled to the second coupling region. 19, if the patent application scope of item 18 = radio frequency identification marking circuit; the sheet still contains a conductive adhesive to couple the first conductive material layer and the second conductive material layer. 2 0. — A type of radio frequency identification mark includes :: a base body including an antenna formed on the surface thereof; and — a radio frequency identification mark circuit chip fixed on the base body, and at least one printed interconnection pad formed on the radio frequency identification mark circuit chip. , And at least one printed interconnection pad coupled with the radio frequency identification marking circuit to the antenna β 2 1. The RF identification mark of item 20 in the patent application scope, wherein at least one printed interconnection pad includes a conductive material layer printed An interconnect pad is formed on one surface of the circuit crystal and is coupled to the substrate. 2 2. The radio frequency identification mark according to item 21 of the patent application scope, wherein at least one printed interconnection pad includes an insulating material layer disposed between the conductive material layer and the surface. - 第15頁 45 582 6 六、申請專利範圍 2 3.如申請專利範圍第2 2項之射頻識別標記,其中之絕 緣材料係印刷在表面上。 2 4.如申請專利範圍第2 1項之射頻識別標記,其中之導 電材料含導電油墨,導電聚合物及導電膠合劑之一。‘f 2 5 ·如申請.專.利範圍第2 1項之射.頻識別標記,其中之表 面尚含電路晶片之側表面。 2 6 ·如申請專利範圍第2 1項之射頻識別標記,尚含一導 電材料層耦合至少一印刷互連·焊墊及天線。 2 7.如申請專利範圍第2 0項之射頻識別標記,其中之基 ; 體包括一 C0隙,及射頻識別標記電路晶>!即配置在凹隙 中 〇 . 2 8, —種射頻識別標記包含: 一基體,基體包括一形成在表面上之凹隙及形成在表面 上之天線;及 〜 —射頻識別標記電路晶片配置在凹隙中及固定在基體 上,此射頻識別標記電路晶片至少與一印刷互連焊墊形 成,其中至少一印刷互連焊墊將射頻識別標記電路晶片耦 合至天線。 2 9.如申請專利範圍第2 8項之射頻識別標記,其中至少 —印刷互連焊墊含一導電材料層印刷在電路晶片之表面 上,及耦合至形成在表面上之一互連焊墊。 3 0 ·如申請專利範圍第2 9項之射頻識別標記,其中至少 一印刷互連焊墊含一絕緣材料層,配置在導電材料層與表 面之間。Page 15 45 582 6 6. Scope of patent application 2 3. If the radio frequency identification mark of item 22 of the patent application scope, the insulating material is printed on the surface. 2 4. The RF identification mark according to item 21 of the patent application scope, wherein the conductive material contains one of conductive ink, conductive polymer and conductive adhesive. ‘F 2 5 • If you apply for the radio frequency identification mark of item 21 of the patent, the surface also includes the side surface of the circuit chip. 2 6 · If the radio frequency identification mark in item 21 of the patent application scope, it still contains a layer of conductive material coupled to at least one printed interconnection pad and antenna. 2 7. The RF identification mark according to item 20 of the scope of patent application, wherein the base body includes a C0 gap, and the radio frequency identification mark circuit crystal >! is disposed in the recess. 0.2, a kind of radio frequency identification The mark includes: a base body, the base body including a recess formed on the surface and an antenna formed on the surface; and-the radio frequency identification mark circuit chip is arranged in the recess and fixed on the base body, and the radio frequency identification mark circuit chip is at least Formed with a printed interconnection pad, wherein at least one printed interconnection pad couples the RFID circuit chip to the antenna. 2 9. The radio frequency identification mark according to item 28 of the scope of patent application, wherein at least-the printed interconnection pad contains a layer of conductive material printed on the surface of the circuit chip, and is coupled to an interconnection pad formed on the surface . 30 · If the RFI mark of item 29 of the patent application scope, at least one printed interconnection pad includes an insulating material layer and is disposed between the conductive material layer and the surface. 第16頁 455826 六、申請專利範圍 3 1.如申請專利範圍第3 0項之射頻識別標記,其中之絕 緣層為印刷在表面上。 3 2.如申請專利範圍第2 9項之射頻識別標記,其中之導 電層含導電油墨,導電聚合物及導電膠合劑之一。 〜 .3 3.如申請專利範圍第29項之射.頻識別標記,其中之表 面尚含電路晶片之側表面。 3 4.如申請專利範圍第29項之射頻識別標記,尚含一導 電材料層耦合至少一印刷互連^焊墊及天線。 3 5.如申請專利範圍第2 8項之射頻識別標記,其中之凹 隙含基體之局部壓縮部份。 3 6 .如申請專利範圍第2 8項之漸頻識別標記,其中之凹 隙含一孔隙形成於固定在基體上之一薄疊片中。Page 16 455826 VI. Scope of Patent Application 3 1. For the radio frequency identification mark No. 30 of the scope of patent application, the insulating layer is printed on the surface. 3 2. The radio frequency identification mark according to item 29 of the patent application scope, wherein the conductive layer contains one of conductive ink, conductive polymer and conductive adhesive. ~ .3 3. If the radio frequency identification mark of item 29 of the patent application scope, the surface of which contains the side surface of the circuit chip. 3 4. If the radio frequency identification mark of item 29 of the patent application scope includes a conductive material layer coupled to at least one printed interconnection pad and antenna. 3 5. The radio frequency identification mark according to item 28 of the patent application scope, wherein the recess contains the local compressed part of the substrate. 36. The gradual frequency identification mark according to item 28 of the scope of patent application, wherein the recess contains a pore formed in a thin laminated sheet fixed on the substrate.
TW88115650A 1998-09-11 1999-09-17 Radio frequency identification tag circuit chip having printed interconnection pads TW455826B (en)

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US6693541B2 (en) 2001-07-19 2004-02-17 3M Innovative Properties Co RFID tag with bridge circuit assembly and methods of use
US8698262B2 (en) 2004-09-14 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method of the same
US20060202269A1 (en) 2005-03-08 2006-09-14 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and electronic appliance having the same
CN112163659A (en) * 2020-09-09 2021-01-01 北京智芯微电子科技有限公司 Miniature electronic tag and preparation method thereof

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JP2716336B2 (en) * 1993-03-10 1998-02-18 日本電気株式会社 Integrated circuit device
US5495250A (en) * 1993-11-01 1996-02-27 Motorola, Inc. Battery-powered RF tags and apparatus for manufacturing the same
US5528222A (en) * 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
US5654693A (en) * 1996-04-10 1997-08-05 X-Cyte, Inc. Layered structure for a transponder tag

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