TW454340B - Method for manufacturing PMOS transistor with ultra-shallow junction - Google Patents

Abstract

The present invention discloses a kind of method for manufacturing PMOS transistor, which is especially suitable for use in the manufacturing process having a line width smaller than 0.18 μm and is used to manufacture a PMOS transistor with ultra-shallow junction. The method includes the following steps: (a) providing a semiconductor substrate, on which a gate structure is formed; (b) implanting N-type ions to form a bag-shape doped region in the substrate near the gate edge; (c) performing a rapid thermal annealing procedure; (d) implanting P-type ions to form a lightly doped source/drain region in the substrate on both sides of gate without performing any annealing procedure onto the implanted region; (e) forming a spacer on the sidewall of gate; (f) implanting P-type ions to form a heavily doped source/drain region in the substrate on both sides of gate so as to complete a PMOS transistor with ultra-shallow junction.

Description

464340 V. Description of the Invention (i) [Field of the Invention] The present invention relates to a semiconductor process technology, and relates to a method for fabricating a PM0S transistor with an ultra-shallow junction on a semiconductor substrate. This method is particularly suitable for processes below 0. 8 microns. [Background of the Invention] In order to improve the density and speed of integrated circuits, the channel length of the device must only be possible to reduce. However, as the device shrinks, the distribution of doping concentration in the channel region and the source / drain region must become shallower, so that Avoid short channel effects ° In the past, in the era of large-size components, the junction depth was about 1 to 3 microns, but in today's advanced ultra-large integrated circuit technology, this junction depth (junct I〇I1 Depth) has been reduced to below 0.2 microns. For example, for a 0.18 micron device, the required depth of the source / drain junction may be only 0.07 micron. In order to fabricate semiconductor devices with very shallow junctions, how to accurately control the profile depth after implantation to avoid affecting the effective channel length and junction depth of the MOS has become an important issue in process development. In the manufacturing process of the P-type metal-oxide semiconductor (MOS transistor), a source and a drain are usually implanted into the pMOS using a B + or BF / plasma source. Since the diffusion rate of thallium ions is much faster than arsenic ions, serious transient accelerated diffusion (TED; Transient Enhancement) occurs.

Diffusion), so PM0S is more difficult to make shallow junctions than title. In order to avoid transient accelerated diffusion and increase junction depth, current processes below 0.25 microns are generally based on lightly doped source / drain regions (ldd;

454340 V. Description of the invention (2)

After implantation of Lightly Doped Drain, a rapid thermal tempering is performed to activate the doped ions to maintain a steep doping profile and reduce short channel effects. Please refer to Figure 1. The part of the PM0S transistor in the existing technology is as follows: implant N-type ions to form a pocket-shaped doped region-implant P-type ions to form a nudge source / drain region-rapid thermal tempering Process—Deposition an insulating layer as a gate sidewall layer. According to the above, in order to reduce the phenomenon of transient accelerated diffusion, the current general method 'is to perform a rapid thermal tempering before depositing the sidewall spacer, in order to obtain a shallower joint surface. However, this method is not suitable for forming an ultra-shallow junction, and further correction is necessary. [Summary of the Invention] In view of this, the main object of the present invention is to provide a method for forming a PMOS transistor with a very shallow junction. In order to achieve the above-mentioned purpose, in the method of the present invention, the rapid thermal tempering process of the lightly doped source / dead regions is deliberately omitted, that is, after implanting the lightly doped source / drain regions, Any tempering procedure activates lightly doped source / drain region implant ions. Although this approach runs counter to existing concepts, experimental results show that the method of the present invention can not only obtain a shallower joint depth, but also have significant improvements in the short channel effect and CQV (overlapping capacitance). It is inferred from this that in the process below 0.18 micron, boron enhanced diffusion (BED; boron enhanced diffusion) should be more dominant than transient accelerated diffusion (TED), and the intention of the present invention Omit lightly doped source

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454340 V. Description of the invention

= And the rapid thermal tempering process of the polar region 'can avoid the phenomenon, but is conducive to the formation of very shallow junctions. ^ ^ According to the above, the present invention provides a box of ® ® ® ^ A method for forming a PMOS electric body with a very shallow junction, the main steps include: (0 provide a semiconductor ^ ^ :: pole ^ ⑻ thin type The ions are planted with P-type ions on the pole edge = ，, and the source / non-polar region is processed in the substrate on both sides of the gate, but no tempering process is performed thereon; (6) on the sidewall insulation layer ; And implanting p-type ions, forming a heavily doped source / drain region in the closed substrate, and completing a faceted PMOS transistor. ^ Positioning for the above and other purposes, features, and characteristics of the present invention, The advantages and advantages can be more easily understood. The following is a description of the preferred embodiment and the accompanying details. The details are as follows: 5 days [Simplified description of the diagram] Figure 1 is a part of the PM0S transistor according to the conventional technology. Figure 2 of the manufacturing process is a partial manufacturing flow chart of the PMOS transistor according to the present invention. Figures 3A to 3E are schematic cross-sectional views of the manufacturing process of the pMOS transistor according to the embodiment of the present invention. Figure 4 continued to show the boron ion implantation Concentration depth maps after rtA treatment and without RTA treatment. Figure 5 shows a FIG path length relationship with the starting voltage, wherein. PM0S port lines produced according to the flow chart of the first conventional 1, △ 2 is in accordance with FIG.

454340 V. Description of invention (4) tPM0S produced by the process of the present invention. [Symbol description] 100 ~ semiconductor substrate; 102 ~ gate oxide layer; ~ gate conductive layer; 106 ~ shielding oxide layer ~ bag-shaped doped region; p_ ~ p-type ion lightly doped region; P + ~ P-type ion heavy Doped region; 110 ~ sidewall layer. [Embodiment] The following describes a preferred embodiment of the present invention in detail with reference to FIGS. 2 and 3A to 3E as follows. In this embodiment, a PMOS element is formed on an N-type semiconductor substrate 1 Q 〇 . First, as shown in FIG. 3A, a gate structure is formed on the substrate 100 and includes a gate oxide layer 102 and a gate conductive layer 104. The gate oxide layer 102 is usually formed slowly by using a dry or wet thermal oxidation method at a temperature of 700 to 100 ×, and the thickness is about 10 to 90 A. The gate conductive layer 104 may be a doped complex crystal; an epsilon layer or a polycrystalline silicon silicide layer (ρο 1 yc i de). For example, a polycrystalline silicon gate can be formed by a low-pressure chemical vapor deposition (LPCVD) method to form a layer of polycrystalline silicon with a thickness of about 10,000 to 3,000 A, and then use phosphorous ions or arsenic ions. Plant formation; or, doping can be performed by adding phosphine or arsine 'in-situ' during the process of breaking the sedimentary complex. In addition, when the word line requires a lower resistance, a polycrystalline silicon silicide gate can be formed. For example, a low-voltage chemical vapor deposition method can be used to form a doped polycrystalline silicon layer first, with a thickness of about 100 0 ~ 2000 A, and then a low-pressure chemical vapor deposition method is then used to deposit a silicide metal layer, such as tungsten silicide, with a thickness of about 1,000 to 2000 A. After the gate oxide layer and the gate conductive layer are formed, they are defined as shown in FIG. 3A by using a conventional lithography imaging and etching technique and using a gas-containing etching source.

454340 V. Description of the invention (5) Gate structure. After the etching is completed, the photoresist can be removed using the dry plasma removal process and wet cleaning process of the oxygen plasma. The wet cleaning process can be used to remove the oxide layer that is not covered by the gate conductive layer. ′ Next, as shown in FIG. 3B, a shield oxide layer 106 is formed on the surface of the substrate 100 and the side wall of the gate 104 by a thermal oxidation method, and the thickness is about 20 to 70 A. Because the etching process performed in the aforementioned definition of the gate structure 'may cause some defects in the gate oxide layer and the wafer surface, the re-oxidation process here can restore the damage caused by the etching' and form The shielding oxide layer 10 can be used to protect the gate oxide layer and the substrate from ion damage in the subsequent lightly doped source / light-emitting (LDD) ion implantation. Next, N-type ions are implanted to form a pocket doped region 108 in the substrate near the gate edge. The purpose of forming the bag-shaped doped region iQg is to reduce the risk of pUnch-through. Generally speaking, PM0S can be implanted in the form of a bag with phosphorus or arsenic ions at a dose of about 1 X 1013 ~ 6 X 1013 cnr2 and an energy of about 50 ~ 150 KeV. 0 Please refer to Figure 3C. Next, 'do not do ion implantation of lightly doped source / drain (LDD)', but directly perform a rapid thermal tempering procedure (RTA) 109 to repair the lattice defects caused by bag-shaped implants. On the other hand, if NMOS is produced on the substrate at the same time, the LDK planting of NMOS and the bag-like planting can also be tempered at this time. The rapid thermal tempering here is preferably performed at a temperature of 900 C to 1050 ° C.凊 Refer to Figure 3D and perform the light tempering procedure before completing the light tempering.

454340

Ion implantation of doped source / non-electrode (LDD) implants p-type ions into the substrate on both sides of the gate 'to form a lightly doped source / 彡 and electrode region p-. LMD implantation of PM0S elements can use boron ion (B) or boron difluoride (BF2) ion at a dose of about 1014 ~ 1 015 / cm-2 and an energy of about 1 ~ 1 5 KeV. Please refer to FIG. 3E. After the lightly doped source / inverted region p is implanted, the gate sidewall layer is directly deposited without performing any tempering procedure. For example, a low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) method can be used to deposit an insulating layer having a thickness of about 2000 to 2000 in at 350 to 850 ° C. Nitrile oxide, oxynitride, etc .; if a composite (compos ite) sidewall layer is made, more than one insulating layer can be deposited. After the deposition is completed, using SF6, CF, CHF3, or C2F6 as an etching source 'to perform anisotropic etching using a reactive ion etching process, a sidewall insulating layer 1 10 can be formed on the sidewall of the gate structure. After that, the gate structure and the sidewall layer 110 are used together as a mask, and a higher dose of ions is implanted into the substrate to form a heavily doped source / drain region P +, which is completed as shown in FIG. 3E. PMOS transistor with extremely shallow junction. Here, the heavily doped source / drain region p + can be used under the conditions of a dose of about 1 X 1 〇i5 ~ 7 X 1 〇i5cm-2 and an energy of about 4KeV. Implanted.

Please refer to FIG. 2, which is a flowchart of the local manufacturing steps of the PM0S transistor according to the present invention. It shows that the process steps of the present invention include: implanted ions forming a bag-shaped doped region—rapid thermal tempering process—implanted p-type ions Form lightly doped source / drain regions—deposit an insulating layer D as the gate sidewall layer

454340 V. Description of the invention (7) It can be seen from the comparison between Fig. 1 and Fig. 2 that the present invention is different from the conventional technology in that the invention advances the steps of the rapid thermal tempering process, and omits the lightly doped source / Fast thermal tempering process in the drain region. Please refer to Figure 4. Figure 4 shows the depth map of boron ion implantation (BF2 / 2KeV / lE15) after RTA treatment and without RTA treatment. The pouch grower 'therefore has a total of four curves. It can be seen from the figure that, whether with or without bag-like planting, those without RTA treatment have a relatively shallow joining depth. Please refer to Fig. 5 '. Fig. 5 shows the relationship between a channel length and the starting voltage, where □ is the pM0s produced according to the conventional process of Fig. 1, and △ is the invention according to Fig. 2 Pm0S produced by the process. It can be seen from the figure that 'the PMOS produced according to the present invention has a marked improvement in the short channel effect' and there is no phenomenon of reverse short channel effect (RSCE). Furthermore, k of PMOS according to the conventional process is 0.63, and CQV of PMOS made according to the present invention is 0 to 55, which further proves that the present invention has a shallower interface depth. For the unexpected advancement produced by the present invention, the inventors made the following inferences: Since the critical temperature of the butterfly accelerated diffusion phenomenon (BED) is about wo, once LDD RTA is performed, silicon boride will inevitably be formed ( SiB4). As a result, when the gate sidewall layer is subsequently deposited, Si & s will release interstitials and promote the diffusion of boron ions. In the present invention, since LDD RTA 'is not performed, silicon boride (SiB4) is not formed, and when the sidewall layer is deposited, the phenomenon of accelerated boron diffusion does not occur.

454340 V. Description of the invention (8) Furthermore, because the accelerated diffusion of boron occurs only when the surface concentration is very high, and when the interface is getting shallower, the required implantation dose is getting higher and higher. Accelerated diffusion (BED) may be more advantageous than transient accelerated diffusion (TED). This may explain why the LDD RTA can reduce the junction depth in the 0.25 micron technology, but it will increase the junction depth below 0.15 micron. For the literature on the accelerated diffusion of boron, see ApL, v〇 1

74, No. 16, p. 2331 (1 999) and IEDM 1997, p. 467 (A

Agarwal et al ·) ° Limitation = Hair: The month has been disclosed as above in a preferred embodiment, but it is not used for: Definition 2: Anyone who is familiar with this skill 'is within the range of I and I, and can make various changes and ：： The range of the moon The scope of the present should be attached to the patent please g the scope of the invention

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Claims (1)

454340 VI. Scope of patent application-1. A method for manufacturing pM0s transistor with extremely shallow junction, including the following steps: (a) providing a semiconductor (b) implanting N-type ions, bag shape Doped region; the substrate 'has a gate structure formed on it; (c) a rapid thermal tempering process is performed in the substrate near the edge of the gate; (d) P-type ions are implanted on both sides of the gate A lightly doped source / drain region is formed in the substrate, but no tempering process is performed on it; (e) a sidewall insulation layer is formed on the gate sidewall, and (o-type P-ions are implanted in the A heavily doped source electrode and / or a pole region are formed in the substrate on both sides of the gate, and the p-deleted transistor with an extremely shallow junction is completed. 2. The manufacturing method described in item i of the patent application scope, wherein Step (a) The anode structure includes a gate conductive layer and a gate oxide layer. 3 The manufacturing method as described in the patent application p., Wherein step H is included in the gate sidewall and thermal oxidation method. A mask is formed on the surface of the substrate. 4. The manufacturer described in item 1 of the patent application scope (b) The N-type ion is a phosphorus ion or arsenic ion. 5. The manufacturing method described in item 丨 of the scope of the patent application, wherein the rapid thermal tempering of the steps is performed at a temperature of 900 to 105 (ρ (:). As described in the first scope of the patent application The manufacturing method 'wherein the P-type ion is a boron ion or a boron difluoride ion. 7. The manufacturing method as described in item i of the patent application range' wherein step e includes: depositing an insulating layer on the substrate, and Into the insulation layer Page 13 454340 6. Scope of patent application Anisotropic etching is performed to form a sidewall insulation layer on the sidewall of the gate structure. 8. The manufacturing method according to item 1 of the scope of patent application, wherein step (e) the sidewall insulating layer is selected from the group consisting of silicon oxide, silicon nitride, and oxynitride. 9. The manufacturing method according to item 1 of the scope of patent application, wherein in step (f), the P-type ion is a boron ion or a boron fluoride ion. Page 14