經濟部智慧財產局貝工消费合作杜印装 4 5 13 2 4 5847twf doc/008 B7 _ 五、發明說明（f ) 本發明是有關於一種金氧半導體元件的製造方法， 且特別是有關於一種雙擴面式金氧半導體高電壓元件之 製造方法。 在 1979 年 IEDM Proceedings —書的 238〜241 頁， 一篇標題爲「高電壓薄膜元件（低表面電場元件）」的文 獻中，提出了一種製造金氧半導體高電壓元件的技術， 其變革之處爲在金氧半導體元件的汲極與通道區之間加 入一層淺的淡摻雜區。因爲其中摻質的量變少，以致電 流載子數量也降低，所以這層淺的淡摻雜區可以視爲一 個漂移區（drift region)，而這種金氧半導體元件也因此被 稱作低表面電場（Reduced Surface Field, RESURF)元件。 低表面電場技術係用來製造高電壓N型通道雙擴面 式金氧半導體元件（Lateral Double Diffused MOS， LDMOS)，以及高電壓P型通道雙擴面式金氧半導體元 件。然而，這種低表面電場之雙擴面式金氧半導體元件 存有若干問題。 第1圖所繪示爲習知雙擴面式金氧半導體元件結構 剖面圖。請參照第1圓，N型矽基底100上有一層場氧 化層102，這層場氧化層1〇2係用來增加N型源極區104 與N型汲極區1〇6間的通道長度。N型淡摻雜區108位 於場氧化層102下的矽基底1〇〇中，作爲此元件受到電 壓時的載子漂移區。P型淡摻雜區112位於閘極11〇之 下，P型淡摻雜區112的功用爲增加元件內部的電場強 度’使兀件的橫向導電度（Trans Conductance)得以改善。 3 本纸張尺度適用中S a家標準<CNS)A4嬈格（210 X 297公爱） III — — ! — —— — — > — — — — — — — ·1!111111 (請先閱讀背面之注$項再填窝本頁) 513 24 A7 5847twf.doc/008 B7 五、發明說明（）） (請先《讀背面之注意事項再填寫本頁) 然而，漂移區108中的淡摻雜濃度會使元件的導電度降 低，且由於通道區的長度不易由作爲罩幕的閘極110作 精確控制，所以電場強度難以增加，從而降低了元件的 導電度。另外，在源極端的N+/P/N-易形成寄生二極體而 影響電流驅動能力，並降低高電壓元件之突返電壓 (snape-back voltage) 〇 本發明提供一種雙擴面式金氧半導體高電壓元件及 其製造方法，可以在基底內形成較精確的通道區，並改 善源極與汲極區間之電流驅動能力及上述習知高電壓元 件之缺失。 本發明提供一種雙擴面式金氧半導體高電壓元件， 此元件包括一 N型雙井'一 P型雙井、一閘極結構、一 源極區與一汲極區。其中，N型雙井與P型雙井相鄰， 且N型雙井之內井中包括數個淺溝渠隔離區，P型雙井 包括一溝渠；閘極結構係配置於基底上，由P型雙井之 內井延伸至N型雙井之內井與最遠離汲極區之淺溝渠隔 離區上；汲極區係配置於N型雙井之內井與外井之間； 源極區係配置於閘極結構下方、P型雙井之內井中。 經濟部智慧財產局員工消费合作社印製 本發明提供一種雙擴面式金氧半導體高電壓元件及 其製造方法，一種雙擴面式金氧半導體高電壓元件及其 製造方法，其製造方法係在基底內形成一第一 P井及與 其相鄰之第一 N井，接著於第一 N井內形成數個淺渠溝 隔離區，然後，在>第一 P井中形成一第二P井並於第一 N 井中形成第二N井，之後，形成一閘極結構於基底上，接 4 本紙張尺度適用中國國家標準（CNS>A4規格<210 X 297公釐） 經濟部智慧財產局員工消费合作社印製 51 324 A7 _5847twf.doc/008_B7_______________ 五、發明說明（$ ) 著再進行離子植入製程，以在第二N井中形成汲極區並在 第二P井中形成一摻雜區，之後，去除部分的摻雜區，形 成裸露出第二P井之溝渠，並使留在閘極結構下方之摻雜 區形成源極區。 上述之雙擴面式金氧半導體高電壓元件，以自行對 準的方式形成較精確的通道區，因此可藉由重摻雜之第二 P井增加其電場強度及其導電度。另，形成P型井之溝渠 將大幅地減少N型源極區與P井之接觸界面，因此可大幅 地減少寄生二極體在垂直方向之形成，從而提高其電流驅 動能力，故高電壓元件之突返電壓降低之問題即可獲得 解決。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是習知一種雙擴面式金氧半導體高電壓元件 之結構示意圖。 第2A圖至第2N圖是依照本發明之方法所繪示之雙 擴面式金氧半導體高電壓元件之製造流程的剖面示意圖。 圖式之標記說明： 100 ' 200 基底 1〇2 場氧化層 104,、248、248a 源極區 106、250 汲極區 5 本纸張尺度適用中國國家標準<CNS)A4规格<210 X 297公釐〉 » — — — — — — — ·1111111 111 — — — — — — . <諳先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消t合作社印製 451324 A7 5847twf.doc/008 37 五、發明說明（A ) 108 N型淡摻雜區 110、254閘極結構 112 P型淡摻雜區 202、202a、216 墊氧化層 204, 204a、218 氮化矽層 206 第一 P型離子植入製程 208 氧化層 208a 場氧化層 210、230、246 N型離子植入製程 212 第一 P井 214 第一 N井 219 圖案化之主動區罩幕層 220 淺渠溝隔離 222 襯氧化層 224 ' 224a 絕緣層 226、252 氧化層 228 圖案化之第二N井罩幕層 232 圖案化之第二P井罩幕層 234 P型離子植入製程 236 第二N井 236a N型離子 238 第二P井 238a P型離子 240、240a閘極氧化層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先《讀背面之注$項再填寫本買)Shellfish Consumer Cooperation, Intellectual Property Bureau, Ministry of Economic Affairs, Du Yinzhuang 4 5 13 2 4 5847twf doc / 008 B7 _ V. Description of the Invention (f) The present invention relates to a method for manufacturing a metal-oxide semiconductor device, and in particular to a method for manufacturing a metal-oxide semiconductor device. Manufacturing method of double-expanded metal-oxide semiconductor high-voltage element. In the 1979 IEDM Proceedings — 238 ~ 241 pages of the book, an article entitled “High Voltage Thin Film Element (Low Surface Electric Field Element)” proposed a technology for manufacturing metal oxide semiconductor high voltage elements, and its changes A shallow lightly doped region is added between the drain and channel regions of the metal-oxide semiconductor device. Because the amount of dopants becomes smaller, so that the number of current carriers is also reduced, this shallow lightly doped region can be regarded as a drift region, and this type of gold-oxygen semiconductor device is also called a low surface. Electric field (Reduced Surface Field, RESURF) element. Low surface electric field technology is used to manufacture high-voltage N-channel double-expanded metal-oxide-semiconductor devices (Lateral Double Diffused MOS, LDMOS), and high-voltage P-channel double-expanded metal-oxide semiconductor devices. However, this double-expanded metal-oxide semiconductor device with a low surface electric field has several problems. FIG. 1 is a cross-sectional view showing the structure of a conventional double-expanded metal-oxide semiconductor device. Please refer to the first circle. There is a field oxide layer 102 on the N-type silicon substrate 100. This field oxide layer 102 is used to increase the channel length between the N-type source region 104 and the N-type drain region 106. . The N-type lightly doped region 108 is located in the silicon substrate 100 under the field oxide layer 102 and serves as a carrier drift region when the element is subjected to a voltage. The P-type lightly doped region 112 is located below the gate electrode 110. The function of the P-type lightly doped region 112 is to increase the strength of the electric field inside the device, so that the lateral conductivity of the element can be improved. 3 The standard of this paper is applicable to the standard of Sa < CNS) A4 grid (210 X 297 public love) III — —! — — — — — — — — — — — — 1! 111111 (please first Read the note on the back page and fill in this page) 513 24 A7 5847twf.doc / 008 B7 V. Description of the invention ()) (Please read the “Notes on the back page before filling this page”) However, the The doping concentration will reduce the conductivity of the device, and because the length of the channel region is not easy to be accurately controlled by the gate 110 as a mask, it is difficult to increase the electric field strength, thereby reducing the conductivity of the device. In addition, N + / P / N- at the source extreme easily forms a parasitic diode, which affects the current driving ability and reduces the snape-back voltage of high-voltage components. The present invention provides a double-spreading metal oxide The semiconductor high-voltage element and the manufacturing method thereof can form a more accurate channel region in the substrate, and improve the current driving capability of the source and drain regions and the lack of the above-mentioned conventional high-voltage element. The invention provides a double-enlarged metal-oxide-semiconductor high-voltage element. The element includes an N-type double well, a P-type double well, a gate structure, a source region, and a drain region. Among them, the N-type double well is adjacent to the P-type double well, and the inner well of the N-type double well includes several shallow trench isolation areas, and the P-type double well includes a trench; the gate structure is arranged on the base and is formed by the P-type The inner well of the double well extends to the inner well of the N-type double well and the shallow trench isolation zone farthest from the drain region; the drain region is arranged between the inner and outer wells of the N-type double well; the source region It is arranged in the inner well of P-type double well under the gate structure. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention provides a double-enlarged metal-oxide-semiconductor high-voltage element and a manufacturing method thereof. A first P well and an adjacent first N well are formed in the substrate, and then several shallow trench isolation areas are formed in the first N well. Then, a second P well is formed in the > first P well and A second N well was formed in the first N well, and then a gate structure was formed on the substrate, and 4 paper sizes were applied to Chinese national standards (CNS > A4 specifications < 210 X 297 mm). Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 51 324 A7 _5847twf.doc / 008_B7 _______________ V. Description of the Invention ($) Ion ion implantation is performed to form a drain region in the second N well and a doped region in the second P well. A portion of the doped region is removed to form a trench exposing the second P well, and the doped region remaining below the gate structure forms a source region. The double-expanded metal-oxide-semiconductor high-voltage element described above forms a more accurate channel region by self-alignment. Therefore, it is possible to increase its electric field strength and conductivity by using a heavily doped second P-well. In addition, forming the trench of the P-type well will greatly reduce the contact interface between the N-type source region and the P-well, so the formation of parasitic diodes in the vertical direction can be greatly reduced, thereby improving its current driving ability, so high-voltage components The problem of reducing the sudden return voltage can be solved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a structure diagram of a conventional double-expanded metal-oxide semiconductor high-voltage element. Figures 2A to 2N are schematic cross-sectional views illustrating a manufacturing process of a double-spread metal-oxide semiconductor high-voltage device according to the method of the present invention. Explanation of the marks in the drawing: 100 '200 substrate, 102 field oxide layer 104, 248, 248a source region 106, 250 drain region 5 This paper size is applicable to the Chinese national standard < CNS) A4 specification < 210 X 297 mm> »— — — — — — — · · 1111111 111 — — — — — —. ≪ 谙 Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperative 451324 A7 5847twf .doc / 008 37 V. Description of the invention (A) 108 N-type lightly doped regions 110, 254 Gate structure 112 P-type lightly doped regions 202, 202a, 216 Pad oxide layer 204, 204a, 218 Silicon nitride layer 206 First P-type ion implantation process 208 Oxide layer 208a Field oxide layer 210, 230, 246 N-type ion implantation process 212 First P well 214 First N well 219 Patterned active area mask layer 220 Shallow trench isolation 222 Lining oxide layer 224 '224a Insulating layer 226, 252 Oxide layer 228 Patterned second N-well cover curtain layer 232 Patterned second P-well cover curtain layer 234 P-type ion implantation process 236 Second N-well 236a N Ion 238 Second P well 238a P-type ion 240, 240a Gate oxide layer Applicable to this paper National Standards (CNS) A4 size (210 X 297 mm) (please, "read the back of the note and then fill in this item bought $)
A7 B7 451324 5847twf.doc/008 五、發明說明（t ) 242 ' 242a 摻雜的複晶矽層 244 閘極罩幕層 254 閘極結構 258 溝渠 260 介電層 262、264 接觸窗開口 266、268 接觸窗 會施例 第2A圖至第2N圖是依照本發明之高電壓元件之製 造流程的剖面示意圖。 請參照第2A圖，首先在一基底200上形成一墊氧化 層202，然後進行一淺層P型離子植入製程206，以在基 底200之表層下植入P型離子，例如是硼，接著再沈積一 氮化矽層204於墊氧化層202上。 請參照第2Β圖，形成一圖案化之Ν井罩幕層於氮化 矽層204上（未顯示於圖上），然後進行蝕刻製程，以去 除欲定義之Ν井區內之一部份氮化砍層204、一部份墊氧 化層202及一部份基底200，因此欲定義之Ν井區內具有 Ρ型離子之基底200將一倂被去除。 之後，以熱氧化法形成一氧化層208於欲定義之Ν 井區之部份基底200上，作爲犧牲氧化層，之後，進行一 淺層第一 Ν型離子植入製程210，以在欲定義之Ν井區內 之基底200表層下植入一 Ν型離子，例如爲磷或砷。 請參照第2C圖，進行一離子驅入製程，以使上述植 k—- It I —a « n n n n Λ ·ϋ I (靖先面之注項再填寫本頁> 經濟部智慧財產局貝工消费合作社印製 本紙張尺度遶用中Η B家標準（CNS>A4規格<210 X 297公釐） B7 451324 5 847twf. doc/008 五、發明說明（6 ) 入於基底200之中的P型與N型離子驅入於基底200之中， 以在基底200內形成一第一P井212及相鄰於第一 P井212 之一第一 N井214，而第一氧化層208則因驅入製程而形 成~場氧化層208a。 請參照第2D圖，去除殘留的氮化矽層204a、殘留的 墊氧化層202a及場氧化層208a。然後，依序形成一墊氧 化層216及一氮化矽層218於基底200上，接著，再於氮 化矽層218上形成一圖案化的主動區罩幕層219，例如一 層光阻層。 之後，請參照第2E圖，進行一蝕刻製程，例如爲非 等向性乾式蝕刻製程，以去除未被罩幕層219所覆蓋的氮 化矽層218以及其下方所覆蓋的墊氧化層216與部分的基 底200，以在基底200之中形成渠溝220，渠溝220可爲 複數個’其數量可依設計之需求而有所不同。 請參照第2F圖，去除罩幕層219«之後，形成一襯 氧化層222於渠溝220的內壁上。襯氧化層222的形成方 法例如爲熱氧化法，其厚度約爲100-500A。然後，形成一 絕緣層224於基底200上，並回塡於淺渠溝隔離220內至 基底200頂層以上的位置。絕緣層224之材質例如爲氧化 砂’其形成之方法包括常壓式化學氣相沈積法’所形成之 厚度約爲5000-9000A。 請參照第2G圖，進行一密實化的製程，使形成之絕 緣層224緻密化。然後，進行一化學機械硏磨製程’以去 除多餘的絕緣層224，留下位於於溝渠220之中的絕緣層 8 本紙張尺度適用t國國家禕芈（CNS)A4洗格（210 X 297公釐） \ 1 I! — ·!!! !1 訂·ί!!_ _ I (請先閱讀背面之注意事項再填寫本頁) 經濟邹智慧財產局員Η消費合作杜印製 經濟部智慧財產局員工消费合作社印製 451324 A7 5847twrdoc/008 B7 五、發明說明（？） 224a，以形成淺溝渠隔離結構。接著，再以譬如爲濕式蝕 刻法去除氮化矽層224及墊氧化層216。 請參照第2H圖，之後，形成氧化層226於基底200 上，作爲犧牲氧化層。之後，形成一圖案化之N井罩幕層 228於氧化層226上，然後，進行一 N型離子植入製程230， 以在N井214中植入N型離子236a。 請參照第21圖，去除圖案化之N井罩幕層228。然 後，再形成一圖案化之P井罩幕層232於氧化層226上， 接著進行一 P型離子植入製程234，以在P井212之中植 入P形離子238a。之後，去除圖案化之P井罩幕層232。 請參照第2J圖，進行一回火製程，以使植入於N井 214之中的N型離子236a驅入於基底200之中，而形成 一第二N井236於第一 N井214內，並使植入於P井212 之中的P型離子238a驅入於基底200之中，而形成一第 二P井238於第一 P井212內，其中，第二N井236之範 圍涵蓋淺渠溝隔離220，且其濃度大於第一 N井214之濃 度；第二P井238的濃度大於第一 P井212的濃度。 然後，請繼續參照第2J圖，形成一閘極氧化層240 於基底200上，接著沈積一摻雜的複晶矽層242於閘極氧 化層240上，之後，形成一圖案化的閘極罩幕層244於摻 雜的複晶矽層242上。閘極氧化層240的形成方法譬如爲 熱氧化法；複晶矽層242的形成方法例如爲化學氣相沉積 法。 請參照第2K圖，進行非等向性蝕刻製程，將摻雜的 9 本紙張尺度適用中國國家棵準（CNS)A4規格<21〇 X 297公釐） -----^ · I ] i i 11 I »11 - I --- (請先閲讀背面之注$項再填寫本頁) 451 324 A7 5847twf.doc/008 B7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（$ ) 複晶矽層242以及氧化層240圖案化，以形成一複晶矽閘 極242a與閘極氧化層240a，構成一閘極結構254。然後， 進行一 N型離子植入製程246,以形成一 N型摻雜區248、 250於閘極結構254兩端之基底200內，同時形成一氧化 層252於摻雜的複晶矽曆242a之表面。其中N型摻雜區 248位於第二P井238內，N型摻雜區250位於第二:N井 236內並與該淺渠溝隔離220相鄰接*係作爲汲極區之用 而淺渠溝隔離224a係位於閘極結構254與汲極區250之 間。 請參照第2L圖，形成一源極區罩幕層，然後進行一 蝕刻製程，以去除未被源極區罩幕層所覆蓋之氧化層252 以及其下方之N型摻雜區248，以形成一溝渠258，並使 留下之N型摻雜區248a形成源極區。 之後，請參照第2M圖，在基底200上形成一層介電 層260，此介電層260之材質例如爲氧化矽，形成的方法 例如爲化學氣相沉積法。其後，以微影與蝕刻技術在介電 層260中分別形成裸露出汲極區250之接觸窗開口 262 ; 以及裸露出井區238與源極區248a之接觸窗開口 264。 其後，請參照第2N圖，在基底200上形成一層金屬 層，以塡滿接觸窗開口 262與264，之後，以微影與蝕刻 技術定義金屬層之圖案，以形成與汲極區250接觸之接觸 窗266以及與源極區248a以及井區238接觸之接觸窗 268。 上述實施例中井區與離子植入製程之導電型離子，並 <請先閱讀背面之注$項再填*本霣) in 1· Λ— 訂----- 線t- 適用争困B家標準（CNS)A4規格（210 x 297公釐> A7 B7 4 513 24 5847twf.d〇c/008 五、發明說明（Cf ) 不限於實施例中所敘述，亦即，上述之P型離子或P井可 以N型離子或N井取代，而N型離子或N井可以P型離 子或P井取代之。 本發明提供一種雙擴面式金氧半導體高電壓元件及 其製造方法，此方法係以自行對準的方式形成較精確的通 道區，因此可藉由重摻雜之第二p井增加其電場強度及其 導電度，而第一P井之作用爲中和熱載子之注入，因此可 減少漏電流之發生。另，利用蝕刻製程於形成P型井之溝 渠，可以大幅地減少N型源極區與P井之接觸界面，因此， 可大大地減少寄生二極體在垂直方向之形成，從而提高其 電流驅動能力；此外，在汲極區以淡摻雜劑量的第一 N井 形成底部崩潰電壓(bulk breakdown)，使元件可以承受較高 電壓，並以重摻雜劑量的第二N井提高其電流驅動能力。 故按本發明方法製造之雙擴面式金氧半導體高電壓元件至 少具備下列優點： 1·大幅地減少高電壓元件在垂直方向形成寄生二極 體之現象及減少漏電流之發生，且可以承受較高 電壓，即增加高電壓元件之操作穩定性。 2.提高其電流驅動能力及導電度，即提高高電壓元 件之操作效能。 3_避免高電壓元件產生突返電壓（snap-back voltage) 降低之現象。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 本紙張尺度適用中困國家標準（CNS)A4规格<210 * 297公釐） ------------P--------訂.！！ 請先閱讀背面之注意事項再填寫本頁)A7 B7 451324 5847twf.doc / 008 V. Description of the invention (t) 242 '242a Doped polycrystalline silicon layer 244 Gate cover curtain layer 254 Gate structure 258 Trench 260 Dielectric layer 262, 264 Contact window openings 266, 268 FIG. 2A to FIG. 2N of the embodiment of the contact window are schematic cross-sectional views of the manufacturing process of the high-voltage element according to the present invention. Referring to FIG. 2A, a pad oxide layer 202 is first formed on a substrate 200, and then a shallow P-type ion implantation process 206 is performed to implant P-type ions, such as boron, under the surface layer of the substrate 200, and then A silicon nitride layer 204 is deposited on the pad oxide layer 202. Referring to FIG. 2B, a patterned N-well mask is formed on the silicon nitride layer 204 (not shown in the figure), and then an etching process is performed to remove a part of the nitrogen in the N-well area to be defined. The chopper layer 204, a part of the pad oxide layer 202, and a part of the substrate 200, so the substrate 200 having P-type ions in the N well region to be defined will be removed at once. After that, an oxide layer 208 is formed on a part of the substrate 200 of the N-well region to be defined by a thermal oxidation method as a sacrificial oxide layer. Then, a shallow first N-type ion implantation process 210 is performed to define the An N-type ion, such as phosphorus or arsenic, is implanted under the surface layer of the substrate 200 in the N well region. Please refer to Figure 2C to perform an ion flooding process so that the above-mentioned It — — I I — a «nnnn Λ · ϋ I (please fill in this page before the note above) Printed by the consumer cooperatives. This paper is used in the standard of B. B family standard (CNS > A4 size < 210 X 297 mm) B7 451324 5 847twf. Doc / 008 5. Description of the invention (6) P in the base 200 And N-type ions are driven into the substrate 200 to form a first P-well 212 and a first N-well 214 adjacent to the first P-well 212 in the substrate 200, and the first oxide layer 208 is A driving process is performed to form a field oxide layer 208a. Referring to FIG. 2D, the remaining silicon nitride layer 204a, the remaining pad oxide layer 202a, and the field oxide layer 208a are removed. Then, a pad oxide layer 216 and a pad oxide layer 216 are sequentially formed. A silicon nitride layer 218 is formed on the substrate 200, and then a patterned active area mask layer 219, such as a photoresist layer, is formed on the silicon nitride layer 218. After that, please refer to FIG. 2E for an etching process. For example, it is an anisotropic dry etching process to remove the silicon nitride layer 218 not covered by the mask layer 219 and The pad oxide layer 216 and a part of the substrate 200 are covered below to form trenches 220 in the substrate 200. The trenches 220 may be plural, and the number may vary according to design requirements. Please refer to FIG. 2F After removing the mask layer 219 «, a liner oxide layer 222 is formed on the inner wall of the trench 220. The formation method of the liner oxide layer 222 is, for example, a thermal oxidation method, and its thickness is about 100-500A. Then, an insulation is formed. The layer 224 is on the substrate 200, and returns to the position above the top layer of the substrate 200 in the shallow trench isolation 220. The material of the insulating layer 224 is, for example, oxide sand, and its formation method includes an atmospheric pressure chemical vapor deposition method. The formed thickness is about 5000-9000A. Please refer to FIG. 2G to perform a densification process to densify the formed insulating layer 224. Then, perform a chemical mechanical honing process to remove the excess insulating layer 224 and leave The insulation layer located in the trench 220 is below. The paper size is applicable to the national standard (CNS) A4 washing grid (210 X 297 mm) \ 1 I! — · !!!! 1 Order · ί !! _ _ I (Please read the notes on the back before filling this page) Economy Zou Zhi Member of the Property Bureau, Consumer Cooperation Du printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative of the Ministry of Economic Affairs printed 451324 A7 5847twrdoc / 008 B7 V. Description of the invention (?) 224a to form a shallow trench isolation structure. Then, for example, wet etching method The silicon nitride layer 224 and the pad oxide layer 216 are removed. Referring to FIG. 2H, an oxide layer 226 is formed on the substrate 200 as a sacrificial oxide layer. After that, a patterned N-well mask curtain layer 228 is formed on the oxide layer 226, and then an N-type ion implantation process 230 is performed to implant N-type ions 236a into the N-well 214. Referring to FIG. 21, the patterned N-well cover curtain layer 228 is removed. Then, a patterned P-well mask curtain layer 232 is formed on the oxide layer 226, and then a P-type ion implantation process 234 is performed to implant P-type ions 238a into the P-well 212. After that, the patterned P-well cover curtain layer 232 is removed. Referring to FIG. 2J, a tempering process is performed so that the N-type ions 236a implanted in the N-well 214 are driven into the substrate 200 to form a second N-well 236 in the first N-well 214. The P-type ions 238a implanted in the P well 212 are driven into the substrate 200 to form a second P well 238 in the first P well 212. The range of the second N well 236 covers Shallow trench isolation 220 has a concentration greater than that of the first N well 214; the concentration of the second P well 238 is greater than that of the first P well 212. Then, please continue to refer to FIG. 2J to form a gate oxide layer 240 on the substrate 200, and then deposit a doped polycrystalline silicon layer 242 on the gate oxide layer 240, and then form a patterned gate cover. The curtain layer 244 is on the doped polycrystalline silicon layer 242. The method for forming the gate oxide layer 240 is, for example, a thermal oxidation method; the method for forming the polycrystalline silicon layer 242 is, for example, a chemical vapor deposition method. Please refer to Figure 2K for the anisotropic etching process. The doped 9 paper sizes are applicable to China National Standard (CNS) A4 (<21〇X 297 mm) ----- ^ · I] ii 11 I »11-I --- (Please read the note on the back before filling in this page) 451 324 A7 5847twf.doc / 008 B7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ) The polycrystalline silicon layer 242 and the oxide layer 240 are patterned to form a polycrystalline silicon gate 242a and a gate oxide layer 240a to form a gate structure 254. Then, an N-type ion implantation process 246 is performed to form an N-type doped region 248, 250 in the substrate 200 at both ends of the gate structure 254, and an oxide layer 252 is formed on the doped polycrystalline silicon calendar 242a. The surface. The N-type doped region 248 is located in the second P-well 238, and the N-type doped region 250 is located in the second: N-well 236 and is adjacent to the shallow trench isolation 220. It is shallow and is used as a drain region The trench isolation 224 a is located between the gate structure 254 and the drain region 250. Referring to FIG. 2L, a source mask layer is formed, and then an etching process is performed to remove the oxide layer 252 not covered by the source mask layer and the N-type doped region 248 below it to form A trench 258 causes the remaining N-type doped region 248a to form a source region. After that, referring to FIG. 2M, a dielectric layer 260 is formed on the substrate 200. The material of the dielectric layer 260 is, for example, silicon oxide, and the method of forming the dielectric layer 260 is, for example, chemical vapor deposition. Thereafter, a contact window opening 262 is formed in the dielectric layer 260 to expose the drain region 250; and a contact window opening 264 is exposed to expose the well region 238 and the source region 248a in the dielectric layer 260, respectively. Thereafter, referring to FIG. 2N, a metal layer is formed on the substrate 200 to fill the contact window openings 262 and 264. Then, a pattern of the metal layer is defined by lithography and etching techniques to form a contact with the drain region 250. The contact window 266 and the contact window 268 in contact with the source region 248a and the well region 238. The conductive ions in the well area and the ion implantation process in the above embodiment, and <Please read the note on the back and fill in * this *) in 1 · Λ— Order ----- Line t- Applicable to Distress B Standard (CNS) A4 (210 x 297 mm)> A7 B7 4 513 24 5847twf.doc / 008 5. The description of the invention (Cf) is not limited to that described in the examples, that is, the above-mentioned P-type ions Or P-well can be replaced by N-type ion or N-well, and N-type ion or N-well can be replaced by P-type ion or P-well. The invention provides a double-spread type metal-oxide semiconductor high-voltage element and a manufacturing method thereof. The more accurate channel region is formed by self-alignment. Therefore, the electric field strength and conductivity of the second p-well can be increased by the heavily doped second p-well, and the function of the first p-well is to neutralize the injection of hot carriers. Therefore, the occurrence of leakage current can be reduced. In addition, by using the etching process to form the trench of the P-type well, the contact interface between the N-type source region and the P-well can be greatly reduced, so the parasitic diode can be greatly reduced Direction formation, thereby improving its current driving ability; in addition, the lightly doped dose in the drain region The first N-well forms a bottom breakdown voltage, so that the device can withstand higher voltages, and the second N-well with a heavy doping dose improves its current driving ability. Therefore, the double-expanded gold manufactured according to the method of the present invention Oxygen semiconductor high voltage components have at least the following advantages: 1. Significantly reduce the phenomenon of parasitic diodes in the vertical direction of high voltage components and reduce the occurrence of leakage current, and can withstand higher voltages, that is, increase the stability of high voltage components 2. Improve its current driving ability and conductivity, that is, improve the operating efficiency of high-voltage components. 3_ Avoid the phenomenon of high-voltage components reducing the snap-back voltage. Although the present invention has a better The examples are disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can apply the National Standard (CNS) A4 Specification < 210 * 297 mm) without departing from the paper standard of the present invention --- --------- P -------- Order.! !! (Please read the notes on the back before filling out this page)
-ϋ I 線· 經濟部智慧財產局員工消f合作社印製 4 51 3 24 5847twf.doc/008 A7 B7 五、發明說明（P)精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 --— — —1— — — — —I . I — — ί I 訂·! --- (锖先《讀背面之注f項再填寫本頁) 經濟部智慧財產局員工消费合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* )-ϋ I line · Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the cooperative 4 51 3 24 5847twf.doc / 008 A7 B7 5. In the spirit and scope of the invention description (P), there can be some changes and retouching. The scope of protection of the invention shall be determined by the scope of the attached patent application. --- — — — — — — — — — I. I — — ί I order ·! --- (锖 "Read the f note on the back side before filling out this page) Duo printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 male *)