TW449778B - Method for manufacturing memory device and logic device on the same chip - Google Patents

Abstract

This invention is about the method for manufacturing memory device and logic device on the same chip, in which memory device has the first gate structure on the first region of the chip and the logic device has the second gate structure on the second region of the chip. At first, the first dielectric layer, a polysilicon layer, the first metal silicide layer and a hard mask layer are sequentially formed on the first region and the second region at the same time. Then, the first gate structure of memory device is defined on the first region. After that, the second dielectric layer is formed to cover the first gate structure, while the second gate structure of logic device is not defined yet at this moment. The hard mask layer and the first metal silicide layer on the second region are removed and the olysilicon layer is reserved. Then, the second gate structure of logic device is defined. After that, the lightly doped drain, source/drain and the second metal silicide layer of the logic device are manufactured.

Description

449778 V. Description of the invention (1) 5 -1 Field of the invention The present invention relates to a semiconductor manufacturing technology, and more particularly to a metal silicide process. 5-2 Background of the Invention Advanced semiconductor wafers (ch i p) consisting of logic elements and memory elements (such as dynamic random access memory elements) can already be mass-produced in the industry. Logic elements are generally used to process data or data, while memory elements are used to store data. In a system in which a logic element and a memory element are manufactured separately, the transmission of data signals between the logic element and the memory element often requires packaging through many layers' to cause a delay in time. In order to improve the performance of the component and other considerations such as cost, those familiar with the technology often want to make these components on the same chip. ,

The word line of the logic circuit with dynamic random access memory (DRAM) element = can have two ways: In order to obtain lower resistance, familiar with this technology, P (Rs) is TiSix) Crystallization (polieide) idler θ, dreaming of W / WNX metal gates to achieve this-A Ji made tungsten / tungsten nitride (immature, and has some disadvantages. Its- , 1. However, these technologies are not easy to reduce the yield or increase the working time. 'Daggers are too complicated, so Rong Q /, two, they easily cause metal pollution

4 4 977 8 V. Description of the invention (2) The problem of contamination. Another method to obtain low resistance is to make self-aligned metal salicide 'such as titanium silicide or cobalt silicide. However, this affects the performance of DRAM components. 4 a a m * heart 从 from ~ ^ ^% person silver 4 6 ~ table is because the A element usually does not have a relatively large, doped self-aligned silicide heavily doped regions. •-3 Purpose and summary of the invention According to the above or to manufacture the memory element and the method of the present invention on a first region, the pole structure, the pole structure, the metal layer, and the conductor layer—the second region forms a conductor layer and the first silicon on the region.极 结构。 Polar structure. Then, the first ion implantation forms a first region of a wafer on a region for other purposes. The logic element has a first gate, a second gate, a first petrified metal layer, and a first gate structure. In order to form a first doped dielectric layer to cover the first degree, the second type is removed. On the same wafer, the element is on the wafer, and the element is sequentially on the wafer. First, after forming the first gate on the first region, the first and first doped regions of the wafer and the first silicided metal page 5

4 4 97 7 S V. Description of the invention (3)

Floor. Then, the -p A L is applied to the conductor layer diagram on the first & domain. After that, the ions are formed to form a second second ion implantation m: '-D structure to form the m-th silver 1 of the mask 1 to form a second doped region. The first embodiment of the invention is that the memory element system can be retained and the present invention can be changed by retaining the memory logic element. The three-piece partition wall and the logic element's standing position, such as memory, are the same. Why stinks and thicknesses can be easily explained without the 5-4 pattern: In order to make the above and other purposes of the present day and month + review day skeleton S private $ month more obvious, < easier to understand, the following special features, The advantages and advantages can be explained in detail as follows: · + Preferred examples only, sub-matching with the drawings, as Λ | — |, the method flow of the method of making memory elements and logic elements is shown in the same 2 pieces -F drawing According to the preferred embodiment of the present invention, the above is intended. The main part of the label description: substrate 101 shallow trench isolation area 102 first dielectric layer

Page 6 449778 V. Description of the invention ⑷ 104 polycrystalline silicon layer 106 first silicided metal layer 108 hard cover layer 110 first region 112 gate structure 114 — spacer wall 116 first lightly doped drain electrode 120 second Region 122, second dielectric layer 124, second gate structure 126, second silicided metal layer 128,-spacer wall 132, light-to-drain hybrid drain electrode 134, first doped region 5-4 preferred embodiment first A FIG. 1 to FIG. 1F are schematic cross-sectional views illustrating a method for manufacturing a memory device (such as a dynamic random access memory device) and a logic device on the same chip according to a preferred embodiment of the present invention. Please refer to FIG. 1F, wherein the memory element includes a first gate structure 112 with a first side wall, and the logic element includes a second gate structure 12 with a second side wall.

4 49778 V. Description of the invention (5) Please refer to the first diagram A to provide a substrate, such as a silicon wafer or a silicon substrate 100. The substrate 100 has a first area for a memory element. In addition, the substrate 100 has a first area. The second area 120 is used by logic elements. Next, a first dielectric layer 102, a conductor layer (such as a doped polycrystalline silicon layer ^ 04), and a first dielectric layer 110 are sequentially formed on the first region 110 and the second region 120 of the substrate 100. The silicide metal layer 106 and a hard mask layer 1 ^ The material of the first silicide metal layer 106 may be tungsten silicide (WSi), and the hard mask layer 10 may be made of silicon nitride (SiN), for example. 》 Please refer to the first figure B, 'Pattern the hard mask layer 108, the first silicided metal layer, the polycrystalline silicon layer 104, and the first dielectric layer 102 on the first region 丨 〇' To form a first gate electrode structure 112. Next, a first ion implantation is performed on the first region 11 with the first gate structure 112 as a mask 'to form a first lightly doped drain (LDD) 116. After that, a first spacer 114 is formed on the first side wall of the first gate structure 112. Please refer to the first C diagram. A second dielectric layer 122 is formed on the substrate 100 to partially cover the substrate 100. Wherein the second dielectric layer 丨 2 2 is higher than the first gate structure 112 ′ and is sufficient to cap the first gate structure 112, the first lightly doped drain electrode 116, the first spacer wall 114, and the first gate structure 112 ′. An area 11 〇 to protect these components in subsequent process steps. The above-mentioned formation method of the second dielectric layer 12 is to first deposit an oxide layer (not fully shown) on the substrate 100, and then partially remove the oxide layer by, for example, lithographic etching, so as to Make the remaining oxygen

Page 8 44S778 V. Description of the invention (6) The formation layer may cover the first gate structure 112, the first lightly doped drain electrode 116, the first spacer 114, and the first region no. It is particularly noted that at this time, the second region 110 of the substrate 100 is exposed. Please refer to FIG. -D 'to remove the hard mask layer 108 (FIG. C) and the first silicided metal layer 106 (FIG. -C) H on the second area 120 using, for example, a photolithographic etching technique. The polycrystalline silicon layer 104 (first C picture) located on the second region 120 is patterned to form a second gate structure 124. Then, using the second gate structure 124 as a mask, a second ion implantation is performed on the second region 120 to form a second lightly doped drain electrode 132 in the second region 120. Referring to FIG. -E, two gap walls 128 are formed on the second side wall of the second gate structure 124. The second partition wall 128 and the first partition wall 1 Η may have different materials, and their thicknesses may also be different. This is because when == 128, the first-㈣ is the second; the electric 1 24 is the reference, according to the first F picture, with the second spacer wall 128 and the second gate structure third doped curtain " The third region is implanted at 12 ° to the third ion implantation to form a hetero region (source / drain region) 134 deeper than the second doped region 132. After the pole 132) ~ \ leisure ^ structure 124 and The third doped region 134 (or the second lightly doped drain 126 may be a second silicide metal layer 126. The second silicide metal layer is a titanium silicide (TiSi2) layer, or a cobalt silicide ((: 〇312) layer). 4 4 9778

V. Description of the invention (7) The present invention has at least the following features: 1. The method can retain the manufacturing process of _QK, components, such as from " to [such as dynamic random access memory changes. For example, the self-aligned soap contact window process does not depend on the logic element t + 彳 it ίΛ ^ can maintain the independence of the memory element / logic element, for example, the material and thickness of the partition wall and the thickness of the soil and logic elements can be different from each other. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make equivalent changes or modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention shall be determined by the scope of the appended patent application.

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Claims (1)

449778 6. Scope of Patent Application 1. A method for manufacturing a memory element and a logic element on the same wafer, wherein the memory element has a first gate structure on a first region of the wafer, and the logic element is on the wafer A second region has a second interelectrode structure. The method for manufacturing a memory element and a logic element on the same wafer includes the following steps: sequentially forming a conductor layer and a first silicided metal layer on the wafer; Patterning the first silicided metal layer and the conductor layer on the first region of the wafer to form the first gate structure; using the first gate structure as a mask, performing a first ion on the first region Implanted to form a first doped region; forming a dielectric layer on the first region of the wafer to cover the first gate, the first doped region, and the first region of the wafer; Removing the first silicided metal layer on the second region; patterning the conductor layer on the second region to form the second idler structure; and using the second gate structure as a mask, The second district Weijin A first ion implantation to form a second doped region. „.Made memory cell 2. The method of taking t.1 pieces and logic elements on the same wafer as described in item 1 of the scope of the patent application, wherein the dielectric layer is formed by depositing a layer on the wafer An oxide layer; and, _ ^ α, patterning the remaining oxide layer to partially remove the oxide layer; the oxide layer can cover the first gate electrode on the first region; 449778 VI. Application for Patent Park 3. The method for manufacturing a memory element and a logic element on the same wafer as described in item 范围 of the patent application scope, further comprising forming another gap wall on the side wall of the first gate structure P 4. The method for manufacturing memory cells 2 t2 on the same wafer as described in item 3 of the patent application f, wherein the material and thickness of the partition wall of the first gate structure are different from the second gate structure. The material and thickness of the partition wall 5 · If the scope of patent application is 帛! The same as described in the above item—the method of chip components and logic elements ... The first tungsten (WSi) layer is a kind of silicon-on-a-chip fabrication of a memory cell two-gate structure and the second one. The method of the same item and the logic element described in item 1 further includes forming a second silicided metal layer on the first doped region. 7. The method for applying the same chip device and logic device as described in item 6 of the scope of the patent application, wherein the second silicided Dzin 70 titanium silicide layer and cobalt silicide layer are one of the groups. s, selected from 8.-a kind of memory element and one of the first logic elements on a substrate has a method of manufacturing the logic element of the substrate-the first gate has the memory on the first region Element pole structure, and one of which contains a second side wall Page 12 4 4 9 7 7 8 VI. Scope of patent application Gate structure step: The memory VI is based on the first region on the substrate to form the first implanted with the first free pole to form the first One is structured in the first region, the first doped region is in the second and second removed position. It will be located in the gate structure; implanted in the first sub-region, and thirdly separated in the first and second regions. ; And on the first metal layer. The manufacturing method of the element and the logic element includes sequentially forming a conductor layer and the first silicided metal layer and the conductor layer gate structure on a first silicided metal structure; the structure is a mask, and a first step is performed on the first area. A doped region; a dielectric layer is formed on the first gate and the first region; the first silicided metal layer on the two regions; the conductor layer on the region is patterned to form two gates to form a gate -The free-gap wall and the sub-implanted structure are masks; a second doped region is performed on the second region; a gap wall is formed on the sidewall of the structure; the second gate structure is a mask, So as to form a third doped region deeper than the second gate structure and the ninth process n: ':; ::::::; memory element and logic element step layer; The pattern is separated from the pole junction. The second and second away regions are doped with silicidation. Page 13 4 4 9778 VI. Patent application scope 1 0 · If a patent application method is used, wherein the substrate is deposited on the substrate, the oxide layer can be covered by the oxide layer. 11. A memory device in the same crystal The logic element is provided with a substrate on which a memory is manufactured to provide a substrate for use. In addition, the substrate is further on the first dielectric layer and a multi-layer of the substrate; the first layer and the polycrystalline stone layer will be positioned on the substrate. And a pole structure; implanted with the first pole ion to form on the first gate electrode; the shape of the second dielectric layer on the substrate is higher than that of the memory element and the logic element described in item 8; The method for forming the electrical layer includes: accumulating an oxide layer; and forming a layer to partially remove the oxide layer, so that the first gate structure and the first region remain. 'A method for manufacturing memory elements and logic elements on a chip has a first gate structure with a first side wall' and a second gate structure with a second side wall. The method for the same element and the logic element includes the following steps : The base j has a first region for the memory element and a second region for the logic element; a first crystal layer and a first petrified metal are sequentially formed on the first region and the second region; Layer and a hard mask layer on a hard mask, and the first petrified metal ° diode dielectric layer is patterned to form the first gate structure as a mask, and a first step is performed on the first region. A first doped region; a first gap is formed on the 4th side wall of the yttrium structure to form a second dielectric layer partially covering the substrate, wherein the first gate structure is sufficient to cover the first gate 449778 six Apply for the details ~~ ---- The polar structure and the first impurity region, the hard f on the second region, where the second dielectric layer can be exposed and removed in the second region layer f; layer; The hard cover curtain layer and the first petrified metal will be located on the second region and the second gate structure; 9 the compound silicon layer circle 彳 b to form the second gate structure as Ion implantation to perform a second step on the second region in the second region of the second region to form a second doped region on the second gate structure; the second spacer and the second side A second gap wall is formed on the wall; a third ion implantation is performed in the region, a gate structure is a mask, and the second and second doped regions are formed; and a third-doped region is formed deeper than the first and second doped regions. Second interelectrode structure and metal layer. ^ A second silicide is grown on the second doped region. 12. As described in the patent application No. 丨, the method of the device and the logic device, the memory is fabricated on the same wafer. The forming method includes forming an oxide layer on the substrate; and patterning the oxide layer using a lithography technique to partially remove the oxide layer so that the remaining oxide layer can cover the first gate structure. , The first spacer and the first doped region, and the second region of the substrate is exposed Page 15 4 497TB 6. The scope of the patent application, the second system of the memory and the first wall of the film and the crystal wall are in the same space, the first item in the institute, and the 13th, such as the patent application scope of the 11th element and logic element Method, the walls have different materials. 14. The method for manufacturing a memory element and a logic element on the same wafer as described in item 11 of the scope of the patent application, wherein the first spacer wall and the second spacer wall have different thicknesses. 15. The method for manufacturing a memory element and a logic element on the same wafer as described in item 11 of the scope of patent application, wherein the first petrified metal layer is a dream crane layer. 16. The method for manufacturing a memory element and a logic element on the same wafer as described in item 11 of the scope of patent application, wherein the second metal silicide layer is a titanium silicide layer. 17. The method for manufacturing a memory element and a logic element on the same wafer as described in item 11 of the scope of the patent application, wherein the second silicided metal layer is a silicided silicon. 18. The method for manufacturing a memory element and a logic element on the same wafer as described in item 11 of the scope of the patent application, wherein the polycrystalline silicon layer is a doped polycrystalline silicon layer. Page 16