TW445611B - Encapsulating method of semiconductor device - Google Patents
Encapsulating method of semiconductor device Download PDFInfo
- Publication number
- TW445611B TW445611B TW089115460A TW89115460A TW445611B TW 445611 B TW445611 B TW 445611B TW 089115460 A TW089115460 A TW 089115460A TW 89115460 A TW89115460 A TW 89115460A TW 445611 B TW445611 B TW 445611B
- Authority
- TW
- Taiwan
- Prior art keywords
- mold
- cavity
- semiconductor device
- substrate
- sealing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 44
- 238000007789 sealing Methods 0.000 claims description 23
- 235000012431 wafers Nutrition 0.000 claims description 15
- 239000000565 sealant Substances 0.000 claims description 9
- 239000000084 colloidal system Substances 0.000 claims description 8
- 239000003566 sealing material Substances 0.000 claims description 8
- 239000012812 sealant material Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 3
- 239000000047 product Substances 0.000 description 9
- 238000005266 casting Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- LIMFPAAAIVQRRD-BCGVJQADSA-N N-[2-[(3S,4R)-3-fluoro-4-methoxypiperidin-1-yl]pyrimidin-4-yl]-8-[(2R,3S)-2-methyl-3-(methylsulfonylmethyl)azetidin-1-yl]-5-propan-2-ylisoquinolin-3-amine Chemical compound F[C@H]1CN(CC[C@H]1OC)C1=NC=CC(=N1)NC=1N=CC2=C(C=CC(=C2C=1)C(C)C)N1[C@@H]([C@H](C1)CS(=O)(=O)C)C LIMFPAAAIVQRRD-BCGVJQADSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 241000282994 Cervidae Species 0.000 description 1
- WGCOQYDRMPFAMN-ZDUSSCGKSA-N [(3S)-3-[4-(aminomethyl)-6-(trifluoromethyl)pyridin-2-yl]oxypiperidin-1-yl]-pyrimidin-5-ylmethanone Chemical compound NCC1=CC(=NC(=C1)C(F)(F)F)O[C@@H]1CN(CCC1)C(=O)C=1C=NC=NC=1 WGCOQYDRMPFAMN-ZDUSSCGKSA-N 0.000 description 1
- 239000004414 compression moulding compound Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
4456 11 五、發明說明（1) ------- 發明領域： 本發明係有關於一種半導體裝置之製造方法，特別有關 ;一種半導體裝置封膠方法。 先前技術： 著更輕更複雜電子裝置需求的日趨強烈，晶片的速度 及複雜性相對越來越高，因此需要更高之封裝效率 (Packaging efflciency)。於是半導體晶片封裝業界發展 球格陣列（Ball Grid Array)封裴技術，以符合其需 求。 第一圖所示係為目前習用於形成球格陣列,封裝構造之矩 陣式（matrix)基板片1〇〇之上視圖。該基板另1〇() 一般包含 複數組陣列排列之基板單元1 20，以及複數條電鍍線 (plating bar)130設於该极數個基板單元12〇之間。該每 一基板單元1 2 0之上表面係設有複數條導電線路 (conduct i ve traces ) 1 2 0a ’其一端係用以電性連接至+ 半導體晶片’另一端則連接於該電鍍線1 3 〇。該每一個f' 板單元1 2 0下表面設有複數個錫球銲墊，其分別電性連接 至該基板單元1 2 0上表面相對應之導電線路1 2 0 a。 一般而言，該基板片之基板單元係分成數組進行封膠。 目前半導體業界一般利用習知的傳遞模塑法（transfer molding)形成封膠體來密封晶片與基板。習用之鑄模裝置 (πιο 1 d i ng apparatus) —般設有罐（P〇t)供封膠材料置放。 該罐係經由洗道（r u η n e r )以及澆道口（ g a t e)連接模穴 (c a v i t y )。此外’該鑄模裝置係設有複數個頂針（e j e c t4456 11 V. Description of the invention (1) ------- Field of invention: The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for sealing a semiconductor device. Prior technology: The demand for lighter and more complex electronic devices is increasing, and the speed and complexity of chips are relatively higher and higher, so higher packaging efficiency is required. Therefore, the semiconductor wafer packaging industry developed Ball Grid Array sealing technology to meet its needs. The first figure is a top view of a matrix substrate 100 that is currently used to form a ball grid array and a package structure. The substrate 10 () generally includes a plurality of substrate units 120 arranged in an array, and a plurality of plating bars 130 are disposed between the pole substrate units 120. A plurality of conductive traces (conductive traces) 1 2 0a are provided on the upper surface of each substrate unit 1 2 0, and one end thereof is used to be electrically connected to the + semiconductor wafer. The other end is connected to the plating line 1 3 〇. A plurality of solder ball pads are provided on the lower surface of each f 'board unit 120, which are respectively electrically connected to the conductive lines 12a corresponding to the upper surface of the substrate unit 120. Generally speaking, the substrate units of the substrate sheet are divided into arrays for sealing. At present, the semiconductor industry generally uses a conventional transfer molding method to form a sealing compound to seal the wafer and the substrate. Conventional mold device (πιο 1 d i ng apparatus)-generally equipped with a pot (Pot) for the placement of the sealant material. The tank is connected to the cavity (c a v i t y) via a wash channel (r u η n e r) and a sprue opening (g a t e). Furthermore, the casting device is provided with a plurality of thimbles (e j e c t
PQ0-102-TV. ptd 第4頁 44561 iPQ0-102-TV. Ptd Page 4 44561 i
五、發明說明（2) p i η )用以將模製產物頂出模穴。 該封膠製程一般係先將已裝設半導體晶片之基板片置人 該鑄模裝置’然後將封膠材料置於罐中，並且密合夾緊模 具；接著’在罐内之柱塞（ρ 1 unger )開始移動壓縮封膠村 料，使其經由澆道以及澆道口而充滿模穴以密封密封晶片 與基板。當封膠塑料充滿模穴後，柱塞保持靜止且持續— 預定時間直至封膠塑料硬化。然後，柱塞上升，打開模 具’去洗道（d e g a t i n g)並且利用該複數個頂針將模製產物 推出模穴。 請參照第二圖’其顯示模製產物自該鑄模裝置取出後之 上視圓。如圖所示，模製產物上形成之封膠體丨4 〇係為正 方形’並且每一封膠體1 40係同時密封基板片丨0〇上的九個 基板單元1 2 0。由於習用鑄模裝置之頂針係設計在封膠體 1 4 0週邊之相對應位置，因此該複數個頂針形成之脫模孔 142係位於該封膠體14〇週邊。當模製品自模具取出後，曄 再經後硬化（post-cure)，打印（marking)，植球（ball mounting)及切割（sawing)等多道加工製程，而完成個別 之球格陣列封裝構造。 一然而，一般而言，客戶會要求最後製得之封裝構造具有 一致的外觀，因此脱模孔142必須設計在每一組基板單元 1 20之外，以免出現在最後製得之球封裝構造的外觀上。 而這將使得基板片上有效之佈線區域（lay〇ut area)變 小’並且浪費封膠材料。 發明概要：5. Description of the invention (2) p i η) is used to push the molded product out of the cavity. The sealing process is generally to first place the substrate wafer with the semiconductor wafer in the mold device, and then place the sealing material in the can and tightly clamp the mold; then, 'the plunger in the can (ρ 1 unger) began to move the compression molding compound to fill the cavity through the runner and the gate of the runner to seal and seal the wafer and the substrate. When the sealant fills the cavity, the plunger remains stationary for a predetermined time until the sealant hardens. Then, the plunger rises, opens the mold ' dewashing channel (d e g a t i n g) and uses the plurality of thimbles to push the molded product out of the cavity. Please refer to the second figure ', which shows the top circle after the molded product is taken out of the mold device. As shown in the figure, the sealing colloids formed on the molded product are square, and each of the colloids 140 is simultaneously sealing the nine substrate units 120 on the substrate sheet 0. Since the ejector pins of the conventional mold device are designed at corresponding positions around the sealing body 140, the ejection holes 142 formed by the plurality of ejector pins are located around the sealing body 140. After the molded product is taken out of the mold, it is subjected to multiple processing processes such as post-cure, marking, ball mounting, and sawing to complete individual ball grid array packaging structures. . First, in general, customers will require the final package structure to have a consistent appearance, so the demolding holes 142 must be designed outside each group of substrate units 120 to avoid appearing in the final package structure. Appearance. And this will make the effective layout area on the substrate sheet smaller and waste the sealing material. Summary of the invention:
4456 1 五、發明說明（3) 本發明之主要目的係提供一種半導體裝置封膠方法用以 形成一封膠體包覆該半導體裝置’其中該封膠體具有複數 個突出部（bulge porU on)分別對應於鑄模裝置之複數個 頂針’使得當利用該複數個頂針將模製產物頂出模穴時， 頂針所形成之脫模孔係位於該封膠體之複數個突出部，藉 此增加基板片上有效之佈線區域。 根據本發明之半導體裝置封膠方法包含下列步驟：（a) 提供一鑄模裝置，其包含一模造部（m〇lding p〇rti〇n)且 有一模穴用以容納該半導體裝置，以及複數個頂針（ej^t P 1 η );( b )密合失緊該模具使得該半導體裝置係位於該模 穴中：（c)將封膠材料注入該模穴中；（d)硬化該封膠材料 而形成一封膠體包覆該半導體裝置，其中該封膠體具 數個突出部（bulge porti〇n)分別對應於該複數個頂針. (e)打開該模具；及（〇利用該複數個頂針將模製產物頂’出 这杈穴，其中該複數個頂針形成之脫模孔係 之複數個突出部。4456 1 V. Description of the invention (3) The main object of the present invention is to provide a method for sealing a semiconductor device to form a colloid to cover the semiconductor device, wherein the sealing compound has a plurality of bulge porU on respectively. The plurality of thimbles in the casting device is such that when the molded product is ejected out of the cavity using the plurality of thimbles, the ejection holes formed by the thimbles are located in a plurality of protrusions of the sealing compound, thereby increasing the effective Routing area. The method for encapsulating a semiconductor device according to the present invention includes the following steps: (a) providing a mold device including a mold section (molding port) and a mold cavity for accommodating the semiconductor device, and a plurality of Thimble (ej ^ t P 1 η); (b) tightly loosening the mold so that the semiconductor device is located in the cavity: (c) injecting sealant material into the cavity; (d) hardening the sealant Material to form a colloid covering the semiconductor device, wherein the sealing colloid has a plurality of protruding portions (bulge portion) respectively corresponding to the plurality of thimbles. (E) opening the mold; and (0 using the plurality of thimbles) The molded product is ejected out of the branch hole, wherein the protruding holes formed by the ejection pins are a plurality of protrusions.
顯ί二瓖Ϊ:明之上述和其他㈣、特徵、和優點能A ',\ 特舉本發明較佳實施例，並配合所附圖亍， 作詳細說明如下。 丨I固不’ 發明說明： ，一圖7不係為根據本發明之球格陣列封裝 本發明之半(未心圖中）取出後之上視圖。根據 覆^半導體ft勝方法係用以形成一封勝體150包 導#裝置。本發明所指的半導體裝置係包含複數個It is obvious that the above and other features, features, and advantages of the invention can be described in detail below with reference to the preferred embodiments of the present invention and the accompanying drawings.丨 I solidly 'Description of the invention:, FIG. 7 is not a top view of the ball grid array package according to the present invention after the half of the present invention (not shown). According to the semiconductor overlay method, it is used to form a single body 150 package guide device. The semiconductor device according to the present invention includes a plurality of
4456 1 五、發明說明4456 1 V. Description of the invention
半導體晶片（未示於圖中）分別電性連接於—基板片 20 0。其中該基板片200較佳係包含複數組陣列排列之基板 單元220，而每一基板單元220係用以安裝一晶片。—^而 ° 基板片2 0 0之基板單元2 2 0係分成數組進行封勝。由第 三圖可知’前述之基板片20 0其基板單元22〇係每九個一组 進行封膠。前述之複數個半導體晶片（未示於圖十）係分 別裝設於基板片2〇0之基板單元220上，然後裝入一鱗模^ 用於本發明封膠方法之鑄模裝置設有罐供封膠材料置 放。該罐係經由澆道以及澆道口連接於模穴。該模穴之形 狀係大致符合封膠體1 5〇之外型。此外，該鑄模裝 '置係設 有複數個頂針（eject pin)其一端可移動出入該鑄模裝置 之模穴’用以將模製產物頂出模穴。 、 值得注意的是，該封膠體1 50大致係為正方形，其 在於具有複數個突出部（bulge port ion) 152分別對鹿、於今 鑄模裝置之頂針並且位於該基板片2 0 0每一組基板單〜元2^ 之外。 接著’將封膠材料置於該鑄模裝置之罐中，並且 緊該鑄模裝置之模具使得設於每一組基板單元上的 晶片係分別置於該鑄模裝置之模穴内。然後，罐中 開始移動壓縮封膠材料。該模具以及封膠材料係先鲈 熱使得當枉塞壓縮封膠材料時，該封膠材料會液化並1經 由該澆道以及澆道口而充滿模穴以包覆該半導體B曰 ， 基板片。當封膠材料充滿模穴後，柱塞會保持靜止且Semiconductor wafers (not shown) are electrically connected to the substrate sheet 200 respectively. The substrate sheet 200 preferably includes a plurality of substrate units 220 arranged in an array, and each substrate unit 220 is used for mounting a wafer. — ^ And ° The substrate unit 220 of the substrate sheet 200 is divided into an array to win. From the third figure, it can be seen that the aforementioned substrate sheet 200 and its substrate units 2220 are sealed in groups of nine. The aforementioned plurality of semiconductor wafers (not shown in FIG. 10) are respectively mounted on the substrate unit 220 of the substrate sheet 200, and then loaded into a scale mold. The mold device used for the sealing method of the present invention is provided with a can. Place the sealing material. The tank is connected to the mold cavity via a runner and a runner gate. The shape of the cavity is approximately the shape of the sealant 150. In addition, the mold assembly is provided with a plurality of eject pins, one end of which can be moved into and out of the mold cavity of the mold device 'to eject the molded product out of the mold cavity. It is worth noting that the sealing compound 150 is generally square, which includes a plurality of bulge port ions 152 respectively facing the deer, the ejector pins of the present molding device, and located on each substrate of the substrate sheet 200. Single ~ Yuan 2 ^ and beyond. Then, the sealing material is placed in the pot of the mold device, and the molds of the mold device are tightened so that the wafers set on each set of substrate units are respectively placed in the mold cavities of the mold device. Then, the jar begins to move the compression sealant. The mold and the sealing material are heated so that when the compression sealing material is plugged, the sealing material will liquefy and fill the cavity through the runner and the gate of the runner to cover the semiconductor substrate. When the sealant fills the cavity, the plunger remains stationary and
4456 14456 1
一預定時間直至封勝材料硬化。然後，柱塞上升且將打開 模具’去淹道（degating)並且利用該複數個頂針將 ^ 物推出模六。 ' 此時，由於該封膠體1 50之突出部丨52係分別對應於該鑄 模裝置之頂針而設，因此該複數個頂針形成之脫^孔^4 係位於該封膠體1 5 0之複數個突出部]5 2。當模製品自模具 取出後，需再經後硬化（post-cure),打印（㈣^叫），\直 球（ball mounting)及切割（sawing)等多道加工製程，而 完成個別之球格陣列封裝構造。 太發明之特徵在於該複數個頂針形成之脫模礼154係被 外移至位在封膠體15〇邊緣之突出部152，因而可有效增加 基板片2 0 0上有效之佈線區域（lay〇ut area)(即所有^ 板單元2 2 0 )，卻不致使脫模孔154出現在最後製得之球& 裝構造的外觀上。此外，一定面積之有效佈線區域（即所 有之基板單元2 2 0 )所需之封膠體丨50可有效縮減，因此 以節省封膠材料。 雖然本發明已以前述較佳實施例揭示，然其並非用以4 定本發明’任何熟習此技藝者，在不脫離本發明之精神^ 範圍内，當可作各種之更動與修改。因此本發明之保護^ 圍當視後附之申請專利範圍所界定者為準。A predetermined time until the seal material hardens. The plunger then rises and will open the mold ' degating and use the plurality of thimbles to push the object out of the mold 6. 'At this time, since the protruding portions of the sealing compound 150 are provided corresponding to the ejector pins of the mold device, the detachment holes ^ 4 formed by the plurality of ejection pins ^ 4 are located in the sealing compound 1 50. Protrusion] 5 2. After the molded product is taken out of the mold, it needs to undergo multiple processing processes such as post-cure, printing (㈣ ^ 叫), \ ball mounting, and sawing to complete individual ball grid arrays. Package structure. The feature of the invention is that the mold release ceremony 154 formed by the plurality of thimbles is moved outward to the protruding portion 152 located on the edge of the sealing body 150, which can effectively increase the effective wiring area (layout) on the substrate 200. area) (that is, all the plate units 2 2 0), but the mold release hole 154 does not appear on the appearance of the final ball & assembly structure. In addition, the sealant 50 required for an effective wiring area of a certain area (that is, all the substrate units 220) can be effectively reduced, thereby saving the sealant material. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to determine the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit of the present invention. Therefore, the protection of the present invention shall be determined by the scope of the appended patent application.
^456 Π 圖式簡單說明 圖不說明· 第1圖：習知用於形成球格陣列封裝構造之矩陣式基板 片之上視圖； 第2圖：習知球格陣列封裝構造之模製半成品自鑄模裝 置取出後之上視圖；及 第3圖：根據本發明之球格陣列封裝構造之模製半成品 自鑄模裝置取出後之上視圖。 圖號說明 100 基板片 120 基板單元 120a 導電線路 130 電鍍線 140 封膠體 142 脫模孔 150 封膠體 152 突出部 154 200 脫模孔 基板片 220 基板單元^ 456 Π A simple illustration of the drawing does not explain. Figure 1: Top view of a conventional matrix substrate used to form a ball grid array package structure. Figure 2: Molded semi-finished self-casting device of a conventional ball grid array package structure. Top view after taking out; and FIG. 3: Top view after taking out the molded semi-finished product of the ball grid array package structure according to the present invention from the mold device. Description of drawing number 100 substrate piece 120 substrate unit 120a conductive line 130 plating line 140 sealant 142 release hole 150 sealant 152 protrusion 154 200 release hole substrate piece 220 substrate unit
P00-1O2-TW. ptd 苐9頁P00-1O2-TW. Ptd 苐 page 9
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089115460A TW445611B (en) | 2000-08-01 | 2000-08-01 | Encapsulating method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089115460A TW445611B (en) | 2000-08-01 | 2000-08-01 | Encapsulating method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW445611B true TW445611B (en) | 2001-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089115460A TW445611B (en) | 2000-08-01 | 2000-08-01 | Encapsulating method of semiconductor device |
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| Country | Link |
|---|---|
| TW (1) | TW445611B (en) |
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2000
- 2000-08-01 TW TW089115460A patent/TW445611B/en not_active IP Right Cessation
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