4 34Λ tlr fO dA /。ο 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（1 ) 本發明是有關於一種記憶體之製造方法，且特別是有 關於一種快閃記憶體(Flash Memory)之製造方法。 電氣抹除式可編程唯讀記憶體(EEPROM)是個人電腦和 電子設備所廣泛採用的記憶體元件。最早傳統的EEPROM 記憶單元係以浮置閘（Floatirtg-Gate)電晶體結構來完成，其 具有可寫入、可抹除、以及斷電後仍可保存數據的優點。 但也有面積太大及存取速度較慢的缺點，典型約在150ns 到200ns之間。近年來已開發出存取速度較快的Flash，真 存取速度約在70ns到80ns之間，美國Intel公司稱之爲快 閃記憶體。 傳統快閃記憶體之電晶體記憶單元之工作原理係利用 熱電子儲存數據及Fowler-Nordheim隧穿效應（Tunneling Effect)抹除數據。即當儲存數據資料時，在汲極區和源極 區間加一約8V高電壓，且在控制閘極層同樣加一高電壓， 使熱電子(Hot Electrons)從源極區流出後，在靠近汲極區附 近穿過隧穿氧化層，注入並陷於浮置閘極層內，也就是習 知汲極側邊注入（Drain Side Injection)的方式。提高了此浮 置閘電晶體的臨限電壓（Threshold Voltage)，達到儲存數據 資料的目的。當要抹除記憶資料時，在源極區施以正電壓 並同時在控制閘極層施以適當的負電壓，使陷於浮置閘極 層內的電子，再度隧穿過隧穿氧化層而脫離出來，使記憶 資料淸除，該浮置閘電晶體回復資料儲存前的狀態。 第1圖係繪示傳統快閃記憶體之佈局(Lay Out)圖。第 2、3與4圖係繪示從第1圖I-Ι剖面方向所得之製造流程 _____________3___ 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） 二*- (請先閲讀背面之注意事項再填寫本頁)4 34Λ tlr fO dA /. ο Printed by the Central Standards Bureau, Ministry of Economic Affairs and Consumer Cooperatives A7 B7 V. Description of the invention (1) The present invention relates to a method for manufacturing a memory, and in particular to a method for manufacturing a flash memory . Electrically erasable programmable read-only memory (EEPROM) is a widely used memory element in personal computers and electronic devices. The earliest traditional EEPROM memory cells were completed with a Floatirtg-Gate transistor structure, which has the advantages of being writeable, erasable, and data can be saved after power off. However, it also has the disadvantages of too large area and slow access speed, typically between 150ns and 200ns. In recent years, Flash, which has a faster access speed, has been developed. The true access speed is between 70ns and 80ns. The Intel Corporation in the United States calls it flash memory. The working principle of the conventional flash memory's transistor memory unit is to erase the data by using thermionic storage data and Fowler-Nordheim tunneling effect. That is, when storing data, a high voltage of about 8V is applied between the drain region and the source region, and a high voltage is also applied to the control gate layer, so that hot electrons (Hot Electrons) flow out from the source region, and then approach The drain region passes through the tunneling oxide layer and is implanted and trapped in the floating gate layer, which is the conventional method of drain side injection. The threshold voltage of this floating gate transistor is increased to achieve the purpose of storing data. When erasing memory data, a positive voltage is applied to the source region and an appropriate negative voltage is applied to the control gate layer to cause the electrons trapped in the floating gate layer to tunnel through the oxide layer again. When it is disconnected, the memory data is erased, and the floating gate transistor returns to the state before the data is stored. Figure 1 is a diagram showing the layout of a conventional flash memory (Lay Out). Figures 2, 3, and 4 show the manufacturing process obtained from the direction of the section I-I in Figure 1 _____________3___ This paper size applies the Chinese National Standard (CNS) A4 (210X297 mm) 2 *-(Please read first (Notes on the back then fill out this page)
經濟部中央標準局員工消費合作社印製Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs
441 1 Ο B 3 5 8 7 t w f <?* 〇 c / 0 0 2 五、發明説明（^-) 剖面圖，而第5與6圖係繪75從第1圖ΙΙ-Π剖面方向所得 之製造流程剖面圖。此習知快閃記憶體之製造方法則如下 所述。 請同時參照第2與5圖’首先，提供一基底1〇，接著 例如使用熱氧化法在此基底10上形成一墊氧化層（未顯 示）。然後例如使用區域氧化法在基底10上形成場氧化層 14(Field Oxide Layer)以定義出元件區（Active Area)。然後， 例如使用濕蝕刻法淸除墊氧化層。接著，例如使用熱氧企 法，使元件區的表面形成一層隨穿氧化層12,厚度爲1OOA。 然後例如使用低壓化學氣相沉積法在此隧穿氧化層12上 形成一層厚度爲1500A的多晶矽物質。然後利用微影蝕刻 技術定義多晶矽物質，以形成多晶矽層16,多晶矽層16 '係作爲快閃記憶體之浮置閘極層之用。 接著例如使用低壓化學氣相沉積法沉積一層內多晶矽 介電物質（Inter-poly Dielectric layer)覆蓋多晶矽層16。此 內多晶矽介電物質的厚度約爲250A，而材質爲氧化物/氮 化物/氧化物（Oxide/Nitride/Oxide)三層結構。然後，使用低 壓化學氣相沉積法在此內多晶矽介電物質上形成另一層多 晶矽物質，此層多晶矽物質的厚度爲3000A。接著，利用 微影蝕刻技術定義此層多晶矽物質並往下蝕刻內多晶矽介 笔物質’藉以形成多晶政層20與內多晶砂介電層18。其 中’多晶矽層20係作爲快閃記憶體之控制閘極層之用。 然後’利用微影蝕刻技術並且以多晶矽層20爲罩幕， 進fr f虫刻步驟，進一步定義多晶砂層16，直至約暴露出基 本紙張尺度適用中國囤家標準（CNS ) a4規格（210X 29"7公釐） (請先聞讀背面之注意事項再填寫本頁j -訂_ 經濟部中央標準局員工消費合作社印製 ^ 4 41 3587tv/f .doc / 002 A7 __—_ B7 五、發明説明（j ) 底10表面。至此，多晶砂層20、內多晶砍介電層18、多 晶矽層16與隧穿氧化層12組成快閃記憶體之閘極電極。 接著，使用一光阻21定義此半導體基底，暴露出閘極 電極其中一側的基底10。並且使用離子植入法，以一傾斜 角度將高濃度的磷離子，植入於暴露出的基底10中，並 進行回火步驟，而形成隧穿擴散區24。此隧穿擴散區24 係延伸至閘極電極下方。 請參照第3圖，當形成隧穿擴散區24之後則移除光fit 21。並使用離子植入法，以多晶矽層20爲罩幕進行離子 植入步驟，植入高濃度的砷離子於基底10中，藉以形成 源極區22a與汲極區22b。其中，隧穿擴散區24包圍住源 極區22a。 請同時參照第4與6圖，然後使用低壓化學氣相沉積 法沉積一層介電層30覆蓋整個基底結構。並且使用微影 蝕刻技術在介電層30上形成接觸窗口 32，此接觸窗口 32 暴露出汲極區22b。並且使用低壓化學氣相沉積法沉積一 層金屬層34，於接觸窗口 32中，且接觸汲極區22b。其 中，金屬層34係作爲位元線之用。然後進行後續的製程 '以完成快閃記憶體之製造。然而，此後續製程爲熟習此技 藝者所能輕易達成，故此處不再贅述。 此習知快閃記憶體是使用熱電子進行編程（Program)的 步驟，而且是利用汲極側邊注入的方式，所以需要較高電 壓（8V)以提供較高的電流。此種習知快閃記憶體在抹除操 作時常會造成過抹除(Over-erase)的現象。 本紙张尺度適用中國國家標率（) Μ規格（210X297公釐） -------^-----2^------訂------卞-1 : ' 二 (請先閲讀背面之注意事項再填寫本頁) A7 B7 4 4 1 Ί U 8 3587twf.doc/002 五、發明説明（f ) 此外，此習知快閃記憶體受限於接觸窗口 32之尺寸， 因此無法有突破性的縮小化。並且因爲形成有場氧化層 14，所以縮小幅度有限，且平坦度不佳。再者，因爲接觸 窗口中需塡入金屬層以作爲位元線之用，因此無法避免金 屬層反射的千擾。 ‘ 因此本發明的主要目的就是在提供一種快閃記憶體之 製造方法，用以改善習知快閃記憶體的缺點。 根攄本發明的目的，提出一種快閃記憶體之製造方法： 包括形成堆疊且已定義之一第一多晶矽層與氧化層於基底 上，此第一多晶矽層之兩側約暴露出基底。形成第一介電 層，例如氧化物/氮化物/氧化物層，覆蓋該第一多晶矽層。 例如使用低壓化學氣相沉積法，彤成第二多晶矽層覆蓋第 一介電層。 例如使用低壓化學氣相沉積法，形成一第二多晶矽層 覆蓋第一介電層。接著，定義第二多晶矽層，用以使得第 二多晶矽層形成一控制閘極層且進一步定義第一多晶矽 層，用以使得第一多晶矽層形成一浮置閘極層，其中控制 聞極層之兩側約暴露出基底。 接著，形成第二介電層，例如氧化物/氮化物/氧化物 層，覆蓋控制閘極層、浮置閘極層、及曝露出之基底。例 如使用低壓化學氣相沉積法，形成一第三多晶矽層於部分 的第二介電層上，且曝露出其餘部分的第二介電層。使用 離子植入法，形成一隧穿擴散區於曝露出的第二介電層下 方之基底中。進一步使第三多晶矽層形成多晶矽間隙壁位 ----*---------衣------訂------卞、 -_" (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部中央標準局貝工消費合作杜印製 ·、在 41 1 Ο 8 3587twf.doc/002 Α7 _Β7_ 五、發明説明（π 於控制閘極層與浮置閘極層之側壁上，藉以使得兩個相鄰 之間隙壁之間曝露出氧化層。使用離子植入法，形成離= 佈植區於曝露出之氧化層下方之基底中。形成導Pjs，例 如金屬矽化物層’覆蓋該第二介電層，並且定義芦， 用以使得導體層形成一選擇閘極層。 ~ θ 本發明是利用源極側邊注入（Source Side Injecti〇n)的 方式’可使記憶胞具有較高的可程式效率與較低的存寫電 流(Write Current) ’例如約爲1〇〇至1〇〇〇微安培（"a)。齒 此，本發明之快閃記憶體不需要高操作電壓，所以可適用 於低伏特與低電源供應的操作中。此外，源極區與汲極區 的離子摻雜是分開進行，可以分別控制摻雜的量，.方便調 整快閃記憶體的參數。 本發明之快閃記憶胞的特性是利用選擇閘防止不當的 潑出電流導致的過度抹除（Over-Erasing)現象，以維持記憶 體的正常運作。 本發明利用離子佈植區係作爲埋入式線（Buried line)之 用°所以不需在後續步驟中形成接觸窗口也不需塡入金屬 層°因此不會有金屬層反射的干擾。 並且’在本發明之製程中不需形成場氧化層，因此依 ί慮本發明之方法所獲得之快閃記憶體，具有較佳的平坦 度’並.且可以大幅縮小尺寸。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， τ文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： :>· C CNS ) A4idT( 210X297¥t"j (請先閲讀背面之注意事項再填寫本頁)441 1 Ο B 3 5 8 7 twf <? * 〇c / 0 0 2 V. Description of the invention (^-) Sectional drawing, and Figs. 5 and 6 are drawn from the cross-sectional direction of Fig. 75 from Fig. 11-II Manufacturing process section. The manufacturing method of the conventional flash memory is as follows. Please refer to FIGS. 2 and 5 at the same time. First, a substrate 10 is provided, and then a pad oxide layer (not shown) is formed on the substrate 10 using, for example, a thermal oxidation method. A field oxide layer 14 is then formed on the substrate 10 using, for example, an area oxidation method to define an active area. Then, the pad oxide layer is removed using, for example, a wet etching method. Next, for example, the surface of the element region is formed with a through oxide layer 12 with a thickness of 100 A by using a thermal oxygen method. Then, a low-pressure chemical vapor deposition method is used to form a layer of polycrystalline silicon material with a thickness of 1500 A on the tunneling oxide layer 12. Then, polycrystalline silicon material is defined by lithographic etching technology to form a polycrystalline silicon layer 16, which is used as a floating gate layer of the flash memory. Next, for example, a low-pressure chemical vapor deposition method is used to deposit an inter-poly silicon dielectric layer (Inter-poly Dielectric layer) to cover the poly-crystalline silicon layer 16. The thickness of the polycrystalline silicon dielectric material is about 250A, and the material is an oxide / nitride / oxide (Oxide / Nitride / Oxide) three-layer structure. Then, another layer of polycrystalline silicon material is formed on the polycrystalline silicon dielectric material by using a low-pressure chemical vapor deposition method, and the thickness of this layer of polycrystalline silicon material is 3000A. Next, the lithographic etching technique is used to define this layer of polycrystalline silicon material and etch the inner polycrystalline silicon dielectric substance 'down to form a polycrystalline political layer 20 and an inner polycrystalline silicon dielectric layer 18. Among them, the 'polycrystalline silicon layer 20 is used as a control gate layer of a flash memory. Then, using the lithographic etching technology and using the polycrystalline silicon layer 20 as a mask, the polycrystalline sand layer 16 is further defined, until the basic paper size is exposed, and the Chinese paper standard (CNS) a4 specification (210X 29 " 7mm) (Please read the notes on the back before filling in this page. J-Order _ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ 4 41 3587tv / f.doc / 002 A7 ____ B7 V. Invention Explanation (j) The surface of the bottom 10. At this point, the polycrystalline sand layer 20, the inner polycrystalline dielectric layer 18, the polycrystalline silicon layer 16 and the tunneling oxide layer 12 constitute the gate electrode of the flash memory. Next, a photoresist 21 is used The semiconductor substrate is defined, and the substrate 10 on one side of the gate electrode is exposed. A high concentration of phosphorus ions are implanted into the exposed substrate 10 at an oblique angle using an ion implantation method, and a tempering step is performed. The tunnel diffusion region 24 is formed. This tunnel diffusion region 24 extends below the gate electrode. Please refer to FIG. 3, when the tunnel diffusion region 24 is formed, the light fit 21 is removed. The ion implantation method is used. , Using polycrystalline silicon layer 20 as a screen In the implantation step, a high concentration of arsenic ions is implanted into the substrate 10 to form a source region 22a and a drain region 22b. The tunneling diffusion region 24 surrounds the source region 22a. Please refer to FIGS. 4 and 6 at the same time. Then, a low-pressure chemical vapor deposition method is used to deposit a dielectric layer 30 to cover the entire base structure. A lithographic etching technique is used to form a contact window 32 on the dielectric layer 30. This contact window 32 exposes the drain region 22b. A low-pressure chemical vapor deposition method deposits a metal layer 34 in the contact window 32 and contacts the drain region 22b. The metal layer 34 is used as a bit line. Then a subsequent process is performed to complete the flash memory. Manufacturing. However, this subsequent process can be easily achieved by those skilled in this art, so it will not be repeated here. The flash memory is a program step using the hot electrons, and it uses the drain side The injection method requires a higher voltage (8V) to provide a higher current. This conventional flash memory often causes over-erase during erasing operations. The paper size is suitable With China National Standard () M specifications (210X297 mm) ------- ^ ----- 2 ^ ------ Order ------ 卞 -1: 'Two (please Read the precautions on the back before filling in this page) A7 B7 4 4 1 Ί U 8 3587twf.doc / 002 5. Invention Description (f) In addition, the conventional flash memory is limited by the size of the contact window 32, so There is no breakthrough reduction. And because the field oxide layer 14 is formed, the reduction is limited and the flatness is not good. Furthermore, because a metal layer needs to be inserted into the contact window as a bit line, it cannot be reduced. Avoid disturbing reflections from metal layers. ‘Therefore, the main object of the present invention is to provide a flash memory manufacturing method to improve the shortcomings of conventional flash memory. Based on the purpose of the present invention, a method for manufacturing a flash memory is provided. The method includes forming a stacked and defined first polycrystalline silicon layer and an oxide layer on a substrate. Both sides of the first polycrystalline silicon layer are exposed approximately. Out of the base. A first dielectric layer, such as an oxide / nitride / oxide layer, is formed to cover the first polycrystalline silicon layer. For example, using a low pressure chemical vapor deposition method, a second polycrystalline silicon layer is formed to cover the first dielectric layer. For example, a low-pressure chemical vapor deposition method is used to form a second polycrystalline silicon layer to cover the first dielectric layer. Next, a second polycrystalline silicon layer is defined so that the second polycrystalline silicon layer forms a control gate layer and a first polycrystalline silicon layer is further defined so that the first polycrystalline silicon layer forms a floating gate. Layer, in which the substrate is exposed on both sides of the control electrode layer. Next, a second dielectric layer, such as an oxide / nitride / oxide layer, is formed to cover the control gate layer, the floating gate layer, and the exposed substrate. For example, a low-pressure chemical vapor deposition method is used to form a third polycrystalline silicon layer on a portion of the second dielectric layer and expose the remaining portion of the second dielectric layer. Using ion implantation, a tunneling diffusion region is formed in the substrate below the exposed second dielectric layer. The third polycrystalline silicon layer is further formed into a polycrystalline silicon interstitial wall ---- * --------- clothing -------- order ------ 卞, -_ " (Please read first Note on the back, please fill out this page again) Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs of the Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm). In 41 1 Ο 8 3587twf.doc / 002 Α7 _B7_ V. Description of the invention (π on the side wall of the control gate layer and the floating gate layer, so that an oxide layer is exposed between two adjacent gap walls. Use The ion implantation method forms an implanted region in the substrate under the exposed oxide layer. A conductive Pjs is formed, for example, a metal silicide layer 'covers the second dielectric layer, and defines a reed for forming a conductive layer One selects the gate layer. ~ Θ The present invention uses a source side injection (Source Side Injection) method to 'allow the memory cell to have higher programmable efficiency and lower write current' For example, about 100 to 10,000 microamperes (" a). To this end, the invention is fast The memory does not need high operating voltage, so it can be used in the operation of low voltage and low power supply. In addition, the ion doping of the source region and the drain region is performed separately, and the amount of doping can be controlled separately. Easy to adjust The parameters of the flash memory. The characteristics of the flash memory cell of the present invention is to use the selection gate to prevent the over-Erasing phenomenon caused by improper spill current to maintain the normal operation of the memory. The present invention uses ions The implantation area is used as a buried line, so there is no need to form a contact window in the subsequent steps, and it is not necessary to penetrate the metal layer. Therefore, there is no interference from the reflection of the metal layer. It is not necessary to form a field oxide layer in the process, so the flash memory obtained by the method of the present invention has better flatness and can be greatly reduced in size. In order to make the above-mentioned objects, features, And advantages can be more obvious and easy to understand, τ Wen special mentions a preferred embodiment, and in accordance with the accompanying drawings, the detailed description is as follows:: > · C CNS) A4idT (210X297 ¥ t " j (Please read the back first Note to fill out this page)
Gi. -訂_ r - / 41 1 Ο 8 L 3 58 7 twf. , d〇C/002 A7 B7 五、發明説明（t) 圖式之簡單說明： 第1圖係繪示傳統快閃記憶體之佈局圖； 第2、3與4圖係繪示傳統快閃記憶體之製造流程剖面 圖，且係從第1圖I-Ι剖面方向所得之製造流程剖面圖； 第5與6圖係繪示傳統快閃記憶體之製造流程剖面圖， 且係從第1圖ΙΙ-Π剖面方向所得之製造流程剖面圖； 第7圖係繪示依據本發明之一較佳實施例之一種快閃 記憶體之佈局圖； " 第8至12圖係繪示依照本發明一較佳實施例的一種快 閃記憶體之製造流程剖面圖，且係沿著第7圖中ΙΠ-ΙΙΙ方 向所得之剖面圖；以及 第13圖係繪示在第12圖的製造步驟中，沿著第7圖 中IV-IV方向所得之剖面圖。 圖示標記說明： 經濟部中央標準局員工消費合作社印製 (請先間讀背面之注意事項再填寫本頁) 10、50 :基底 12、52 :隧穿氧化層 14 :場氧化層 16、62 :浮置閘極層 18、64、70:內多晶砂介電層 20、 60 :控制閘極層 21、 67、74 :光阻 22a、78 :源極區 22b、72 :汲極區 24 :隧穿擴散區 8 本紙張尺度適用中國國家標準（CNS > A4規格（21〇χ297公釐） 經濟部中央標準局員工消費合作社印製 ^4-1 1 〇 3 3B87twf.doc/002 A7 B7 五 ''發明説明（) 32 :接觸窗口 34 :金屬層 68 :多晶矽層 76 :間隙壁 80 :導體層 實施例 第7圖係繪示依據本發明之一較佳實施例之一種快閃 記憶體之佈局圖。第8至12圖係繪示依照本發明一較佳 實施例的一種快閃記憶體之製造流程剖面圖。其中，第8 至丨2圖是繪示沿著第7圖中III-III方向所得之剖面圖。 而第13圖是繪示在第12圖的流程步驟中，沿著第7圖中 IV-IV方向所得之剖面圖。 請參照第8圖，提供一基底50，接著例如使用熱氧化 法在此基底50上形成一層厚度約爲85A至100A的氧化物 質。然後例如使用低壓化學氣相沉積法在此層氧化物質上 形成一層多晶矽物質，此層多晶矽物質的厚度約爲1500A。 接著利用微影蝕刻技術定義此層多晶矽物質與此層氧化物 質，以分別形成多晶矽層54與隧穿氧化層52。其中，多 晶矽層54兩側均暴露出基底表面。 接著例如使用低壓化學氣相沉積法沉積內多晶矽介電 物質57，覆蓋多晶矽層54的表面。此內多晶矽介電物質 57例如爲氧化物/氮化物/氧化物之三層結構，厚度約爲 250A。然後例如使用低壓化學氣相沉積法在此內多晶矽介 電物質上形成一層厚度約爲3000A的多晶矽物質。 9 本紙張尺度i用中國國家標率（CNS > A4規格（210X297公釐） ΓΓ._·—rr-----— (請先閲讀背面之注意事項再填寫本頁) 訂 -r''-'._ 經濟部中央標準局貝工消費合作社印裝 r '' 4 41 1 〇 δ 3 537twf .〇〇c/0 〇5 A7 B7_____ 五、發明説明（？） 然後，使用一罩幕與蝕刻技術定義多晶矽物質，藉以 使得多晶矽物質成爲多晶矽層60,此多晶矽層60係作爲 快閃記憶體之控制閘極層之用。 請參照第9圖，使用定義多晶矽層60之相同罩幕與蝕 刻技術，繼續往下蝕刻內多晶矽介電物質57與多晶矽層 54,藉以分別形成如第9圖所示之內多晶矽介電層64與 多晶矽層62。此多晶矽層62係作爲快閃記憶體之浮置閘 極層之用。 。 接著例如使用低壓化學氣相沉積法沉積內多晶矽介電 物質65，覆蓋整個基底結構表面，包括覆蓋多晶矽層60 與62以及隧穿氧化層52。此內多晶矽介電物質65的厚度 約大於250A，例如爲氧化物/氮化物/氧化物之三層結構。 然後，例如使用低壓化學氣相沉積法在此層內多晶矽介電 物質65上形成一層多晶矽物質66。 請參照第10圖，上光阻67覆蓋部分多晶矽層66，然 後使用蝕刻法去除光阻67所曝露出來的多晶矽層66以及 多晶砍層66下方的內多晶砍介電層65，藉以分別形成多 晶矽層68以及內多晶矽介電層70,並且藉以選擇性地曝 露出隧穿氧化層52的表面。然後進行離子植入步驟，植 入摻質，例如濃度高的N型離子，於曝露出的基底50中。 此濃度高的N型離子，比如爲磷離子。而此離子植入步驟 則是例如使用一傾斜角度將摻質植入基底中。接著，進行 回火步驟，使摻質形成隧穿擴散區72。此隧穿擴散區72 例如是作爲汲極區之用，且約側向地延伸至多晶矽層62 _______ 10 本紙張尺度適用中國國家標芈（CNS ) A4規格（210X297公釐） (請先閲讀背面之注項再填寫本頁) 訂 4 41 1 〇 8 3587twf.doc/002 經濟部中央標準局員工消f合作社印製 A7 B7 五、發明説明（1 ) 下方之基底50中。 請參照第11圖’當隧穿擴散區72形成之後，則去除 光阻67。然後’另外上光阻74覆蓋隧穿擴散區72，並且 覆蓋多晶矽層60上方的部分內多晶矽介電層70。其中， 光阻74所覆蓋之區域例如是原先光阻67(第10圖）所曝露 出之區域。然後進行回蝕刻步驟，例如使用乾蝕刻法，貪虫 刻曝露出的多晶矽層68，直到約曝露出多晶矽層68下方 的內多晶矽介電層70,使得多晶矽層68形成多晶矽間隙 壁76。此多晶矽間隙壁76係位於多晶矽層60與62的側 壁上，且多晶矽間隙壁76和多晶矽層60與62之間存在 有內多晶矽介電層70。其中，兩個鄰近的多晶矽間隙壁76 之間暴露出部分的內多晶矽介電層70。 然後，以多晶矽間隙壁76爲罩幕，進行自行對準 (Self-aligned)離子植入步驟，植入摻質穿過暴露出的內多 晶矽介電層70，並進入基底50中。此離子植入步驟，例 如是植入高濃度的N型離子，比如砷離子。接著進行回火 步驟5使摻質形成離子佈植區78。因爲，離子佈植區78 中植入的是較重的離子，例如砷離子，所以較不易產生擴 散現象。此離子佈植區78例如是作爲源極區，並且與鄰 近的多晶矽層62之間具有一間距，此間距之寬度約等於 間隙壁之寬度。 請參照第12與13圖，當離子佈植區78形成之後，則 去除光阻74。然後，例如使用化學氣相沉積法在內多晶矽 介電層70與多晶矽間隙壁上形成一層金屬矽化物質，此 1---Ϊ--------身-- (請先閱讀背面之注^一^項再填寫本頁)Gi. -Order_ r-/ 41 1 〇 8 L 3 58 7 twf., Doo / 002 A7 B7 V. Description of the invention (t) Brief description of the diagram: Figure 1 shows the traditional flash memory Layout diagrams; Figures 2, 3, and 4 are cross-sectional views showing the manufacturing process of traditional flash memory, and are cross-sectional views of the manufacturing process obtained from the direction of the cross-section of Figure 1-I; Figures 5 and 6 are drawings A cross-sectional view of the manufacturing process of a conventional flash memory, and a cross-sectional view of the manufacturing process obtained from the direction of the cross-section of FIG. 1-II; FIG. 7 shows a flash memory according to a preferred embodiment of the present invention Figures 8 through 12 are cross-sectional views showing the manufacturing process of a flash memory according to a preferred embodiment of the present invention, and are cross-sections taken along the direction Π-III in Figure 7. And FIG. 13 is a cross-sectional view taken along the IV-IV direction in FIG. 7 in the manufacturing step of FIG. 12. Icon description: Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 10, 50: Substrate 12, 52: Tunneling oxide layer 14: Field oxide layer 16, 62 : Floating gate layers 18, 64, 70: Internal polycrystalline sand dielectric layers 20, 60: Control gate layers 21, 67, 74: Photoresistors 22a, 78: Source regions 22b, 72: Drain regions 24 : Tunneling Diffusion Zone 8 This paper size applies to Chinese National Standards (CNS > A4 size (21 × 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ^ 4-1 1 〇3 3B87twf.doc / 002 A7 B7 Fifth invention description () 32: contact window 34: metal layer 68: polycrystalline silicon layer 76: spacer 80: conductor layer embodiment FIG. 7 shows a flash memory according to a preferred embodiment of the present invention The layout diagrams. Figures 8 to 12 are cross-sectional views showing the manufacturing process of a flash memory according to a preferred embodiment of the present invention. Among them, Figures 8 to 2 are shown along III in Figure 7 A cross-sectional view obtained in the -III direction. And Fig. 13 is shown in the process steps of Fig. 12 and taken along the IV-IV direction in Fig. 7 A cross-sectional view. Referring to FIG. 8, a substrate 50 is provided, and then an oxide material having a thickness of about 85 A to 100 A is formed on the substrate 50 using, for example, a thermal oxidation method. Then, for example, a low pressure chemical vapor deposition method is used to oxidize this layer. A layer of polycrystalline silicon material is formed on the material, and the thickness of this layer of polycrystalline silicon material is about 1500 A. Next, the lithographic etching technology is used to define this layer of polycrystalline silicon material and this layer of oxide material to form a polycrystalline silicon layer 54 and a tunneling oxide layer 52. Among them, the polycrystalline silicon The substrate surface is exposed on both sides of the layer 54. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inner polycrystalline silicon dielectric substance 57 to cover the surface of the polycrystalline silicon layer 54. The inner polycrystalline silicon dielectric substance 57 is, for example, oxide / nitride / oxidation The material has a three-layer structure with a thickness of about 250 A. Then, for example, a low-pressure chemical vapor deposition method is used to form a layer of polycrystalline silicon material with a thickness of about 3000 A on the polycrystalline silicon dielectric material. > A4 size (210X297mm) ΓΓ._ · —rr -----— (Please read the notes on the back before filling this page) Order -r ' '-'._ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs'' 4 41 1 〇δ 3 537twf .〇〇c / 0 〇5 A7 B7_____ 5. Explanation of the invention (?) Then, use a screen and Etching technology defines a polycrystalline silicon material, thereby making the polycrystalline silicon material a polycrystalline silicon layer 60, which is used as a control gate layer of a flash memory. Please refer to FIG. 9, using the same mask and etching techniques that define the polycrystalline silicon layer 60, continue to etch the inner polycrystalline silicon dielectric substance 57 and the polycrystalline silicon layer 54 downward to form the inner polycrystalline silicon dielectric layer 64 as shown in FIG. 9, respectively. With polycrystalline silicon layer 62. The polycrystalline silicon layer 62 is used as a floating gate layer of the flash memory. . Then, for example, a low-pressure chemical vapor deposition method is used to deposit the internal polycrystalline silicon dielectric material 65, covering the entire surface of the substrate structure, including covering the polycrystalline silicon layers 60 and 62 and the tunneling oxide layer 52. Here, the thickness of the polycrystalline silicon dielectric substance 65 is greater than about 250 A, and is, for example, a three-layer structure of oxide / nitride / oxide. Then, a layer of polycrystalline silicon substance 66 is formed on the polycrystalline silicon dielectric substance 65 in this layer, for example, using a low pressure chemical vapor deposition method. Referring to FIG. 10, the upper photoresist 67 covers a part of the polycrystalline silicon layer 66, and then the polycrystalline silicon layer 66 exposed by the photoresist 67 and the inner polycrystalline dielectric layer 65 under the polycrystalline layer 66 are removed by an etching method, so as to separate A polycrystalline silicon layer 68 and an inner polycrystalline silicon dielectric layer 70 are formed, and the surface of the tunneling oxide layer 52 is selectively exposed. An ion implantation step is then performed to implant a dopant, such as a high concentration of N-type ions, into the exposed substrate 50. The N-type ion with a high concentration is, for example, a phosphorus ion. The ion implantation step is, for example, implanting a dopant into a substrate using an inclined angle. Next, a tempering step is performed to cause the dopants to form the tunnel diffusion region 72. This tunneling diffusion region 72 is used as a drain region, for example, and extends approximately laterally to the polycrystalline silicon layer 62 _______ 10 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the back first Please fill in this page for the note items) Order 4 41 1 〇8 3587twf.doc / 002 Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs and Co-operative Society A7 B7 V. Description of the invention (1) in the base 50 below. Please refer to FIG. 11 'After the tunnel diffusion region 72 is formed, the photoresist 67 is removed. Then, 'another photoresist 74 covers the tunneling diffusion region 72 and covers a portion of the polycrystalline silicon dielectric layer 70 above the polycrystalline silicon layer 60. The area covered by the photoresist 74 is, for example, the area exposed by the original photoresist 67 (FIG. 10). Then, an etch-back step is performed. For example, using a dry etching method, the exposed polycrystalline silicon layer 68 is etched until the inner polycrystalline silicon dielectric layer 70 below the polycrystalline silicon layer 68 is exposed, so that the polycrystalline silicon layer 68 forms a polycrystalline silicon spacer 76. The polycrystalline silicon spacer wall 76 is located on the side walls of the polycrystalline silicon layers 60 and 62, and there is an inner polycrystalline silicon dielectric layer 70 between the polycrystalline silicon spacer wall 76 and the polycrystalline silicon layers 60 and 62. Among them, a portion of the inner polycrystalline silicon dielectric layer 70 is exposed between two adjacent polycrystalline silicon spacers 76. Then, a self-aligned ion implantation step is performed using the polysilicon spacer wall 76 as a mask, and implanted dopants pass through the exposed inner polysilicon dielectric layer 70 and enter the substrate 50. This ion implantation step is, for example, implanting a high concentration of N-type ions, such as arsenic ions. Tempering step 5 is then performed so that the dopants form the ion implantation region 78. Because the ion implantation area 78 is implanted with heavier ions, such as arsenic ions, it is less likely to cause diffusion. The ion implantation region 78 is used as a source region, for example, and has a distance from the adjacent polycrystalline silicon layer 62. The width of the distance is approximately equal to the width of the spacer. Please refer to FIGS. 12 and 13, after the ion implantation region 78 is formed, the photoresist 74 is removed. Then, for example, a chemical vapor deposition method is used to form a layer of metal silicide on the inner polysilicon dielectric layer 70 and the polysilicon spacer. This 1 --- Ϊ -------- body-- (Please read the back (Note ^ a ^ item, then fill out this page)
本紙張尺度通用中國國家標準（CNS) A4規格（21〇><297公釐） 4 43ut9A ! / 0 0 ： 4 43ut9A ! / 0 0 ： 經濟部中央標準局員Η消費合作社印製 A7 B7 五、發明説明（fo ) 金屬矽化物質之材質例如爲矽化鎢（Tungsten siHclde ; WSi2)。然後使用微影蝕刻方式定義此層金屬矽化物質，而 形成金屬矽化物層80。此金屬矽化物層80係作爲快閃記 憶體之選擇閘極層之用，並且此金屬砂化物層80的延伸 方向約垂直於控制蘭極層。因爲多晶砂間隙壁7 6與金屬 矽化物層80都具有導電性，所以可提供良好的電性導通， 故，選擇閘極層之電阻可降爲多晶矽物質電阻的1/3至 1/4。然後，進行後續的步驟以完成快閃記憶體之製造。然 而此後續製程因爲非關本發明之特徵’所以此處不再贅 述。 在本發明中源極區是利用自行對準植入的方式，以多 晶矽間隙壁76爲罩幕，植入高濃度的N型離子而形成。 本發明是利用源極側邊注入的方式’可使記憶胞具有 較高的可程式效率與較低的存寫電流’例如約爲1〇〇至1000 微安培A)。因此，本發明之快閃記憶體不需要高操作 電壓，所以可適用於低伏特與低電源供應的操作中。此外， 源極區與汲極區的離子摻雜是分開進行，可以分別控制摻 雜的量，方便調整快閃記憶體的參數。 本發明之快閃記憶胞的特性是利用選擇閘防止不當的 滲出電流導致的過度抹除現象，以維持記憶體的正常運 作。 本發明利用離子佈植區72可作爲埋入式線之用。所以 不需在後續步驟中形成接觸窗口也不需塡入金屬層。因此 不會有金屬層反射的干擾。 本紙張尺度適用中國國家標準（CNS ) A4規格（2ί〇χ297公釐) (請先閱讀背面之注意事項再填窝本頁) •C裝. -訂· 4 4110 8 3587twf.doc/002 B7 五、發明説明U() 並且，在本發明之製程中不需形成場氧化層，因此依 據本發明之方法所獲得之快閃記憶體，具有較佳的平坦 度，並且可以大幅縮小尺寸。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中夬標準局員工消費合作社印製 本紙張尺度適用中國國家標率（CNS > A4規格（210X297公釐）The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (21〇 < 297 mm) 4 43ut9A! / 0 0: 4 43ut9A! / 0 0: Printed by A7 B7, a member of the Central Standards Bureau of the Ministry of Economic Affairs 2. Description of the Invention (fo) The material of the metal silicide is, for example, tungsten silicide (Tungsten siHclde; WSi2). The lithographic etching method is then used to define the metal silicide layer to form a metal silicide layer 80. The metal silicide layer 80 is used as the gate layer of the flash memory, and the metal sand layer 80 extends in a direction approximately perpendicular to the control blue electrode layer. Because the polycrystalline silicon spacers 76 and the metal silicide layer 80 are conductive, they can provide good electrical conduction. Therefore, the resistance of the selected gate layer can be reduced to 1/3 to 1/4 of the polycrystalline silicon material resistance. . Then, the subsequent steps are performed to complete the manufacture of the flash memory. However, since this subsequent process is not related to the features of the present invention ', it will not be repeated here. In the present invention, the source region is formed by implanting a high concentration of N-type ions by using a self-aligned implantation method, using polycrystalline silicon spacers 76 as a mask. In the present invention, the source side injection is used to make the memory cell have higher programmable efficiency and lower write and write current, for example, about 100 to 1000 microamperes A). Therefore, the flash memory of the present invention does not require a high operating voltage, so it can be used in operations with low voltage and low power supply. In addition, the ion doping in the source region and the drain region is performed separately, and the amount of doping can be controlled separately to facilitate adjusting the parameters of the flash memory. The flash memory cell of the present invention is characterized by the use of a selection gate to prevent excessive erasure caused by improper oozing current to maintain the normal operation of the memory. The present invention utilizes the ion implantation area 72 as an embedded wire. Therefore, it is not necessary to form a contact window in a subsequent step or to infiltrate a metal layer. Therefore, there is no interference from the reflection of the metal layer. This paper size applies Chinese National Standard (CNS) A4 specification (2ί〇χ297 mm) (Please read the precautions on the back before filling in this page) • C Pack.-Order · 4 4110 8 3587twf.doc / 002 B7 5 2. Description of the invention U () In addition, no field oxide layer needs to be formed in the process of the present invention, so the flash memory obtained according to the method of the present invention has better flatness and can be greatly reduced in size. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumers' Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs This paper size applies to China's national standard (CNS > A4 size (210X297 mm)