TW440980B - Package with an innovation substrate having an embedding capacitor to reduce the signal noise - Google Patents

Abstract

The package of the present invention comprises a substrate which has a grounding ring and a power ring formed on the upper surface of the substrate; a chip configured on the substrate; a golden wire used to connect the chip with the substrate; an encapsulation covering over the chip and the substrate for protecting the chip and the conductive wires; a conductor ball grid formed on the lower surface of the substrate for transmitting the signal; and, at least a capacitor to be formed on the substrate for eliminating the coupled noise. The inventive design is to only reserve the pad of de-coupled capacitor for connecting to the power ring and the grounding ring while making layout on the substrate surface.

Description

4 40 9 8 0 V. Description of the invention (l) Field of the invention: The present invention relates to a semiconductor package, especially a package having a capacitor planted on a substrate to reduce the influence of noise on electrical properties. Background of the invention: Recently, with the rapid evolution of semiconductor technology, driven by the thinness and lightness of electronic products, the number of I / Os of 1C semiconductors is not only increasing, but also increasing in density, resulting in the number of pins of package components. More and more, the speed requirements are getting faster and faster. Generally, semiconductor wafers need a structure to prevent damage caused by moisture and external forces. This technology is related to packaging technology. There are more and more pins in the package. One of the important considerations in making small, high-speed and extremely high-density components is to make a package with good heat dissipation. —A conventional semiconductor package includes a substrate and a wafer, and the wafer is adhered to the substrate by silver glue or other materials. The electrical signals of the chip are transmitted to the substrate through gold wires. Ball matrix array packaging technology (b a 1 1 g r i d arr ay; hereinafter referred to as bga packaging) such as solder balls (so 1 der bump) is disposed on the bottom surface of the substrate. A molding compound covers the surface of the substrate and the wafer to prevent the wafer and gold wires from being impacted by external forces or the influence of moisture. However, due to the continuous increase in the accumulation level and the speed of signal transmission, the rapid and effective transmission of heat and signals has become an important issue. However, the use of traditional wireframe packaging has its limitations.

5. Description of the invention on page 4 (2) At present, a variety of packaging structures have been proposed. One of them can refer to U.S. Patent No. 5629835. The structure proposed by Mahulikar et al. Is entitled "METAL BALL GRID" ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY " ° IC semiconductor packages tend to use ball grid array packaging technology (hereinafter referred to as BGA packaging). The characteristics of BGA structure is that the pins responsible for I / O are spherical. The slender pin distance of the lead-frame components is short, and the electrical transmission distance of the packaged components is short and fast, which can meet the needs of future speeds. It can easily increase the number of pins and has a large enough distance to make the group farmers more Easy, can also meet the needs of high pin count in the future. However, the current BGA uses gold wires to connect day to day, but often due to unstable voltage and 4m such seals: 7 衮 Noise interference affects electrical characteristics The characteristics of this piece. Elegant condition + conductor seal to promote the integration of the previous discussion and use this book to solve a new semiconductor package structure. The invention will be used to solve the problems mentioned above. Purpose and summary of the invention: The main purpose of the invention is to propose a seal to prevent noise interference from vehicles. 5. Description of the invention (3) The package of the invention includes a substrate. The substrate has a grounding ring and a power supply ring formed on the upper surface of the substrate. A wafer device is formed on the substrate. Gold wires are used to connect the wafer and the substrate. The sealant covers the wafer and the substrate and a power ring is formed. On the upper surface of the substrate, a gold wire is used to connect to protect the lower surface of the wafer for transmission beyond the domain and is located on the ring and a power ring board of the present invention, and the gold wire is used to protect it. A conductive ball array is formed on the lower surface of the substrate to eliminate coupling impurities and to protect the chip and conductive connections. The conductive ball array is formed on the lower surface of the substrate to transmit signals and at least one capacitor is formed in the area where the gold wire is made and located in the area. The sealing compound is used to eliminate the coupling noise. Another embodiment of the present invention includes a substrate, the substrate has a ground loop to connect the chip and the substrate, the sealing compound and the conductive connection. The transmission signal and at least one capacitor sealant are also eliminated-the embodiment includes a substrate formed on the upper surface of the substrate to connect the wafer and the substrate, the sealing sheet and the conductive connection, and to conduct the signal and at least one telecommunication. The substrate covers the wafer and the ball array of the substrate is formed on the substrate and formed in the area where the gold wire is made. The substrate has a ground. A wafer device is formed by the base glue covering the wafer and the substrate body ball array. The substrate capacity is formed outside of Fengsheng. It is simply explained with the diagram:

440980 V. Description of the invention ¢ 4) Figures A and B are top views of the embodiment of the present invention. FIG. 2 is a wearing view of a second embodiment of the present invention. FIG. 3 is a wearing view of a third embodiment of the present invention. Symbol component comparison table: 'Package 1 0 substrate 1 2 chip 1 4 gold wire 1 6 conductor ball 1 8 ground ring 2 0 power ring 2 2 pin 24 capacitor 26 insulation package 2 8 Detailed description of the invention: First embodiment: The present invention discloses a semiconductor package with improved electrical characteristics. The package of the present invention has a capacitor for eliminating coupling noise. Examples of the present invention are shown in Figs. First, refer to FIG. 1, which is a cross-sectional view of a first embodiment of the present invention. This package 10 includes a substrate 12, a semiconductor wafer 14 is assembled on the substrate 12, and the wafer 14 is between the substrate 14 and the substrate 12. Fix with wafer bonding material (such as silver glue). The substrates 1 and 2 include many conductive channels.

440980 V. Description of the invention (5) In order to transmit signals, the material of the substrate 12 can be selected from polyimide, phenolic resin, FR4, FR5 or βΤ. The material of the conductive channel can be gold, steel or alloy. The electrical connection between the chip 14 and the substrate 丨 2 mainly uses a plurality of conductive wires, such as a gold wire 丨 6 is soldered on the chip 丨 4, and the conductor ball 18 is used for signal transmission. According to an embodiment, it can be Use a solder ball. The conductive ball array forms conductive balls on the lower surface of the substrate 12 using a conventional ball-planting technique.

Fig. 1A and Fig. 1B are top views of the substrate of the present invention. The substrate 12 has a postal placement area 14a, a ground ring 20 and a power ring 22 surrounding it. The power ring 22 supplies the power required for the operation of the components. There are a lot of conductive pins 24 around it, and Jing Jingchuan and the substrate 12 are covered with insulating packages 28. During the operation of the components, they can be distributed and arranged to reduce their quality. D or signal cables The problem of coupling is at least connected to the decoupling characteristics between the power ring 2 2 and the ground ring 20. For the place of production. According to the electrical properties of the power supply ring, the ground source ring, and the signal wire piece of the present invention, the upper surface is resolved due to the instability of the voltage. The capacitor power ring 22 needs to be reserved when connected to the surface of the component substrate. The characteristics of two percent avoidance and material characteristics, for example, are affected by the combination of _ components-capacitor 26 is connected to the ground ring 2 0. Capacitor 26 can be described as capacitor 26, and the design is only required to decouple the supply and install the ring, and the characteristic ring. Into the base. Decoupling needs to be connected to the capacitors of the substrate, such as electrical interference. It can be formed on the board due to the supply board 12 and the contact pads can be placed on the surface wiring pads.

440980 V. Description of the invention (6) The ground ring 20 is electrically connected to it. The above-mentioned electric circuit 26 is located under the conductive connection (gold wire) 26 in the area where the conductive connection is made. Because of the limitation of the geometric structure or too many arc layers of the wire, 'to consider that placing a capacitor between the power ring 22 and the ground ring 20 causes the line arc to be too high', the power ring 22 and the ground ring 20 can be used. The circuit layout or using a multi-layer substrate to connect to the periphery or corner of the substrate is shown in FIG. 1B or other embodiments. Second Embodiment: FIG. 2 shows a cross-sectional view of a second embodiment of the present invention. The structure also includes a substrate 12, a wafer 14, and a conductive connection (gold wire). The conductive connection 16 is connected to the conductive structure via a conductive structure. Conductor balls 18 arranged in a matrix of balls on the bottom surface of the substrate. Of course, this package contains at least one capacitor 26. The connection between the capacitor and the power supply terminal and the ground is achieved by wiring layout or using a multilayer substrate, so that the capacitor placement pad is formed outside the gold wire formation area. Three embodiments: The embodiments of other transformations are the same as the examples, so the same corpse and essential components are placed outside the sealing gel with the above 26. Private number. In this example, the decoupling capacitor is mainly used. At present, the present invention forms a sealed dream. Welding is performed on the substrate first, and then: the sequence is the same as the traditional technology. Steps for joining gold wires and sealing glue. The present invention is described above with reference to the preferred embodiments, and is familiar with the art in this field.

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Claims (1)

4 40 9 8 0 6. Patent application scope 袈 1, a semiconductor package with a capacitor planted on a substrate, the semiconductor includes: a substrate having a ground ring and a power ring formed on the upper surface of the substrate; A chip is mounted on the substrate; a conductive connection is used to connect the chip and the substrate; a repair is covered on the wafer and the substrate to protect the chip and the conductive connection; a ball array, Formed on the lower surface of the substrate for transmitting signals; and < -capacitors, formed in the region where the conductive connection is made and within the 'ten glue, for eliminating coupling noise. 2 Seal the semiconductor with a capacitor planted on the substrate as described in item 1 of the scope of patent application, where the above-mentioned conductive connection is a gold wire. 3: The semiconductor package t, which has a capacitor planted on the substrate in the first item of the scope of the α patent application, the above-mentioned capacitor is formed between the ground ring and the power supply ring. : ° The semiconductor package f, ^ 'with a capacitor planted on a substrate in the first patent application range has a contact pad for bonding the capacitor. In the first item of the patent application No. 5, the semiconductor i'j having a capacitor planted on a substrate, wherein the above-mentioned conductor ball array is a solder ball. Page 11 VI. Application Patent Scope 6. —A semiconductor package having a capacitor planted on a substrate, the semiconductor package includes: a substrate 'the substrate has a ground ring and a power ring is formed on the upper surface of the substrate; a wafer, Pei is placed on the substrate; a conductive connection is used to connect the chip and the substrate; Feng Sheng is covered on the wafer and the substrate to protect the chip and the conductive connection; a conductive ball array is formed on The lower surface of the substrate is used to transmit signals; and at least one capacitor is formed outside the area where the conductive connection is made and inside the sealant 'to eliminate coupling noise. 7 The semiconductor package with a capacitor planted on a substrate according to item 6 of the Shengu patent scope, wherein the above-mentioned conductive connection is a gold wire. The semiconductor having a capacitor planted on a substrate according to the sixth item of the scope of interest, the eight capacitors are respectively connected to the ground ring and the power ring. A semiconductor having a capacitor planted on a substrate in the sixth item of the 9-millimeter range " ', the above substrate has a contact pad is called bonding the capacitor. Scope of patent application on page 12 '11. A semiconductor package having a capacitor planted on a substrate, the body package comprising: a power source ring formed on a substrate, the substrate having a ground ring and an upper surface; A chip is mounted on the substrate; a conductive connection is used to connect the chip to the substrate; a sealing kick is covered on the chip and the substrate to protect the chip and the conductive connection; a conductor ball barrier column, Formed on the lower surface of the substrate at least…, formed outside the sealant to eliminate; news and 1 2 _ If a semiconductor package with a capacitor planted on the substrate as described in the patent application item 丨 丨, wherein the above The conductive connection is gold. 1 3. If the semiconductor with a capacitor planted on the substrate is cracked according to item 11 of the scope of the patent application, wherein the above capacitors are respectively connected to the ground ring and the power supply ring. 14. A semiconductor package having a capacitor planted on a substrate according to item 11 of the scope of patent application, wherein said substrate has contact pads for bonding the capacitor. 1 5. If applied, please apply for semiconductor package with capacitor planted on the substrate according to item 11 of the patent, where the above-mentioned array of conductor balls are solder balls. Page 13