TW440911B - Method for breaking the geometrical limitation in the semiconductor photolithography process - Google Patents

Abstract

The present invention discloses a method for breaking the geometry limitation in the semiconductor photolithography process. In the process for manufacturing semiconductor devices, a process for etching the sidewall is additionally provided after the photolithography and etching step and before peeling off the photoresist. Therefore, the spacing or line width between adjacent devices can be reduced, such that the geometrical dimension of the device can further break the limitation of the photolithography process. The present invention is characterized in being compatible with the existing semiconductor process, so as not to add manufacturing difficulties, influence the yield and increase too much additional manufacturing cost.

Description

V. Description of the Invention (1) Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, which breaks through the lithography process and limits the size of the semiconductor device.彳 是 心 能 Background of the invention The so-called lithography technology is to convert a large number of electronic parts (patterns) to a tiny crystal layer by layer. As the density of integrated circuits continues to increase, in order to make a the same, or even to reduce, the unit of integrated circuits is continuously reduced. The solution of z product protection = is to continuously reduce the circuit design specifications (D: the only ^ ^ es1gn Ku 1 e ) * Lithography technology is the biggest bottleneck encountered when scaling down. Taking the first picture as an example, it shows two adjacent capacitors B on the dynamic random access memory (DR AM). The limitation of the above-mentioned lithography technology on the geometric size of the capacitors A and B lies between the two. The distance d 'is mainly limited to the minimum feature size that can be exposed by the lithography technology. The capacitance value of the valley is directly proportional to its area. One of the methods to make semiconductor capacitors obtain larger capacitance values is It is to increase the area of the capacitor electrode layer. However, because the distance between the semiconductor capacitor and the adjacent components is limited by the lithographic process, it cannot be further reduced, which means that the restrictions on the length and width of the electrode layer of the semiconductor capacitor are based on the lithography technology at the time. Therefore, in the conventional technology, the area of the semiconductor capacitor electrode layer is defined according to the lithography process. In this given size, a method is used to increase the surface area of the capacitor electrode layer to increase the capacitance value, such as the formation of a coarsely complex polycrystalline stone (rugged ρ ο 1 ysi 1 ic ο η)

Page 4 d409 1 1 V. Description of the invention (2) The surface of the electrode layer is micro-roughened to enlarge the surface area of the capacitor electrode layer. Another example is U.S. Patent Nos. 5843822 and No. 59096 21, which respectively propose methods for increasing the area of the electrode layer. The technical content of the two patents makes the side of the capacitor electrode layer wavy by the difference in the etching ratio between the materials. 'Thereby increasing the area of the surface of the capacitor electrode layer. However, the above-mentioned method is too complicated in practical application, which is undesired in the semiconductor manufacturing process; and these conventional technologies still cannot fundamentally increase the size of components or reduce the size between components. Therefore, it is necessary to propose a better improvement plan for perfection. The purpose of the invention and the invention can break through the size or reduce the invention, can break through the width and width between elements, increase the method of the invention, and the method of the invention can be based on the surface area. The present invention outlines a method for manufacturing a semiconductor device, and the geometric limit of the manufacturing process increases the size of the device. A method of manufacturing a semiconductor capacitor is proposed to reduce the length of the electrode layer of the semiconductor capacitor and the adjacent locally extended semiconductor capacitor. The area of the capacitor electrode layer is reduced. The company is also proposing a process for manufacturing semiconductor capacitors, which achieves the main purpose of increasing the electrode layer of semiconductor capacitors. The current lithography interval between the existing lithography components is the second, and the semiconductor lithography is simpler. Another purpose is to propose a method for reducing the width of a semiconductor circuit.

Page 5 V. Description of the invention (3) Inch method, according to the present invention, a limit method is based on steps such as semiconducting, after stripping the light sequence, so reducing the size of adjacent elements to further break through the micro or shrink The invention of the rule between elements is applied to increase the effect that a gate conductor rule can achieve. The feature of the present invention is that only one additional etching is added to affect the yield, or the size is increased or the circuit design between components is reduced, which is a breakthrough in the process of the shadow process between the components. In the case of the substrate capacitance, and the first step is to reduce the size of the β size outside the cheek. In the geometric process of the lithography process in the conductor process, the lithography and etching field is added to increase the distance or line width of the etched sidewall to make the geometrical limitation of the element 'fundamentally increase the size of the element. In several embodiments, according to this The area 'reduced line width or the gate conductor's computer simulation chart shows that the foundry's semiconductor process is compatible, but it does not increase the difficulty and cost of the process technology', which can increase the component diagrams briefly. With the accompanying drawings, the present invention, from the following detailed description and other purposes and advantages will be able to be more clearly understood, the above-mentioned first picture shows the dynamic response and is more obvious. Among them: The distance between capacitors indicates that micro = two adjacent capacitors in the memory, which are limited by these two. For the manufacturing process of the semiconductor device, the t process is a geometric second circle to a second circle. The figure describes the manufacturing method according to the present invention, and the manufacturing process of an embodiment of the present invention to scare + conductor capacitance.

5. Description of the invention (4) The third figure shows the effect achieved by increasing the surface area of the electrode layer of a semiconductor capacitor according to the present invention. Figures 4a to 4d show schematic diagrams of the flow of manufacturing a gate conductor according to the present invention. Figs. 5a to 5d show another embodiment according to the present invention. Description of drawing number: 10 silicon substrate 102 isolation 12 insulation layer 12 silicon oxide layer 13 silicon nitride layer 14 word line 16 bit line 18 plug 20 insulation layer 22 photoresist 25 groove 25 'groove 26 conductor layer 27 concave Slot 27 'groove 30 gate oxide layer 322 doped polycrystalline silicon layer 324 tungsten silicide layer 326 silicon nitride layer 34 photoresist 36 gate conductor 40 substrate 42 structural layer 44 Capacitance is to fundamentally reduce the distance between the semiconductor capacitor and adjacent elements, extend the size of the semiconductor capacitor electrode layer, and further increase the surface area of the capacitor electrode layer. The second a to the first

V. Description of the invention (5) The figure shows the process of making dynamic random access content according to the present invention. First, as shown in Figure 3, Yu Zhen substrate 2 $ Li 102, and then a character line (Mt 丨 丨

Uyd Ilne). Then sequentially deposit J 1 3 ^ ^ ^ 2〇, ^ ^ ^ ^ (plug) After completing the plug 18, in the nitride stone 々 〖q main fee 205 9 04 ^ m Xi layer 13 surface Cover an insulating layer with a photoresist 22 on the surface of the insulating layer 20. However, a photomask C is placed on the top for the lithography process, and the rust f is particularly obstructive ^ The pattern on yc is transferred to = 22 through: = light ^ :: system. Next, the touch-etching process is performed according to the pattern of the photoresist 22. J: Dry-etching is used to pattern the insulating layer 20 into the grooves ^ and 27 without photoresist. Among them, the gasification stone layer 13 is a stop layer for the remaining time. , That is, the state shown in Figure -c. Ming amount! When t f reaches 1 here, the photoresist 22 is peeled off. According to the present invention, a step of etching the sidewall is added in the field. Before the photoresist 22 is peeled off, the side walls of the grooves 25 and f are etched to expand to the side, and the state shown in FIG. By sculpting the side walls of the grooves 25 and 27, the distance between the grooves 25 and 27, = the distance d is further reduced to d, and the sides of the sides of the grooves 25 and 27 are expanded to make their length and width Enlarged fundamentally to form groove 25, = groove 27 '. Among them, the preferred one is to use wet etching to etch the sidewalls of the grooves 25 and 27. Chemical solution used for wet etching 糸 Depends on the material of the insulating layer 20, for example, the insulating layer 20 is silicon dioxide

Page 8 440 9 t 1 V. Description of the invention (6) (Si02), you can use Hydrofluoric Acid. Generally speaking, the erosion rate of hydrofluoric acid to silicon dioxide is quite high, which is not easy to control in the process. Therefore, in practical applications, diluted hydrofluoric acid solution is used, or a buffering agent (such as fluorine A mixed solution of ammonium chloride (NH4F)) is used to perform silicon dioxide etching. The purpose of adding a buffer is to supplement the consumption of fluoride ions in the solution due to the etching reaction in order to maintain a stable etching rate. And through proper control of various process conditions of wet etching, such as solution concentration, reaction temperature and reaction time, the rate of wet etching can be controlled. Next, the photoresist 2 2 is removed, and then a conductive layer 26 is filled to fill the grooves 2 5 ′ and 2 7 ′, and becomes the state shown in the second figure e. After undergoing a planarization process (Planarization), it becomes the second In the state shown in figure f, the lower electrode layer structure of two adjacent semiconductor capacitors is thus formed. The subsequent process is to fabricate the upper electrode layer of the capacitor above the lower electrode layer of the capacitor. This is well known to those skilled in the field of semiconductor capacitor manufacturing and will not be described in detail here. In the above process, the sidewalls of the etched grooves 25 and 27 can break through the geometric size limitation d of the lithography process, so that the distance d between the grooves 25 and 27 is further reduced to d ', thereby making the grooves The sizes of 2 5 and 27 are enlarged. The surface area of the capacitor electrode layer obtained after the enlarged grooves 2 5 ′ and 2 7 ′ obtained by subsequent processes can be increased as compared with conventional techniques. For other embodiments, making a capacitor according to the present invention should be understood as adding a step of etching the sidewall before removing the photoresist. I reduces the distance between the capacitor electrode layer and the adjacent element (not necessarily the capacitor). The area of the layers has increased radically.

Page 9 1 4 0 9 1 1 V. Description of the invention 的 The ratio of the sidewall of the etched groove to the increase in the surface area of the capacitor electrode layer can be represented by the simulation results in the figure. It is assumed that the original length of the groove 2 5 is 3L, Ά, the degree is 1L, the depth is H < > In the chart of the third figure, the horizontal axis represents the percentage of increase in length and width of the semiconductor capacitor electrode layer J, which is the ratio of the distance of the side wall extension of the groove 2E i 'to the width L. The axis is the percentage increase in the surface area of the semiconductor capacitor, where the surface area of the semiconductor capacitor refers to the sum of the areas of the lower electrode layer of the semiconductor capacitor other than its bottom surface. The lithography process limits the geometric size of the capacitor and the adjacent components by reducing the distance between the semiconductor capacitor electrode layer and the adjacent components. The pitch extends the width and length of the semiconductor capacitor electrode layer to increase the surface area of the semiconductor capacitor electrode layer. 0 Compared to the conventional semiconductor capacitor manufacturing process, the present invention only increases the process of engraving the side wall and is therefore compatible with the past semiconductor capacitor manufacturing process. 0 In the process of ik engraving, the effect of pre-cleaning the groove surface before the conductive layer 26 is deposited can be achieved together. It is particularly noteworthy that the present invention applies the engraving technology to make a semiconductor capacitor electrode layer. The expansion of the side wall of the groove to the side is different from pre-cleaning the groove in the conventional technology. D Pre-cleaning in the conventional technology is to remove the particles on the surface of the groove (part) .C) e) or other Surface attachments? To facilitate the deposition of conductor layers to make semiconductor capacitors, this step can only consume insulation The thickness of the layer is about 50 angstroms, and the application of the wet type engraving method in the present invention is to etch the side wall of the groove to expand the side wall to the side so as to reduce the distance between the groove and the adjacent element, increase the geometry of the groove, and make the semiconductor capacitor electrode layer. The table

Page ί 5. Fifth, description of the invention (8) 'Increase the area' It is only in the process of etching the side wall that the pre-cleaning effect can be obtained together. In terms of a 0.25 micron process, the present invention reduces the distance between the two capacitors to 0.1 micron. The above description uses the fabrication of a semiconductor capacitor as an example to illustrate the characteristics of the present invention. However, the technical idea of the present invention should be understood as the use of etching technology in photoresist stripping to further break through the geometric size limit G of the existing lithography process. The fourth figure shows a process of manufacturing a semiconductor process according to the present invention, in which a doped-poly layer 322 is sequentially formed on a gate oxide M in sequence, A silicon silicide (WSix) layer 324 and a silicon nitride (SiN) layer 326. The silicon nitride layer is covered with a layer of photoresist 34, and then according to the photolithography process of the gate conductor to be produced, after development, the photoresist 24 becomes the case shown in Figure 4 and 3. The width W of the resist 34 is photolithography. Restrictions on the geometrical dimensions of the manufacturing process. Next, the pattern of the resist 34 is etched to the nitride nitride layer 326 to obtain the shape shown in the fourth b. The process proceeds here to 'remove the resist 34, so its fabrication: the size of the conductor is mainly limited by the micro The geometric limit of the shadow process, that is, the size W of the photoresist 24. According to the present invention, before the photoresist 24 is removed, the sidewalls of the silicon nitride layer 3 2 6 are further etched, so that the width of the silicon nitride layer 326 is further reduced to become the silicon nitride layer 3 shown in FIG. 4c. 26. The better one is wet etching of the sidewall of the silicon nitride layer 32'6 with phosphoric acid (H3P04) at 140 degrees Celsius. After the sidewall of the silicon nitride layer 326 is etched, its width w is smaller than the width W of the original silicon nitride layer 3 2 6. Finally, the silicon nitride layer 3 2 6 is used as a mask 'to etch the complex crystal doped with the tungsten silicide layer 3 2 4 which is not covered by the silicon nitride layer 326; the layer 3 2 2' is obtained Gate conductor shown in Figure 4

Page 11 5'Invention description (9) 3 6, wherein the size of the gate conductor 36 is based on the size W of the silicon nitride layer 3 2 6 ', in other words, the gate conductor can be manufactured according to the present invention, and its geometric size can be broken Limits of the lithography process. A similar process can be used to make wires. Based on the development of highly integrated semiconductor devices, it is an inevitable trend to reduce components, reduce the spacing between components, and reduce line width. These necks have been limited by the minimum geometric size of the lithography process. However, the more advanced the lithography process is, the new equipment will inevitably be introduced, and the process technology becomes more complicated and difficult. The lower the yield rate and the higher the cost. According to the present invention, the circuit design specifications can be further reduced with a more mature or existing lithography process. The advantage of this is that the more mature lithography technology is applied, the yield is higher, and it does not add too much extra. Cost, and the effect can be comparable to advanced lithography process. Furthermore, with the continuous development of the lithography process, the limitations of the existing lithography technology can be broken through with the present invention, the semiconductor size can be optimized, and the circuit design specifications can be further reduced. The embodiments described above use photoresist as a mask in the semiconductor process for lithography and etching processes. In other different applications, the mask may use other materials, such as the aforementioned silicon nitride. Taking the fifth figure as an example, a structural layer 42 is formed on the substrate 40. The structural layer 42 is mainly used for making components. The mask 44 on the surface is obtained after a photolithography process and an etching process by a photoresist. pattern. Next, the structural layer 42 underneath is engraved by the surname of the mask 44 and becomes the state shown in Fig. 5b. Before the mask 4 4 is removed, the sidewalls of the structural layer 42 are etched to narrow the size, so the result shown in Figure 5c is obtained. After the mask 4 4 is removed, it becomes the fifth figure d.

Page 12 4 40 91 1 V. State of the invention description (ίο).

From the idea that the structure that is tied to the cover can be photoresistor-layer or polymetallic silicidation for the above purposes, the teachings or examples of various implementations of the technically disclosed peel-off sidewalls, or the covered junctions Layers of dielectrics, polycrystals are not intended to limit the present invention. From the present invention, for the purpose of illustration, the mask on which the idea is used to attempt to rely on the components, j is better to use = ^ qianwei v. Wet type Etching. ^ Materials, such as nitride nitride or oxygen Ϊ 2 砚, depending on the components made at the time, semiconductor or conductive material stone (Polysi 1 icon). The description of the preferred embodiment of the present invention is made by modifying the embodiment of the form precisely disclosed by the present invention or ^ the principle of the present invention and the practice of poor inventions are selected ^ from the following patent application scope and # The main technique is to engrav the mask on the mask to convert silicon, and 'possibly it is, for example, a metal, it is 闉 mingzhi'. Based on the above, it is possible for the technicians to decide by narration and equalization of the hair.

Claims (1)

6. Scope of Patent Application 1. A method for manufacturing a semiconductor capacitor, including the following steps: coating a layer of photoresist on the surface of an insulating layer; performing a lithography process to remove a portion of the photoresist; etching in the first etching process without being covered by the photoresist Forming a groove in the insulating layer > etching the sidewall of the groove in a second etching process; and continuing the process of the semiconductor capacitor. 2. The method according to item 1 of the scope of patent application, wherein the first etching process is dry etching. 3. The method according to item 1 of the scope of patent application, wherein the second etching process is wet etching. 4. The method according to item 3 of the scope of patent application, wherein the wet etching is an argon fluoride acid solution. 5. A method for manufacturing a semiconductor device, including the following steps: covering a surface of a conductor layer with a cover layer; covering a surface of the cover layer with a layer of photoresist; performing a lithography process to remove part of the photoresist; A mask layer covered by a photoresist; etching a sidewall of the mask layer; removing the photoresist; and etching a conductor layer not covered by the mask layer. 6. The method according to item 5 of the scope of patent application, wherein the side walls of the mask layer are etched by wet etching. 7. The method according to item 6 of the scope of patent application, wherein the wet etching is Page 15 440911 6. Scope of patent application Use phosphoric acid solution. 8. The method according to item 5 of the scope of patent application, wherein the mask layer is silicon nitride. 9. A method of breaking the geometrical limit of the lithography process in a semiconductor process' includes the following steps: forming a patterned mask on a surface of a structural layer; etching a portion of the structural layer not covered by the mask; and etching the structure Side walls of the layer. 10. The method according to item 9 of the scope of patent application, wherein the sidewalls of the structural layer are etched by wet etching. Π. The method according to item 9 of the scope of patent application, wherein the cover layer is nitrogen | il2. The method according to item 9 of the scope of patent application, wherein the mask layer is silicon oxide silicon. 1 3. The method according to item 9 of the scope of patent application, wherein the structural layer is composed of one or more dielectric layers, semiconductors or conductive materials. 14. The method according to item 13 of the scope of the patent application, wherein the conductor material is composed of at least one of a metal, a metal petrified compound or a polycrystalline petrified compound. Page 16