經濟部中央榡準局員工消費合作杜印製 α 3 f 3 2 G .：- 3589twf,d〇c/002 A7 B7 五、發明説明（I ) 本發明是有關於一種記憶體之製造方法，且特別是有 關於一種快閃記憶體(Flash Mem〇ry)之製造方法。 電氣抹除式可編程唯讀記憶體(EEPROM)是個人電腦和 電子設備所廣泛採用的記憶體元件。最早傳統的EEPROM 記憶單元係以浮置閘（Floating_Gate)電晶體結構來完成’其 具有珂寫入、可抹除、以及斷電後仍可保存數據的優點。 但也有面積太大及存取速度較慢的缺點’典型約在150ns 到200ns之間。近年來已開發出存取速度較快的Flash'其 存取速度約在7〇ns到80ns之間’美國Iinel公司稱之爲快 閃記憶體·+; 傳統快閃記億體之電晶體記憶單元之工作原理係利用 熱電子儲存數據及Fowler-Nordhdm隧穿效應（Tunneling Effect)抹除數據。即當儲存數據資料時，在汲極區和源極 區間加-.·約8V高電壓，且在控制閘極層同樣加一高電壓， 使熱電子（Hm Electrons)從源極區流出後，在靠近汲極區附 近穿過隧穿氧化層，注入並陷於浮置閘極層內，也就是習 知汲極側邊注入（Drain Side. Injection)的方式。提高了此浮 置閘電晶體的臨限電壓(Threshold Voltage)，達到儲存數據 資料的目的。當要抹除記憶資料時，在源極區施以正電壓 並同時在控制閘極層施以適當的負電壓，使陷於浮置閘極 層內的電f，再度隧穿過隧穿氧化層而脫離出來，使記憶 資料淸除’該浮置閘電晶體回復資料儲存前的狀態。 第1圖係繪示傳統快閃記憶體之佈局（Lay Out)圖。第 2、3與4圖係繪示從第]圖M剖面方向所得之製造流程 ( CNS ) A4^ ( 2)0^297^ ) ---------^-------IT------^ (-請先閲讀背面之注音項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 3 5 8 9 twf . doc / Ο Ο 2 4， A7 B7 五、發明説明（>) 剖面圖，而第5與6圖係繪示從第1圖II-II剖面方向所得 之製造流程剖面圖。此習知快閃記憶體之製造方法則如下 所述。 請同時參照第2與5圖，首先，提供一基底10，接著 例如使用熱氧化法在此基底丨〇上形成一墊氧化層（未顯 示）。然後例如使用區域氧化法在基底10卜.形成場氧化層 14(Field Oxide Layer)以定義出元件區（Active Area)。然後， 例如使用濕蝕刻法淸除墊氧化層。接著，例如使用熱氧化 法，使元件區的表靣形成一層隧穿氧化層12,厚度爲100A。 然後例如使用低壓化學氣相沉積法在此隧穿氧化層12 1: 形成一層厚度爲1500A的多晶矽物質。然後利用微影蝕刻 技術定義多晶砂物質，以形成多晶砂層16 1多晶砂層16 係作爲快閃記憶體之浮置閘極層之用。 接著例如使用低壓化學氣相沉積法沉積一層內多晶矽 介電物質（Inter-poly Dielectric layer)覆蓋多晶砂層16°此 內多晶矽介電物質的厚度約爲250A，而材質爲氧化物/氮 化物/氧化物（Oxide/Nitnde/Oxide)三層結構。然後’使用低 壓化學氣相沉積法在此內多晶矽介電物質上形成另一層多 晶矽物質，此層多晶矽物質的厚度爲3000A。接著，利用 微影蝕刻技術定義此層多晶矽物質並往下蝕刻內多晶矽介 電物質，藉以形成多晶矽層20與內多晶矽介電層18。其 中，多晶砂層20係作爲快閃記憶體之控制聞極層之用。 然後，利用微影触刻技術並且以多晶政層20爲罩幕， 進行飩刻步驟，進一步定義多晶砍層丨6，直至約暴露出基 _4_____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------1------1T------,^ (-請先閲讀背面之注意事項再填寫本頁) 梢 439282 3589twf.doc/002 Β7 經濟部令央標準局員工消費合作社印製 五、發明説明（ί ) 底】0表面。至此，多晶矽層20、內多晶矽介電層18、多 晶矽層16與隧穿氧化層Π組成快閃記憶體之閘極電極. 接著，使用光阻2]定義此半導體基底，暴露出閘極 電極其中一側的基底10。並且使用離子植入法，以一傾斜 角度將高濃度的磷離子，植入於暴露出的基底10中，並 進行回火步驟，而形成隧穿擴散區24。此隧穿擴散區24 係延伸至閘極電極下方。 請參照第3圖，當形成隧穿擴散區24之後則移除光阻 21。並使用離子植入法，以多晶矽層20爲罩幕進行離子 植入步驟，植入高濃度的砷離子於基底10中，藉以形成 源極區22a與汲極區22b。其中，隧穿擴散區24包圍住源 極區2 2 a。 請同時參照第4與6圖，然後使用低壓化學氣相沉積 法沉積一層介電層30覆蓋整個基底結構。並且使用微影 蝕刻技術在介電層30上形成接觸窗口 32，此接觸窗口 32 暴露出汲極區22b。並且使用低壓化學氣相沉積法沉積一 層金屬層34，於接觸窗口 32中，且接觸汲極區22b。其 中，金屬層34係作爲位元線之用。然後進行後續的製程 以完成快閃記憶體之製造3然而’此後續製程爲熟習此技 藝者所能輕易達成，故此處不再贅述。 此習知快閃記憶體是使用熱電子進行編程（Pr〇gram)的 步驟，而且是利用汲極側邊注入的方式，所以需要較高電 壓(8V)以提供較高的電流。此種習知快閃記憶體在抹除操 作時常會造成過抹除(〇ver-erase)的現象。 ----------装------1Τ------,#. (請先閲讀背面之注意事項 .k寫本頁) 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 3589twf . doc/ 002 A7 B7 五、發明説明（十） 此外，此習知快閃記憶體受限於接觸窗口 32之尺寸， 因此無法有突破性的縮小化u並且因爲形成有場氧化層 14，所以縮小幅度有限，且平坦度不佳。再者，因爲接觸 窗门中需塡入金屬層以作爲位元線之用，因此無法避免金 屬層反射的千擾。 因此本發明的主要目的就是在提供一種快閃記憶體之 製造方法，用以改善習知快閃記憶體的缺點。 根據本發明的目的，提出一種快閃記憶體之製造方法，’ 包括下列步驟：形成堆疊且已定義之第一多晶矽層與氧化 層於基底上= 依序形成第-介電層與第二多晶矽層覆蓋該第一多晶 石夕層=例如使用微影餓刻法定義第一多晶砂層’並進一步 往下定義第一多晶矽層，此第二多晶矽層位於第一多晶矽 層上，且該第二多晶矽層具有--第--延伸方向，其中第二 多晶砂層之兩側約暴露出基底。形成一第一離子佈植區， 例如磷離子佈植區，於第二多晶矽層其中一側下方之基底 中。此磷離子佈植區可作爲汲極區之用。形成第二離子佈 植區，例如砷離子佈植區，於第二多晶矽層之其中另一側 下方之基底中。此砷離子佈植區可作爲源極區之用’並& 以-間距距離該第-多晶矽層= 依序形成_·第二介電層覆蓋整個基底結構’以及形成 已定義之第二多晶矽層覆蓋第二介電層’此第三多晶矽層 具有一第二延伸方向。其中，第一延伸方向與第二延伸方 向約互相垂直。 本紙張尺度適用中國國家標準（CMS > A4規格（2Ι〇Χ2ί7公釐） ----------^------1Τ------0 (請先聞讀背面之注意事項 f寫本頁) 3589twf .doc/002 A7 3589twf .doc/002 A7 經濟部中央標準局員工消費合作社印製 五、發明説明（ζ ) 本發明造利用源極側邊注入（Source Side Injection)的 方式，可使記憶胞具有較高的可程式效率與較低的存寫電 流（Write Current)，例如約爲1〇〇至1〇〇〇微安培（v A)。因 此，本發明之快閃記憶體不需要高操作電壓，所以可適用 於低伏特與低電源供應的操作中。此外，源極區與汲極區 的離子摻雜是分開進行，可以分別控制摻雜的量，方便調 整快閃記憶體的參數。 · 本發明之快閃記憶胞的特性是利用選擇閘防止不當的 滲出電流導致的過度抹除(Over-Erasing)現象，以維持記憶 體的正常運作。 本發明利用離子佈植區係作爲埋入式線(Buried line)之 用所以不需在後繪步驟中形成接觸窗口也不需塡入金屬 層。因此不會有金屬層反射的干擾。 並a，在本發明之製程中不需形成場氧化層，因此依 據本發明之方法所獲得之快閃記憶體，具有較佳的平坦 度，並且可以大幅縮小尺寸。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂’ 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 F : 圖式之簡單說明： 第1圆係繪示傳統快閃記憶體之佈局圖； 第2、3與4圖係繪示傳統快閃記憶體之製造流程剖面 圖，且係從第1圖I-Ι剖面方向所得之製造流程剖面圖； 第5與6圖係繪示傳統快閃記憶體之製造流程剖面圖’ 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX 297公釐} I Hi.^I H ^------^ (請先閱讀背面之注意事項 一:寫本頁) ^4 3 9 2 8 2 3 5 8 9 twf . doc / 0 02 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（（7) 且係從第]圖II-II剖面方向所得之製造流程剖面圖； 第7圖係繪示依據本發明之一較佳實施例之一種快閃 W憶體之佈局圖； 第8至12圖係繪示依照本發明一較佳實施例的一種快 閃記憶體之製造流程剖面圖，且係沿著第7圖中ΠΙ-ΙΙΙ方 向所得之剖面圖；以及 第13圖係繪示在第12圖的製造步驟中，沿著第7圖 中IV-IV方向所得之剖面圖。 圖示標記說明： 10、50 :基底 12、52 :隧穿氧化層 14 :場氧化層 16、6 2 :浮置聞極層 20、 60 :控制閘極層 22a、72 :源極區 22b、68 :汲極區 24 :燧穿擴散區 32 :接觸窗口 34 :金屬層 76 :選擇閘極層 、64、74 :內多晶矽介電層 21、 66、70 :光阻 實施例 第7圖係繪示依據本發明之-較佳實施例之一種快閃 ----------私衣------1T------0 (#先聞讀背面之注意事項 供寫本頁) 本紙張尺度適用中國國家標準（CNS >A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 3589twf . doc/002 A7 __B7 五、發明説明（1) 記憶體之佈局圖。第8至12圖係繪示依照本發明一較佳 實施例的一種快閃記憶體之製造流程剖面圖。其中，第_8 至12围是繪示沿著第7圖中ΙΙΙ-ΠΙ方向所得之剖面圖。 而第13圖是繪示在第12圖的流程步驟中，沿_著.弟7圖中 IV-IV方向所得之剖面圖。 請參照第8圖，提供一基底50，接著例如使用熱氧化 法在此基底50上形成-層厚度約爲85A至100A的氧化物 質。然後例如使用低壓化學氣相沉積法在此層氧化物質上 形成一層多晶矽物質，此層多晶矽物質的厚度約爲1500A。 接著利用微影蝕刻技術定義此層多晶矽物質與此層氧化物 質，以分別形成多晶矽層54與隧穿氧化層52。其中，多 晶矽層54兩側均暴露出基底表面。 接著例如使用低壓化學氣相沉積法沉積內多晶矽介電 物質57，覆蓋多晶砍層54的表面。此內多晶矽介電物質 57例如爲氧化物/氮化物/氧化物之三層結構，厚度約爲 250A。然後例如使用低壓化學氣相沉積法在此內多晶矽介 電物質上形成一層厚度約爲3000A的多晶矽物質。 然後，使用一罩幕與蝕刻技術定義多晶矽物質’藉以 使得多晶矽物質成爲多晶矽層60，此多晶矽層60係作爲 快閃記憶體之控制閘極層之用。 請參照第9圖，使用定義多晶矽層60之相同罩幕與触 刻技術，繼續往F蝕刻內多晶矽介電物質5 7與多晶矽層 54，藉以分別形成如第9圖所示之內多晶矽介電層64與 多晶矽層62=此多晶矽層62係作爲快閃記憶體之浮置閘 本紙張尺度適用中國國家標準（CNS ) A4说格（2丨0 X 2SI7公釐） I^------、訂------0 (請先閲讀背面之注意事項.f寫本頁) 35S9twf.doc/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明Θ ) 極層之用。 請參照第10圖，上光阻66覆蓋部分多晶矽層60，藉 以選擇性地曝露出隧穿氧化層52的表面。然後進行離子 植入步驟，植入摻質，例如濃度高的Ν型離子，於基底50 中，此基底50的位置對應於未被光阻66覆蓋的隧穿氧化 層52。此濃度高的Ν型離子，比如爲磷離子。而此離子 植入步驟則是例如使用·傾斜角度將摻質植入基底中。接 著，進行回火步驟，使摻質形成隧穿擴散區68。此隧穿擴 散區68例如是作爲汲極區之用，且約側向地延伸至多晶 石夕層62下方之基底50中。 3靑爹照第1丨圖’當隨穿擴散區68形成之後’則去除 光阻66 =然後，另外上光阻70覆蓋隧穿擴散區68以及部 分原先被光阻66 (第10圖）所覆蓋之隧穿氧化層52表面， 例如是覆蓋鄰近多晶矽層62的隧穿氧化層52表面。然後， 進行離子植入步驟，於基底50中植入摻質，例如植入高 濃度的Ν型離子，比如砷離子。此基底50的位置對應於 未被光阻66覆蓋的隧穿氧化層52。接著進行回火步驟， 使摻質形成離子佈植區72。因爲，離子佈植區72中植入 的是較重的離子，例如砷離子，所以較不易產生擴散現象。 此離？佈植區72.例如是作爲源極區，並且約以一間距距 離多晶矽層62。 請參照第12與13圖，當離子佈植區72形成之後，則 去除光阻70»接著例如使用低壓化學氣相沉積法沉積內多 晶矽介電物質74，覆蓋整個基底結構表面，包括覆蓋擴散 ---Hi--—- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------^-----—ΐτ------.^ (.請先閲讀背面之注意事項Κ, ‘寫本頁〕 ϋΙ4 3 9 2 8 2 3589twf . doc/002 A7 B7 經濟部中央標率局員工消費合作社印裝 五、發明説明（7) 摻雜區68、離子佈植區72、多晶矽層60與62。此內多晶 矽介電物質74的厚度約大於250A，例如爲氧化物/氮化物 /氧化物之三層結構。然後，例如使用低壓化學氣相沉積法 在此層內多晶矽介電物質74上形成一層多晶矽物質。接 著，例如使用微影蝕刻技術定義此層多晶矽物質，直至約 曝露出下方的內多晶矽介電物質層74，以形成多晶矽層 76。此多晶矽層76係作爲快閃記憶體之選擇閘極層之用， 選擇閘極層的位置係對應且位於浮置閘極層上，並且選擇 閘極層的延伸方向約垂直於控制閘極層。然後，進行後續 的步驟以完成快閃記憶體之製造。然而此後續製程因爲非 關本發明之特徵，所以此處不再贅述。 本發明是利用源極側邊注入的方式，可使記憶胞具有 較高的可程式效率與較低的存寫電流，例如約爲100至1000 微安培（// A)。因此，本發明之快閃記憶體不需要高操作 電壓，所以可適用於低伏特與低電源供應的操作中。此外， 源極區與汲極區的離子摻雜是分開進行，可以分別控制摻 雜的量，方便調整快閃記憶體的參數。 本發明之快閃記憶胞的特性是利用選擇閘防止不當的 滲出電流導致的過度抹除現象，以維持記憶體的正常運 作。 本發明利用離子佈植區72可作爲埋入式線之用。所以 不需在後續步驟中形成接觸窗口也不需塡入金屬層。因此 不會有金屬層反射的干擾。 並且，在本發明之製程中不需形成場氧化層，因此依 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------i------,1T------線 (請先閲讀背面之注意事項-..六寫本頁) 3589twf.doc/002 _______B7_ 五、發明説明（丨C ) 據本發明之方法所獲得之快閃記憶體，具有較佳的平坦 度，並ii可以大幅縮小尺寸。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----------t---------.—ΐτ------0 (，請先閱讀背面之注意事項r^寫本頁) 經濟部中央標準局員X消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）The consumer cooperation of the Central Economic and Technical Bureau of the Ministry of Economic Affairs of the People's Republic of China has printed α 3 f 3 2 G.:- 3589twf, doc / 002 A7 B7 V. Description of the invention (I) The present invention relates to a method for manufacturing a memory, and In particular, it relates to a method for manufacturing a flash memory. Electrically erasable programmable read-only memory (EEPROM) is a widely used memory element in personal computers and electronic devices. The earliest traditional EEPROM memory cell was completed with a floating gate structure. It has the advantages of writing, erasing, and saving data after power failure. However, there are disadvantages of too large area and slow access speed ', which are typically between 150ns and 200ns. In recent years, Flash with faster access speed has been developed. Its access speed is between 70ns and 80ns. The American Iinel company calls it flash memory. The working principle is to use thermal electron storage data and Fowler-Nordhdm tunneling effect to erase data. That is, when storing data, a high voltage of-. · Approximately 8V is applied between the drain region and the source region, and a high voltage is also applied to the control gate layer to cause hot electrons (Hm Electrons) to flow from the source region. Passing through the tunnel oxide layer near the drain region, it is implanted and trapped in the floating gate layer, which is the conventional method of drain side injection. The threshold voltage of the floating gate transistor is increased to achieve the purpose of storing data. When erasing memory data, a positive voltage is applied to the source region and an appropriate negative voltage is applied to the control gate layer, so that the electric current f trapped in the floating gate layer is tunneled again through the tunnel oxide layer. And when it comes out, the memory data is deleted, and the floating gate transistor is restored to the state before the data is stored. Figure 1 is a diagram showing the layout of a conventional flash memory (Lay Out). Figures 2, 3, and 4 show the manufacturing process (CNS) A4 ^ (2) 0 ^ 297 ^ obtained from the cross-section direction of Figure M --------- ^ ------ -IT ------ ^ (-Please read the phonetic entry on the back before filling this page) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3 5 8 9 twf. Doc / 〇 〇 2 4, A7 B7 5 2. Description of the invention (>) A cross-sectional view, and Figs. 5 and 6 are cross-sectional views of the manufacturing process obtained from the direction of the cross-section of Fig. 1-II. The manufacturing method of the conventional flash memory is as follows. Referring to FIGS. 2 and 5 at the same time, first, a substrate 10 is provided, and then a pad oxide layer (not shown) is formed on the substrate, for example, using a thermal oxidation method. Then, for example, an area oxidation method is used to form a field oxide layer 14 on the substrate 10 to define an active area. Then, the pad oxide layer is removed using, for example, a wet etching method. Next, for example, a thermal oxidation method is used to form a tunnel oxide layer 12 on the surface of the device region to a thickness of 100A. Then, for example, a low pressure chemical vapor deposition method is used to tunnel the oxide layer 12 1: to form a layer of polycrystalline silicon material with a thickness of 1500A. Polylithic sand material is then defined using lithographic etching technology to form a polycrystalline sand layer 161. The polycrystalline sand layer 16 serves as a floating gate layer for flash memory. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inter-poly silicon dielectric layer (Inter-poly Dielectric layer) to cover the polycrystalline sand layer. The thickness of the polycrystalline silicon dielectric material is about 250A, and the material is oxide / nitride / Oxide (Nitnde / Oxide) three-layer structure. Then, a low-pressure chemical vapor deposition method is used to form another layer of polycrystalline silicon material on the polycrystalline silicon dielectric material, and the thickness of this layer of polycrystalline silicon material is 3000A. Next, this layer of polycrystalline silicon material is defined using a lithography etching technique and the inner polycrystalline silicon dielectric material is etched down to form a polycrystalline silicon layer 20 and an inner polycrystalline silicon dielectric layer 18. Among them, the polycrystalline sand layer 20 is used as a control layer of the flash memory. Then, using the lithography touch-engraving technology and using the polycrystalline layer 20 as a mask, the engraving step is performed to further define the polycrystalline layer 丨 6 until the base _4_____ is exposed. This paper size applies the Chinese National Standard (CNS) A4 specifications (210X297 mm) --------- 1 ------ 1T ------, ^ (-Please read the precautions on the back before filling this page) Tip 439282 3589twf. doc / 002 Β7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (发明) Bottom] 0 surface. So far, the polycrystalline silicon layer 20, the inner polycrystalline silicon dielectric layer 18, the polycrystalline silicon layer 16 and the tunneling oxide layer Π constitute the gate electrode of the flash memory. Next, the photoresist 2] is used to define the semiconductor substrate and expose the gate electrode among them One side of the base 10. And using ion implantation, a high concentration of phosphorus ions is implanted into the exposed substrate 10 at an oblique angle, and a tempering step is performed to form a tunnel diffusion region 24. The tunneling diffusion region 24 extends below the gate electrode. Referring to FIG. 3, the photoresist 21 is removed after the tunnel diffusion region 24 is formed. The ion implantation process is performed using the polycrystalline silicon layer 20 as a mask to implant a high concentration of arsenic ions into the substrate 10 to form a source region 22a and a drain region 22b. The tunneling diffusion region 24 surrounds the source region 22a. Please refer to FIGS. 4 and 6 at the same time, and then use a low pressure chemical vapor deposition method to deposit a dielectric layer 30 to cover the entire substrate structure. A lithographic etching technique is used to form a contact window 32 on the dielectric layer 30. The contact window 32 exposes the drain region 22b. A low-pressure chemical vapor deposition method is used to deposit a metal layer 34 in the contact window 32 and contact the drain region 22b. Among them, the metal layer 34 is used as a bit line. Then, follow-up processes are performed to complete the manufacture of flash memory. However, this follow-up process can be easily achieved by those skilled in the art, so it will not be repeated here. This conventional flash memory is a step of programming using thermal electrons (Pr0gram), and it uses the drain side injection method, so it needs a higher voltage (8V) to provide a higher current. Such conventional flash memory often causes over-erase during erasing operation. ---------- Installation ----- 1T ------, #. (Please read the notes on the back first. K write this page) The paper scale is applicable to Chinese national standards (CNS ) A4 size (210X297mm) printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3589twf.doc / 002 A7 B7 V. Description of the invention (ten) In addition, the conventional flash memory is limited by the size of the contact window 32, Therefore, there is no groundbreaking reduction in u, and because the field oxide layer 14 is formed, the reduction is limited and the flatness is not good. In addition, because the metal layer needs to be inserted into the contact window and door as a bit line, the interference caused by the metal layer reflection cannot be avoided. Therefore, the main object of the present invention is to provide a flash memory manufacturing method for improving the shortcomings of the conventional flash memory. According to the purpose of the present invention, a method for manufacturing a flash memory is proposed, which includes the following steps: forming a stacked and defined first polycrystalline silicon layer and an oxide layer on a substrate = sequentially forming a first dielectric layer and a first dielectric layer Two polycrystalline silicon layers cover the first polycrystalline silicon layer = for example, the first polycrystalline sand layer is defined by the lithography method and the first polycrystalline silicon layer is further defined. This second polycrystalline silicon layer is located at the first On a polycrystalline silicon layer, and the second polycrystalline silicon layer has a first extension direction, wherein the substrate is exposed on both sides of the second polycrystalline sand layer. A first ion implanted region, such as a phosphorus ion implanted region, is formed in the substrate below one side of the second polycrystalline silicon layer. This phosphorus ion implantation region can be used as a drain region. A second ion implanted region, such as an arsenic ion implanted region, is formed in the substrate below the other side of the second polycrystalline silicon layer. This arsenic ion implanted region can be used as a source region 'and & with a pitch distance of the first polycrystalline silicon layer = sequentially formed _ · a second dielectric layer covers the entire substrate structure' and a defined second The crystalline silicon layer covers the second dielectric layer. The third polycrystalline silicon layer has a second extending direction. The first extension direction and the second extension direction are approximately perpendicular to each other. This paper size applies to Chinese national standards (CMS > A4 specification (2Ι〇Χ2ί7mm) ---------- ^ ------ 1T ------ 0 (Please read first Note on the back f write this page) 3589twf .doc / 002 A7 3589twf .doc / 002 A7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (ζ) The present invention uses source side injection (Source Side Injection) Injection) method can make the memory cell have higher programmable efficiency and lower write current (Write Current), for example, about 100 to 1000 microamperes (v A). Therefore, the present invention Flash memory does not require high operating voltage, so it can be used in low voltage and low power supply operations. In addition, the ion doping in the source and drain regions is performed separately, and the amount of doping can be controlled separately. It is convenient to adjust the parameters of the flash memory. · The characteristics of the flash memory cell of the present invention is to prevent the over-erasing phenomenon caused by improper oozing current in order to maintain the normal operation of the memory. The use of ion implantation flora as a buried line The contact window needs to be formed in the post-painting step and the metal layer does not need to be penetrated. Therefore, there is no interference from the reflection of the metal layer. And a, no field oxide layer needs to be formed in the process of the present invention, The obtained flash memory has better flatness and can be greatly reduced in size. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand, hereinafter, a preferred embodiment is provided and cooperates with all The drawing is used for detailed description, such as F: the brief description of the drawing: The first circle shows the layout of the traditional flash memory; the second, third and fourth figures show the cross-section of the manufacturing process of the traditional flash memory Figures are cross-sectional views of the manufacturing process obtained from the direction of the cross-section of Figure 1-I; Figures 5 and 6 are cross-sectional views of the manufacturing process of traditional flash memory 'This paper size applies to China National Standard (CNS) A4 Specifications (2 丨 OX 297mm) I Hi. ^ IH ^ ------ ^ (Please read the first note on the back: write this page) ^ 4 3 9 2 8 2 3 5 8 9 twf.doc / 0 02 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention Description ((7) And it is a cross-sectional view of the manufacturing process obtained from the direction of the cross-section of FIG. II-II; FIG. 7 is a layout diagram of a flash W memory body according to a preferred embodiment of the present invention; and FIGS. 8 to 12 are A cross-sectional view of a manufacturing process of a flash memory according to a preferred embodiment of the present invention is shown, and is a cross-sectional view taken along the direction II-III in FIG. 7; and FIG. 13 is shown in FIG. 12 In the manufacturing steps, the sectional view is taken along the IV-IV direction in FIG. 7. Description of icons: 10, 50: substrate 12, 52: tunneling oxide layer 14: field oxide layer 16, 6 2: floating smell layer 20, 60: control gate layer 22a, 72: source region 22b, 68: Drain region 24: Punch-through diffusion region 32: Contact window 34: Metal layer 76: Select gate layer, 64, 74: Internal polycrystalline silicon dielectric layer 21, 66, 70: Photoresist example 7 Shows a flash according to the preferred embodiment of the present invention ---------- Private clothing ----- 1T ------ 0 (# 先 闻 读 NOTES on the back for (Write this page) This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 3589twf. Doc / 002 A7 __B7 V. Description of the invention (1) Memory layout Figures 8 to 12 are cross-sectional views showing the manufacturing process of a flash memory according to a preferred embodiment of the present invention. Among them, the _8 to 12th circle are shown along the ll-ll-ll in the seventh figure. A cross-sectional view obtained in the direction shown in FIG. 13 is shown in the process steps of FIG. 12 along the IV-IV direction in FIG. 7. Please refer to FIG. 8 to provide a substrate 50, then For example, a thermal oxidation method is used to form an oxide material on the substrate 50 with a layer thickness of about 85 A to 100 A. Then, for example, a low pressure chemical vapor deposition method is used to form a layer of polycrystalline silicon material on this layer of oxide material. The thickness of this layer of polycrystalline silicon material is about It is 1500 A. Next, the polycrystalline silicon material and the oxide material are defined by lithographic etching technology to form a polycrystalline silicon layer 54 and a tunneling oxide layer 52. Among them, the polycrystalline silicon layer 54 exposes the substrate surface on both sides. Then, for example, using a low voltage The chemical vapor deposition method deposits an inner polycrystalline silicon dielectric substance 57 to cover the surface of the polycrystalline cutting layer 54. The inner polycrystalline silicon dielectric substance 57 has, for example, a three-layer structure of oxide / nitride / oxide, and has a thickness of about 250 A. Then, For example, a low-pressure chemical vapor deposition method is used to form a layer of polycrystalline silicon material with a thickness of about 3000 A on the polycrystalline silicon dielectric material. Then, a mask and an etching technique are used to define the polycrystalline silicon material, so that the polycrystalline silicon material becomes a polycrystalline silicon layer 60. Layer 60 is used to control the gate layer of flash memory. Please refer to Figure 9 to define the polycrystalline The same mask and touch technology of the silicon layer 60 continue to etch the polycrystalline silicon dielectric substance 5 7 and the polycrystalline silicon layer 54 toward F, so as to form the polycrystalline silicon dielectric layer 64 and the polycrystalline silicon layer 62 as shown in FIG. 9 respectively. Polycrystalline silicon layer 62 is used as a floating gate for flash memory. The paper size is applicable to the Chinese National Standard (CNS) A4 scale (2 丨 0 X 2SI7 mm) I ^ ------, order ----- -0 (Please read the precautions on the back. F write this page) 35S9twf.doc / 002 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention Θ) Polar layer. Referring to FIG. 10, the upper photoresist 66 covers a portion of the polycrystalline silicon layer 60, thereby selectively exposing the surface of the tunneling oxide layer 52. Then, an ion implantation step is performed to implant dopants, such as high-concentration N-type ions, into the substrate 50, and the position of the substrate 50 corresponds to the tunneling oxide layer 52 not covered by the photoresist 66. The N-type ion having a high concentration is, for example, a phosphorus ion. The ion implantation step is, for example, implanting a dopant into a substrate using a tilt angle. Next, a tempering step is performed to cause the dopants to form a tunnel diffusion region 68. This tunneling diffusion region 68 is used, for example, as a drain region and extends approximately laterally into the substrate 50 below the polycrystalline silicon layer 62. 3 Photo according to Figure 1 丨 After the formation of the diffusion region 68, the photoresist 66 is removed. Then, the photoresist 70 covers the tunnel diffusion region 68 and part of the photoresist 66 (Figure 10). The covered surface of the tunneling oxide layer 52 is, for example, a surface of the tunneling oxide layer 52 covering the adjacent polycrystalline silicon layer 62. Then, an ion implantation step is performed to implant a dopant into the substrate 50, such as implanting a high concentration of N-type ions, such as arsenic ions. The position of this substrate 50 corresponds to the tunnel oxide layer 52 which is not covered by the photoresist 66. A tempering step is then performed to form the ion implantation region 72 by doping. Because the ion implantation region 72 implants heavier ions, such as arsenic ions, it is less likely to cause diffusion. This away? The implanted region 72 is, for example, a source region, and is spaced apart from the polycrystalline silicon layer 62 by an interval. Please refer to FIGS. 12 and 13. After the ion implantation region 72 is formed, the photoresist 70 is removed. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inner polycrystalline silicon dielectric substance 74 to cover the entire surface of the substrate structure, including covering diffusion. --Hi ----- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) --------- ^ ------- ΐτ ------. ^ ( .Please read the note on the back KK, 'Write this page] ϋΙ4 3 9 2 8 2 3589twf. Doc / 002 A7 B7 Printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) Doped region 68 , Ion implantation region 72, polycrystalline silicon layers 60 and 62. Here, the thickness of polycrystalline silicon dielectric substance 74 is greater than 250A, for example, a three-layer structure of oxide / nitride / oxide. Then, for example, using low pressure chemical vapor deposition A polycrystalline silicon substance is formed on the polycrystalline silicon dielectric substance 74 in this layer. Then, for example, this layer of polycrystalline silicon substance is defined using a lithographic etching technique until the underlying polycrystalline silicon dielectric substance layer 74 is exposed to form a polycrystalline silicon layer 76. This polycrystalline silicon layer 76 is used as the flash memory selection gate For the layer, the position of the selected gate layer is corresponding and located on the floating gate layer, and the extension direction of the selected gate layer is approximately perpendicular to the control gate layer. Then, the subsequent steps are performed to complete the flash memory. Manufacturing. However, this subsequent process is not related to the features of the present invention, so it will not be repeated here. The present invention uses the source side injection method to make the memory cell have higher programmability and lower storage and writing The current, for example, is about 100 to 1000 microamperes (// A). Therefore, the flash memory of the present invention does not require a high operating voltage, so it is suitable for operation with low voltage and low power supply. In addition, the source region The ion doping is performed separately from the drain region, and the amount of doping can be controlled separately to facilitate the adjustment of the parameters of the flash memory. The characteristics of the flash memory cell of the present invention is to prevent the excessive leakage caused by improper oozing current by using a selection gate. The erasing phenomenon is used to maintain the normal operation of the memory. The present invention utilizes the ion implantation area 72 as an embedded thread. Therefore, it is not necessary to form a contact window or deposit gold in the subsequent steps. Layer. Therefore, there will be no interference from the reflection of the metal layer. Also, no field oxide layer needs to be formed in the process of the present invention, so the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied according to the paper scale. ---- ------ i ------, 1T ------ line (please read the notes on the back-.. 6 write this page) 3589twf.doc / 002 _______B7_ V. Description of the invention (丨C) The flash memory obtained by the method of the present invention has better flatness and can be greatly reduced in size. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. ---------- t ---------.— ΐτ ------ 0 (Please read the notes on the back r ^ write this page) Member of the Central Standards Bureau of the Ministry of Economic Affairs Paper size printed by X Consumer Cooperative is applicable to China National Standard (CNS) A4 (210X297 mm)