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TW432653B - Flip chip package structure and process with increased encapsulation efficiency and reliability - Google Patents

Flip chip package structure and process with increased encapsulation efficiency and reliability Download PDF

Info

Publication number
TW432653B
TW432653B TW88121289A TW88121289A TW432653B TW 432653 B TW432653 B TW 432653B TW 88121289 A TW88121289 A TW 88121289A TW 88121289 A TW88121289 A TW 88121289A TW 432653 B TW432653 B TW 432653B
Authority
TW
Taiwan
Prior art keywords
substrate
wafer
chip
flip
pads
Prior art date
Application number
TW88121289A
Other languages
Chinese (zh)
Inventor
Su Tao
Wei-Chung Wang
Hsueh-Te Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21643270&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW432653(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW88121289A priority Critical patent/TW432653B/en
Application granted granted Critical
Publication of TW432653B publication Critical patent/TW432653B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a structure and a process of a flip chip package with increased encapsulation efficiency and reliability. The process comprises, prior to covering the chip on the surface of the substrate, pre-coating a plurality of non-conductive adhesive on the center region of the chip cover region on the substrate where the adhesive maintains a suitable gap for maintaining a suitable air flow between the center region of the chip and the outside, thereby increasing the adhesion strength of the chip covering on the substrate and preventing the deformation of the adhesion region of the protrusion electrode in the subsequent baking process which may cause a poor connection of the electrode or separation, as well as ineffectiveness of the package product. The center region of the substrate is formed with a through hole. Through the through hole and a pre-coated non-conductive adhesive, a filler material can flow towards the center of the substrate during a filling operation towards the whole surrounding or one side of the chip. Furthermore, during the flowing of the filling material, air among the substrate, the chip and the filling material can escape out of the substrate through the through hole formed at the center, thereby greatly reducing the packaging time while effectively driving away air between the substrate and the chip without generating a void.

Description

C7 D7 f 4 326 5 3 五、創作説明（/ ) 本發明係關於一種可增進封勝效率及可靠度之覆晶封 裝結構及製程’尤指一種在基板上之中央形成有一通孔的 覆晶封裝結構以及在基板之中央處先以點矩陣的方式塗佈 有黏膠，以加強覆晶時晶片與基板間因黏膠之作用而加強 晶片與基板彼此間的黏著性，進而提高導電膠對晶片突塊 電極與基板焊墊之間黏著可靠度，之後，充填材料可由晶 片之全部周圍或是一側同時澆注時，充填材料可以同時向 晶片中央區域流動’而存在於基板 '晶片以及充填材料間 的空氣則可因為充填材料的流動而被推送到通孔處，並由 該通孔處散出至外界；此舉可大幅減少澆注封膠之時間而 可增進封膠效率。 按，覆晶封裝之半導體裝置由於具有高元件密度及快 速之資料存取速度’故其使用已逐漸普遍，第六A圖至六 D圖顯示一習知之覆晶封裝製程以將一晶片（DIE) (5〇 )黏著至一基板上（51) ’又如第七圖所示，該晶片（5〇 )之底面具有分佈於邊緣之周邊突塊電極（peripheral BUMP ) ( 52 )，各突塊電極（52 )係由共晶焊料（ EUTECTIC SOLDER)所形成，並經由電極塾（53)設置於 晶片（50)底面；再請參照第六a圖，於覆晶封裝時，係 首先將晶片（50)具有突塊電極（52)之面朝下，並如第 六B圖所示’將晶片（5〇)置入一裝有熔接劑（FLUX)( 54)之容器（55)内以將突塊電極（52)浸入熔接劑（54 )中’再將突塊電極（52)沾有熔接劑（54)之晶片（50 )取出’並如第八C圖所示，將晶片（50)覆置於一基板 ____3 本#Mit尺度埴用中困國家標率（CNS > A4規格（2丨0X297公釐） "" I 装 ： 訂I 線 · - ' (請先閲讀背面之注意"項存填寫本頁) 經濟部"^57雇/;>0工^^費合作社印製 1*43265 3 五、創作説明（7) (51) 上，另請參照第八圖所示’該基板（51)上係覆蓋 有一層焊罩（57)及形成有若干焊墊（58)以與該晶片（ 50)之突塊電極（52)焊接在一起，藉此，如第六d圊所 示’該晶片（50)與基板（51)間得以形成適當之電連接 ’最後’尚須使用一點膠管（56)來進行封膠步驟以在晶 片（51)與基板（52)間澆灌注入充填材料⑼仙比[ )(59)，使該晶片（51)與基板（52)更可靠地結合在 一起’以避免覆晶半導體裝置受熱時，晶片（51)與基板 (52) 產生不同程度之膨脹而破壞其焊接之可靠性。 又’第九A圖至九D_圖係顯示另一可見於美國專利第 5641996號案之覆晶封裝製程，其係將一底面具有金質之 周邊突塊電極（82)之晶片（80)黏著至一基板（81)上 ，其封裝步驟亦是首先將晶片（80)具有突塊電極（82) 之面朝下（如第九A圖），將其置入一裝_有導電勝（ CONDUCTIVE ADHESIVE) (84)之容器（85)内以將突塊電 極（82)浸入導電膠（84)中（如第九B圖），再將突塊 電極（82)沾有導電穆·（84)之晶片（8〇)取出並覆置於 一基板（81)上（如第九C圖），其中，該基板（81)上 係覆蓋有一層焊罩（87)及形成有若干焊塾（88)以與該 晶片（80)之突塊電極（82)藉由導電膠（84)黏著在一 起’最後’則以一點膠管（DISPENSER) (86)進行封膠 製程以在晶片（80)與基板（81)間澆灌注入充填材料（ 如第九D圖）。 前述習知之覆晶封裝製程於澆注充填材料（59，89) 4 本紙&尺度逋用中國國家梂率（CNS ) A4洗格（210X297公着 1 ~ H! 裝一_ ^ 7訂I '~線 <· - I {請先聞讀背面之注意事項再填寫本頁) C7 D7 14 326 5 3 五、創作説明（> ) 時，僅能'以點膠管（56，86)自晶片（50，80 )之一側或 兩側予以澆注，以使該充填材料（59，89)藉著毛細作用 {請先閲讀背面之注意事項再填寫本頁) (CAPILLARY ACTION)流入晶片（50，80)與基板（5卜 81)間，因此，其澆注封膠之時程極長，而使得覆晶封裝 製程之效能無法提高，且在晶片（50，80 )之中央底下之 充填材料不易將殘餘空氣有效排除而產生空隙（VOID)， 使得在覆晶封裝之半導體裝置於受熱時，易受水氣熱應力 (HYGRO-THERMAL STRESS)之作用而損壞，故實有予以改 進之必要。 再者，即使在克服了上述產生空隙的問題後，由於晶 片（50’ 80)與基板（51，81)在灌入充填材料之前，晶 片（50，80)與基板（51 ’81)之間必須要藉由加熱固化 (CURING)的過程而先行連結在一起，惟，在加熱固化時 ，由於晶片（50，80)與基板（51，81)因為熱膨脹係數 (COEFFICIENT OF THERMAL EXPANSION)的不同而有受熱 變形或應力產生的問題，而容易產生導電膠（84)黏著不 良或分離情形。 因此，本發明之目的即在提供—種可增進封膠效率及 可靠度之覆晶封裝製程’其主要係將晶片覆置於—基板表 面之前，先行藉由點矩陣的方式將黏膠予以塗佈在基板中 間之區域上’促使覆晶時晶片與基板間因黏膠之作用而加 強晶片與基板彼此間的黏著性，進而提高導電膠對晶片突 塊電極與基板焊墊之間黏著可靠度； 本發明的再一目的即是在提供一種可增進封膠效率之 5 表紙張尺度適用中國國家標準（CNS > A4現格（21〇χ297公簸·)· F4 326 5 3 g 五、創作说明（0)" — 覆晶封裝結構，其主要是在該基板之區域中央形成有一 孔’藉此，充填材料可由晶月之全部周圍或是一側同時澆 注時，充填材料可以同時向晶片中央區域流動，而存在於 基板、晶片以及充填材料間的空氣則可因為充填材料的流 動而被推送到通孔處，並由該通孔處散出至外界；此舉可 大幅減少澆注封膠之時間，並有效將該基板與晶片間之空 氣驅離。 & 為使貴審查委員能進一步瞭解本發明之結構、特 徵及其目的，茲附以圖式及詳細說明如后： (一） 圖式部分： 第一圖：係本發明所使用之基板之平面圖； 第二圖：係本發明所使用之基板之剖面圖； 第二圖.係顯示本發明在基板上洗塗充填材料之平面圖； 第四圖：係顯示本發明之基板塗佈黏膠後之平面圖； 第五A至第五E圖：係顯示本發明之覆晶封裝製程； 第六A至第六D圖：係顯示一種習知之覆晶封裝製程。 第七圖：係為晶片之突塊電極排列示意圖； 第八圖：係為基板之表面示意圖；以及 第九Α圖至第歡也\圖：係為另一習用之覆晶封裝製程。 '炉 (二） 圖號部分： (10) ( 51) ( 81)基板 (11 ) ( 58) ( 88 )焊墊 (13)通孔 6 本紙張尺度逍用中國國家梂準（CNS ) A4*t格（210X297公漦) {請先《讀背面之注意事項再填寫本頁) 訂 線 經濟部智ti:9{減/.;θχ;/]ίΓΗ合作社印裂 麝4 326 5 3 C7 _ D7 五、創作説明（f) (15)黏膠 ( 30) ( 50) ( 80)晶片 ( 31 ) ( 52) ( 82)突塊電極 ( 32) ( 53)電極墊 ( 33) ( 84)導電膠 (34) ( 55) ( 85)容器 (35) ( 59 ) ( 89 )充填材料 (36) 通氣空隙 (54)熔接劑 (56) ( 86)點膠管 ( 57) ( 87)焊罩 有關本發明之覆晶封裝結構及製程，首先請先參照第 一圖及第二圖，其顯示本發明之覆晶封裝結構所使用之基 板（10)之平面圖及剖面圖，該基板（丄〇 )之對應覆蓋 晶片之區域處設有複數個焊墊（1 1 )，又於對應覆蓋晶 片之區域之適當位置（本實施例係在中央位置）則形成有 一通孔（1 3 )，另該複數個焊墊（1 1 )係分佈於對應 覆蓋晶片之區域的邊緣以對應於待連接晶片突塊電極，該 對應覆蓋晶片之區域之尺寸則係略大於待連接晶片底面之 尺寸。 為了能進一步減少封膠所需之時間’如第三圖所示， 可在將晶片（未顯示）覆置於該基板（10)之前，於該對 應覆蓋晶片之區域内與焊墊（1 1)間先行以點矩陣的方 7 本紙張尺度逍用中國國家椹率（〇呢>八4規/格（210父297公釐） n I n n I n I n n 1 (請先《婧背面之注意事項再填寫本頁) 訂 線 經濟部智总时/t/.JH;工消費合作钍印製 經濟部智asta/.7,-h丄消費合作社印製 朦432653 - 五、創作説明（& ) 式塗佈黏膠（1 5 )，而在當黏膠（1 5 )塗佈完成之後 ，其即如同在第四圖中所示之結構；故當晶片覆置黏著於 基板（10)時，晶片與基板（1 〇)間在相互黏合時即有部 分可藉由所塗佈之黏膠（15)而接合在一起，進而提高 導電膠（33)對晶片突塊電極（31)與基板焊墊（1工） 之間黏著可靠度。 再請參照第五A圖至五E圖所示，本發明之覆晶封装 製程係以將一底面具有分佈於邊緣之金質周邊突塊電極（ 31)之晶片（30)黏著至該基板上（1〇);其中，該晶片 (30)之各突塊電極（31_)係經由電極塾（32)設置於晶 片C 30)底面’而於覆晶封裝時，參照第五a圖所示，係 首先將晶片（30)具有突塊電極（31)之面朝下，而如第 五B圖所示’將晶片（30 )往下置入一裝有導電勝（33 ) 之谷器（34)内以將突塊電極（31)之端部浸入導電膠（ 33)中’再將突塊電極（31)端部沾有導電穋（33)之晶 片（30)取出並覆置於該基板（1〇)上，如第五C圖所示 ，使其複數個突塊電極（31)分別對準該基板（1〇)之複 數個焊墊（13) ’而藉加熱的方式（如第五d圖所示）由 導電膠（33)將對應之突塊電極（31)與焊塾（13)黏接 在一起’故而使得晶片（30)黏著至該基板（1〇)上以建 立適當之電連接。由於在第五D圖中所示之步驟中，當將 晶片（30)予以和基板（1 0)相連接時，因為在基板 (1 0)上即已有藉由點矩陣方式所塗佈之黏膠（1 5 ) ，故而其間之接結強度將較習用之方式來的更為大。 8 本紙張尺度適用中國國家棣率（CNS > A4规格（210X297公釐） --^---^------裝--"----訂------ 線 (請先閲請背面之注f項再填寫本頁) ^4 326 5 3 C7 _D7_____ 五、創作説明（7) 當晶片（30)與基板（10)黏著在一起時，即可同時 自晶片（3G )之四面或是單側澆注充填材料（35 )以進行 封膠製程’當該充填材料（35)於晶片（30)與基板（10 )間藉由毛細作用向内流入時，晶片（30 )下之空氣即經 由充填材料（3 5)之排擠而朝向該通孔（1 3)向外排 出’故不易產生空隙（VOID) ’當封膠完成後，如第 五E圖所示，於基板（1〇)上之通孔（13)與晶片（30 )亦因為充填材料（3 5 )之填塞而予以充滿，而沒有任 何空隙產生之虞。 综上所述’本發明藉由基板（1〇)之通孔（13)，可 在將晶片（30)黏著至基板（1〇)之該對應覆蓋晶片之區 域後’令充填材料（35)由晶片（30)之四邊同時堯注， 並同時向内佈滿整個對應覆蓋晶片之區域’而介於基板（ 10)、晶片（30)以及黏膠（15)之間的空氣，則 可由該通孔（13)處向外排擠出去，此舉可大幅減少澆注 封膠之時間以增進覆晶封裝之效能，並有效將該基板（1〇 )與晶片（30)間之空氣驅離，誠為一具產業上利用性、 新穎性及進步性之發明，應符合專利申請要件，爰依法提 出申請。 I -—訂I I 線 (請先Μ讀背面之注意事項再填寫本頁) 9C7 D7 f 4 326 5 3 V. Creation instructions (/) The present invention relates to a flip-chip packaging structure and process that can improve the efficiency and reliability of sealing, especially a flip-chip with a through hole formed in the center of the substrate The packaging structure and a dot matrix are first coated with adhesive in the center of the substrate to enhance the adhesion between the wafer and the substrate due to the effect of the adhesive between the wafer and the substrate during the chip-on, thereby improving the conductive adhesive pair. The reliability of the adhesion between the wafer bump electrode and the substrate pad. After that, when the filling material can be poured from all around the wafer or one side at the same time, the filling material can flow to the central area of the wafer at the same time, and it is present on the substrate. The wafer and the filling material The air in between can be pushed to the through hole due to the flow of the filling material and diffused from the through hole to the outside; this can greatly reduce the time for pouring the sealant and improve the sealing efficiency. According to the flip chip packaged semiconductor devices, because of their high component density and fast data access speeds, their use has gradually become widespread. Figures 6A to 6D show a conventional flip chip packaging process to convert a chip (DIE ) (50) adhered to a substrate (51) 'As shown in the seventh figure, the bottom surface of the wafer (50) has peripheral bump electrodes (52) distributed on the edges, each bump The electrode (52) is formed by a eutectic solder (EUTECTIC SOLDER), and is arranged on the bottom surface of the wafer (50) through the electrode 塾 (53); then please refer to FIG. 6a. When flip-chip packaging, the wafer ( 50) The side with the bump electrode (52) is facing down, and as shown in FIG. 6B, 'the wafer (50) is placed in a container (55) containing a welding agent (FLUX) (54) to The bump electrode (52) is immersed in the welding agent (54), and then the wafer (50) with the welding electrode (52) dipped in the welding agent (54) is taken out, and the wafer (50) is shown in FIG. 8C. Overlay on a substrate ____3 This #Mit scale uses the standard rate of the middle and poor countries (CNS > A4 specification (2 丨 0X297 mm) " " I equipment: Order I line ·-(Please read the note at the back & save the item and fill out this page) Ministry of Economic Affairs " ^ 57 雇 /; > 0 工 ^^ Printed by the cooperative 1 * 43265 3 V. Creative Instructions (7) (51 ), Please also refer to the eighth figure, 'The substrate (51) is covered with a layer of solder mask (57) and a number of pads (58) are formed to contact the bump electrode (52) of the wafer (50). Soldering together, as shown in the sixth paragraph (d), 'the wafer (50) and the substrate (51) have a proper electrical connection.' Finally ', a little glue tube (56) must be used to perform the sealing step in The filling material is poured between the wafer (51) and the substrate (52), and the filling material ratio [] (59) is made, so that the wafer (51) and the substrate (52) are more reliably bonded together 'to prevent the flip-chip semiconductor device from being heated, The wafer (51) and the substrate (52) have different degrees of expansion, which destroys the reliability of their welding. Figures 9A through 9D_ show another flip-chip packaging process that can be found in US Patent No. 5641996, which is a wafer (80) with a gold peripheral bump electrode (82) on the bottom surface. It is adhered to a substrate (81), and its packaging step is also to first place the wafer (80) with the bump electrode (82) face down (as shown in Figure 9A), and place it in a package_ 有 电 胜 ( CONDUCTIVE ADHESIVE) (84) in the container (85) to immerse the bump electrode (82) into the conductive adhesive (84) (as shown in Figure 9B), and then immerse the bump electrode (82) with conductive Mu · (84 ) Of the wafer (80) is taken out and placed on a substrate (81) (such as the ninth figure C), wherein the substrate (81) is covered with a layer of welding cover (87) and a number of welding pads ( 88) Adhesive bonding with the bump electrode (82) of the chip (80) by the conductive adhesive (84), and finally, the sealing process is performed with a one-piece rubber tube (DISPENSER) (86) to bond the chip (80) with Filling material is poured between the substrates (81) (as shown in Figure 9D). The aforementioned conventional flip-chip packaging process is used to pour the filling material (59, 89). 4 paper & standard (Chinese national rate (CNS) A4) (210X297 published 1 ~ H! Packing _ ^ 7Order I '~~ Line < ·-I {Please read the notes on the back before filling this page) C7 D7 14 326 5 3 V. When creating instructions (>), you can only use the dispensing tube (56, 86) from the chip (50, 80) One or both sides are poured, so that the filling material (59, 89) flows into the wafer (CAPILLARY ACTION) by capillary action {Please read the precautions on the back before filling this page) (CAPILLARY ACTION) 80) and the substrate (5, 81), so the sealing process is very long, making the performance of the flip-chip packaging process unable to improve, and the filling material under the center of the wafer (50, 80) is not easy to Residual air is effectively removed to generate voids (VOID), so that when the flip-chip packaged semiconductor device is heated, it is susceptible to damage by HYGRO-THERMAL STRESS, so it is necessary to improve it. Furthermore, even after the above-mentioned problem of generating voids is overcome, since the wafer (50 '80) and the substrate (51, 81) are filled with the filling material, the gap between the wafer (50, 80) and the substrate (51'81) It must be connected together through the process of heat curing (CURING). However, during heat curing, the wafer (50, 80) and the substrate (51, 81) are different due to the difference in the coefficient of thermal expansion (COEFFICIENT OF THERMAL EXPANSION). There are problems caused by thermal deformation or stress, and it is easy to cause poor adhesion or separation of the conductive adhesive (84). Therefore, the object of the present invention is to provide a flip-chip packaging process that can improve the sealing efficiency and reliability. It mainly involves coating the adhesive with a dot matrix before placing the wafer on the surface of the substrate. Distributing on the middle area of the substrate 'promotes the adhesion between the wafer and the substrate due to the effect of the adhesive between the wafer and the substrate during the chip-on, thereby improving the adhesion reliability of the conductive adhesive to the wafer bump electrodes and the substrate pads ; Another object of the present invention is to provide a 5-sheet paper size that can improve the sealing efficiency and apply the Chinese national standard (CNS > A4 standard (21〇297297) · F4 326 5 3 g 5. Creation Explanation (0) —Flip-chip packaging structure, which is mainly formed with a hole in the center of the region of the substrate, thereby filling material can be simultaneously poured into the wafer when the material is poured from all around the crystal moon or one side at the same time The central area flows, and the air existing between the substrate, the wafer, and the filling material can be pushed to the through hole due to the flow of the filling material and diffused to the outside from the through hole; Significantly reduce the time for pouring the sealant, and effectively drive away the air between the substrate and the wafer. &Amp; In order to allow your reviewers to further understand the structure, characteristics and purpose of the present invention, drawings and detailed descriptions are attached as After: (1) Schematic part: The first figure: a plan view of a substrate used in the present invention; the second figure: a cross-sectional view of a substrate used in the present invention; the second figure. A plan view of the filling material; The fourth view is a plan view showing the substrate of the present invention after being coated with an adhesive; the fifth views A to F are views showing the flip chip packaging process of the present invention; the sixth A to the sixth D Figure: shows a conventional flip chip packaging process. Figure 7: Schematic diagram of the bump electrode arrangement of the wafer; Figure 8: Schematic diagram of the surface of the substrate; This is another conventional flip chip packaging process. 'Furnace (2) Drawing number part: (10) (51) (81) Substrate (11) (58) (88) Solder pad (13) Through hole 6 Use China National Standards (CNS) A4 * t (210X297 public address) {Please read " Please fill in this page before filling in this page) ti: 9 {minus ..; θχ; /] ίΓΗcooperative cooperatives printed cracks 4 326 5 3 C7 _ D7 V. Creative Instructions (f) (15) Viscose (30) (50) (80) Chip (31) (52) (82) Bump electrode (32) (53) Electrode pad (33) (84) Conductive glue (34) (55) (85) Container (35) ) (59) (89) Filling material (36) Ventilation gap (54) Welding agent (56) (86) Dispensing tube (57) (87) Welding cover First, please refer to the flip chip packaging structure and manufacturing process of the present invention. Referring to the first and second figures, there are shown a plan view and a cross-sectional view of a substrate (10) used in a flip-chip package structure of the present invention. A plurality of solder pads are provided at corresponding areas of the substrate (丄 〇) covering the wafer. (1 1), and a through hole (1 3) is formed at an appropriate position corresponding to the area of the covering wafer (the central position in this embodiment), and the plurality of bonding pads (1 1) are distributed on the corresponding covering wafer The edge of the area corresponds to the bump electrode of the wafer to be connected, and the size of the area corresponding to the covered wafer is slightly larger than the size of the bottom surface of the wafer to be connected. In order to further reduce the time required for the sealant, as shown in the third figure, before the wafer (not shown) is placed on the substrate (10), the pad (1 1 ) Before the use of the dot matrix square 7 paper scales to use the Chinese national rate (0 it > 8 4 gauge / grid (210 father 297 mm) n I nn I n I nn 1 (please first Please fill in this page again for the matters needing attention) Ordering the Ministry of Economic Affairs, the total number of hours /t/.JH; Industry and consumer cooperation 部 Printing the Ministry of Economics wisdom asta / .7, -h 丄 Printing by the Consumer Cooperative 432653-V. Creation Instructions ;) Type coating adhesive (1 5), and after the coating of adhesive (1 5) is completed, it has the same structure as shown in the fourth figure; therefore, when the wafer is adhered to the substrate (10) At this time, when the wafer and the substrate (10) are bonded to each other, part of the wafer and the substrate (10) can be joined together by the applied adhesive (15), thereby improving the conductive adhesive (33) to the wafer bump electrode (31) and Reliability of adhesion between substrate pads (1 work). Please refer to FIG. 5A to FIG. 5E, the flip-chip packaging process of the present invention is to distribute a bottom surface with The wafer (30) of the gold peripheral bump electrode (31) on the edge is adhered to the substrate (10); wherein each bump electrode (31_) of the wafer (30) is provided through the electrode 塾 (32) At the bottom surface of the chip C 30) 'and when flip-chip packaging, referring to the fifth figure a, first the face of the wafer (30) with the bump electrode (31) facing down, as shown in the fifth figure B' Place the wafer (30) down into a trough (34) with a conductive pin (33) to immerse the end of the bump electrode (31) into the conductive glue (33), and then place the bump electrode (31) ) Take out the wafer (30) with conductive rhenium (33) on the end and place it on the substrate (10). As shown in Figure 5C, align its multiple bump electrodes (31) with the The plurality of solder pads (13) of the substrate (10) are heated by a heating method (as shown in FIG. 5d), and the corresponding bump electrodes (31) and the solder pads (13) are adhered by the conductive adhesive (33). “Attach together” thus makes the wafer (30) adhere to the substrate (10) to establish a proper electrical connection. Because in the step shown in the fifth D figure, when the wafer (30) is connected to the substrate (1 0), the substrate (1 0) is already coated by the dot matrix method. Viscose (1 5), so the bond strength between them will be greater than the conventional method. 8 This paper size is applicable to China's national standard (CNS > A4 size (210X297mm)-^ --- ^ ------ packing-" ---- order ------ line (Please read the note f on the back before filling this page) ^ 4 326 5 3 C7 _D7_____ V. Creation Instructions (7) When the wafer (30) and the substrate (10) are stuck together, you can start from the wafer ( 3G) on four sides or one side, pouring the filling material (35) to perform the sealing process. When the filling material (35) flows inward between the wafer (30) and the substrate (10) by capillary action, the wafer (30 The air under) is expelled toward the through hole (1 3) through the extrusion of the filling material (3 5), so it is not easy to generate voids (VOID). After the sealing is completed, as shown in Figure 5E, the The through hole (13) and the wafer (30) on the substrate (10) are also filled due to the filling of the filling material (3 5) without any risk of voids. In summary, the invention uses a substrate ( The through hole (13) of 10) can be used to make the filling material (35) be simultaneously injected from the four sides of the wafer (30) after the wafer (30) is adhered to the corresponding area of the substrate (10) that covers the wafer. and When the entire area corresponding to the wafer is covered inwardly, the air between the substrate (10), the wafer (30) and the adhesive (15) can be squeezed out from the through hole (13). It can greatly reduce the time for pouring the sealing compound to improve the performance of the flip-chip package, and effectively drive the air between the substrate (10) and the chip (30), which is an industrial availability, novelty and progress. Inventions of a natural nature should meet the requirements for patent applications, and apply in accordance with the law. I-Order II (please read the notes on the back before filling out this page) 9

Claims (1)

P4 326 5 3 g —___ D8 六、申請專利範圍 1 ·—種覆晶封裝結構，包括： 一基板’其表面具有複數個焊墊； 基板中間區域内形成有一通孔 複數個以點矩陣方式，附著於基板表面焊墊内側區域 的黏膠； 一覆置於該基板上之晶片，其底面具有複數個突塊電 極以導電勝連接至該基板之該複數個焊墊； 及 澆注於該晶片與該基板間之充填材料； 其中’該基板表面之中間區域為一對應覆蓋晶片之區 域，且該複數個焊墊係位於該對應覆蓋晶片之區域内，又 於該對應覆蓋晶片之區域内形成有一通孔，藉此，該充填 材料可由該晶片之全部周圍同時澆注，使其經由該對應覆 蓋晶片之區域以極佳之流動性向内流動，可有效將該基板 與該晶片間之空氣自該通孔處驅離而不會產生空隙。 2. 如申請專利範圍第1項所述之覆晶封裝結構，其 中該晶片之突塊電極係分佈於其底面邊緣且該基板之焊墊 係位於該對應覆蓋晶片之區域内之邊緣。 3. 如申請專利範圍第丨項所述之覆晶封裝結構，其 _該複數個黏膠為不導電。 4· 一種覆晶封裝製程，其係將一底面具有複數個突 塊電極之晶片覆置連接至一基板，其中該基板表面之中間 區域為一對應覆蓋晶片之區域，該對應覆蓋晶片之區域内 ______10 ( CNS ) A4#Lfr { 210 X 2974^¾ ) 一— -- (請先®#背面之注$項再填寫本育) 订 線 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 14 32 6 5 3 g8 _ DS 六、申請專利範圍 具有複數個焊墊以分別對應於該複數個突塊電極，又於該 對應覆蓋晶片之區域之中央則形成有一通孔，該封裝製程 包括下述之步驟： 將黏膠予以塗佈在基板上焊墊内側之區域； 將該晶片之複數個突塊電極浸入導電膠中後取出，以 使每一突塊電極之端部沾有導電膠； 將該晶片覆置於該基板，使其複數個突塊電極分別對 準該基板之複數個焊墊，而藉由導電膠將對應之突塊電極 與焊墊黏著在一起； 加熱固化，使得晶片和基板之間因為導電膠與黏膠之 關係而可穩固地結合在一起；及 將充填材料由該晶片之全部周圍或單側同時澆注，使 其經由該對應覆蓋晶片之區域以極佳之流動性向内流動而 至佈滿整個區域，可有效將該基板與該晶片間之空氣由該 通孔驅離而不會產生空隙。 5·如申請專利範圍第4項所述之覆晶封裝製程，其 中該黏膠係以點矩陣的方式塗佈整個該對應覆蓋晶片之區 域内。 6_如申請專利範圍第4項所述之覆晶封裝製程，其 中該複數個黏膠為不導電。 11 本紙張尺度埴用t國國家椹率（CNS ) A4规格（210X297公釐） ---------%------訂.-------漆 f · (請先S讀背面之注意事項再填寫本瓦)P4 326 5 3 g —___ D8 6. Scope of patent application 1 · A flip-chip package structure, including: a substrate with a plurality of pads on its surface; a through-hole in the middle area of the substrate with a dot matrix method, Adhesive adhered to the inner area of the pad on the surface of the substrate; a wafer overlaid on the substrate, the bottom surface of which has a plurality of bump electrodes connected electrically to the substrate by the plurality of pads; and cast on the wafer and A filling material between the substrates; wherein 'the middle region of the substrate surface is a region corresponding to the covering wafer, and the plurality of pads are located in the region corresponding to the covering wafer, and a region is formed in the region corresponding to the covering wafer; Through-holes, whereby the filling material can be cast simultaneously from the entire periphery of the wafer, allowing it to flow inwardly through the area corresponding to the covered wafer with excellent fluidity, which can effectively pass the air between the substrate and the wafer from the through-hole. The holes are driven away without creating voids. 2. The flip-chip package structure as described in item 1 of the scope of the patent application, wherein the bump electrodes of the wafer are distributed on the bottom edge and the pads of the substrate are located on the edge of the area corresponding to the covered wafer. 3. The flip-chip packaging structure described in item 丨 of the patent application scope, wherein the plurality of adhesives are non-conductive. 4. A flip-chip packaging process, which connects a wafer with a plurality of bump electrodes on its bottom surface to a substrate, wherein the middle area of the substrate surface is a region corresponding to the covered wafer, and the region corresponding to the covered wafer is within ______10 (CNS) A4 # Lfr {210 X 2974 ^ ¾) I-(please note the $ item on the back of the ## before filling in this education) Threading the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, printed the intellectual property of the Ministry of Economy Printed by the Bureau ’s Consumer Cooperative 14 32 6 5 3 g8 _ DS VI. The scope of the patent application has a plurality of pads corresponding to the bump electrodes, respectively, and a through hole is formed in the center of the corresponding area covering the wafer The packaging process includes the following steps: applying adhesive to the area inside the pads on the substrate; immersing the plurality of bump electrodes of the wafer into the conductive glue and taking them out, so that the ends of each bump electrode The substrate is covered with conductive adhesive; the wafer is placed on the substrate so that the plurality of bump electrodes are respectively aligned with the plurality of pads of the substrate, and the corresponding bump electrodes and the pads are adhered by the conductive adhesive. Together; heating and curing, so that the wafer and the substrate can be firmly bonded together due to the relationship between the conductive adhesive and the adhesive; and the filling material is simultaneously cast from the entire periphery or one side of the wafer so that it passes through the corresponding covering The area of the wafer flows inward with excellent fluidity to cover the entire area, and the air between the substrate and the wafer can be effectively driven away by the through hole without generating a gap. 5. The flip-chip packaging process as described in item 4 of the scope of the patent application, wherein the adhesive is applied in a dot matrix manner over the entire area of the corresponding covered wafer. 6_ The flip-chip packaging process described in item 4 of the scope of patent application, wherein the plurality of adhesives are non-conductive. 11 This paper uses the national standard (CNS) A4 size of the paper (210X297 mm) ---------% ------ order .------- lacquer f · ( (Please read the notes on the back before filling in this tile)
TW88121289A 1999-12-06 1999-12-06 Flip chip package structure and process with increased encapsulation efficiency and reliability TW432653B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
CN114641150A (en) * 2022-03-25 2022-06-17 深圳市兆兴博拓科技股份有限公司 Circuit board mounting method based on dispensing optimization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
CN114641150A (en) * 2022-03-25 2022-06-17 深圳市兆兴博拓科技股份有限公司 Circuit board mounting method based on dispensing optimization

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