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TW430994B - FET with source-substrate terminal and its production method - Google Patents

FET with source-substrate terminal and its production method

Info

Publication number
TW430994B
TW430994B TW087121524A TW87121524A TW430994B TW 430994 B TW430994 B TW 430994B TW 087121524 A TW087121524 A TW 087121524A TW 87121524 A TW87121524 A TW 87121524A TW 430994 B TW430994 B TW 430994B
Authority
TW
Taiwan
Prior art keywords
semiconductor
source
fet
layer
substrate terminal
Prior art date
Application number
TW087121524A
Other languages
Chinese (zh)
Inventor
Jenoe Tihanyi
Wolfgang Werner
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW430994B publication Critical patent/TW430994B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

This invention relates to a FET with source-substrate terminal and trench-gate (8) (Source-Down-FET), in which a drain-area (5) of the 1st conductive type is provided on a surface of a semiconductor-layer (3) of the 1st conductive type, said semiconductor-layer (3) is arranged on a semiconductor-substrate (1) of the 1st conductive type. Said trench-gate (8) basically goes through said semiconductor-layer (3), where a source-area (11) of the 1st conductive type is provided on the end of a trench (8) on the other surface of said semiconductor-layer (3) and semiconductor-areas (6, 7) of the 2nd conductive type are located in the region near said trench (8) on the other surface of said semiconductor-layer (3), the surface of said semiconductor-areas (6, 7) together with the surfaces of said source-area (11) form the other surface of said semiconductor-layer (3).
TW087121524A 1998-01-15 1998-12-23 FET with source-substrate terminal and its production method TW430994B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19801313A DE19801313C2 (en) 1998-01-15 1998-01-15 FET with source-substrate connection

Publications (1)

Publication Number Publication Date
TW430994B true TW430994B (en) 2001-04-21

Family

ID=7854702

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087121524A TW430994B (en) 1998-01-15 1998-12-23 FET with source-substrate terminal and its production method

Country Status (6)

Country Link
EP (1) EP0966764A1 (en)
JP (1) JP2001515663A (en)
KR (1) KR100443976B1 (en)
DE (1) DE19801313C2 (en)
TW (1) TW430994B (en)
WO (1) WO1999036964A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4774586B2 (en) * 1999-10-21 2011-09-14 富士電機株式会社 Manufacturing method of semiconductor device
DE10004984A1 (en) 2000-02-04 2001-08-16 Infineon Technologies Ag Vertical semiconductor device with source-down design and corresponding manufacturing process
DE10042226B4 (en) * 2000-08-28 2014-12-24 Infineon Technologies Ag Source-down power MOSFET and method of making the same
US6455905B1 (en) * 2001-04-05 2002-09-24 Ericsson Inc. Single chip push-pull power transistor device
DE10239310B4 (en) * 2002-08-27 2005-11-03 Infineon Technologies Ag Method for producing an electrically conductive connection between a first and a second buried semiconductor layer
JP2005150686A (en) * 2003-10-22 2005-06-09 Sharp Corp Semiconductor device and manufacturing method thereof
US7947569B2 (en) 2008-06-30 2011-05-24 Infineon Technologies Austria Ag Method for producing a semiconductor including a foreign material layer
US7943449B2 (en) * 2008-09-30 2011-05-17 Infineon Technologies Austria Ag Semiconductor component structure with vertical dielectric layers
US8519473B2 (en) * 2010-07-14 2013-08-27 Infineon Technologies Ag Vertical transistor component

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62159468A (en) * 1986-01-08 1987-07-15 Tdk Corp semiconductor equipment
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
JP3291958B2 (en) * 1995-02-21 2002-06-17 富士電機株式会社 Back source MOSFET
DE19638439C2 (en) * 1996-09-19 2000-06-15 Siemens Ag Vertical semiconductor device controllable by field effect and manufacturing process

Also Published As

Publication number Publication date
KR100443976B1 (en) 2004-08-09
JP2001515663A (en) 2001-09-18
WO1999036964A1 (en) 1999-07-22
DE19801313C2 (en) 2001-01-18
KR20000076284A (en) 2000-12-26
DE19801313A1 (en) 1999-07-22
EP0966764A1 (en) 1999-12-29

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees