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TW428325B - Method of forming metal oxide semiconductor field effect transistor - Google Patents

Method of forming metal oxide semiconductor field effect transistor

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Publication number
TW428325B
TW428325B TW88117481A TW88117481A TW428325B TW 428325 B TW428325 B TW 428325B TW 88117481 A TW88117481 A TW 88117481A TW 88117481 A TW88117481 A TW 88117481A TW 428325 B TW428325 B TW 428325B
Authority
TW
Taiwan
Prior art keywords
drain
gate
dielectric layer
source
layer
Prior art date
Application number
TW88117481A
Other languages
Chinese (zh)
Inventor
Jian-Ting Lin
Jin-Lai Chen
Jr-Wen Jou
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW88117481A priority Critical patent/TW428325B/en
Application granted granted Critical
Publication of TW428325B publication Critical patent/TW428325B/en

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Abstract

This invention is about method of forming metal oxide semiconductor field effect transistor, in which the metal oxide semiconductor field effect transistor is formed by a specific procedure so as to effectively control thermal damage during the fabrication process. This invention at least includes the following procedures. At first, a substrate is provided, on which the isolation and well regions are formed. The first dielectric layer, conduction layer and antireflection layer are sequentially formed on the substrate. The photolithography and etching process are used to form a gate. After forming the source, drain and spacer, thermal process is performed onto source and drain such that the first metal silicide is formed on source and drain. The second dielectric layer is used to cover substrate and gate. The surface of the second dielectric layer is planarized such that the antireflection layer of gate is completely stripped and the conduction layer of gate is partly stripped off. After forming the second metal silicide on the conduction layer, the spacer is removed and, the lining pad and doped source/drain are formed. Finally, the third dielectric layer is formed on the second dielectric layer to cover gate. Apparently, the great characteristic of this invention is that the doped source/drain and lining pad are formed after a series of thermal process have been performed. Therefore, the influence of thermal process on doped source/drain and lining pad, such as deposition and so on, can be effectively avoided.
TW88117481A 1999-10-11 1999-10-11 Method of forming metal oxide semiconductor field effect transistor TW428325B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88117481A TW428325B (en) 1999-10-11 1999-10-11 Method of forming metal oxide semiconductor field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88117481A TW428325B (en) 1999-10-11 1999-10-11 Method of forming metal oxide semiconductor field effect transistor

Publications (1)

Publication Number Publication Date
TW428325B true TW428325B (en) 2001-04-01

Family

ID=21642577

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88117481A TW428325B (en) 1999-10-11 1999-10-11 Method of forming metal oxide semiconductor field effect transistor

Country Status (1)

Country Link
TW (1) TW428325B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680514B (en) * 2018-08-21 2019-12-21 南亞科技股份有限公司 Transistor device and method for preparing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680514B (en) * 2018-08-21 2019-12-21 南亞科技股份有限公司 Transistor device and method for preparing the same
US10903080B2 (en) 2018-08-21 2021-01-26 Nanya Technology Corporation Transistor device and method for preparing the same
US11482419B2 (en) 2018-08-21 2022-10-25 Nanya Technology Corporation Method for preparing transistor device

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Legal Events

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GD4A Issue of patent certificate for granted invention patent