7008 A7 B7 五、發明說明（（） 本發明是有關於一種具有T形閘極的製造方法，且特 別是有關於一種形成複晶矽間隙壁，以形成T形閘極的方 法。 在半導體積體電路的製程中，閘極的品質對於元件的 效能具有很大的影響。尤其是在深次微米(Deep Sub-Micron) 積體電路的製程中，閘極的電阻値將因爲閘極的寬度減小 而昇高，因此製作閘極的材質就必須具有相當良好的電氣 性質。由於以複晶矽與金屬矽化物所組成的多晶矽化物金 屬（Polycide)具有較複晶矽爲佳的導電性，且其與常用作介 電層的氧化物之間具有較佳的附著力，因此常被用爲形成 閘極的材質。 第1A圖至第1C圖繪示習知一種製造具有多晶矽化物 金屬之閘極的剖面流程圖。 請參照第1A圖，在已經形成有隔離結構102的基底100 上形成閘氧化層106與複晶矽層108。接著，於基底100 中形成輕摻雜汲極結構l〇4(Lightly Doped Drain ; LDD)。 其中，閘氧化層106與複晶矽層108共同組成閘極結構 110° 請參照第1B圖，形成間隙壁112緊接於閘極結構110 的側壁，並且於基底100中形成源極/汲極區114。形成與 基底100共形的金屬層116覆蓋源極/汲極區114、間隙壁 112以及複晶矽層108。 請參照第1C圖，進行加熱製程，以使部分的金屬層 116(繪示於第1B圖中）與部分的複晶矽層108以及源極/汲 3 --^--^-----III I -------—訂-------1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印4,,农 4.26892 4785twf.doc/008 A7 --- ---B7_____— 五、發明說明（1 ) 極區II1的表面進行反應，以形成金屬矽化物層118。其 中’金屬矽化物層118與複晶矽層108共同組成多晶矽化 物金屬層120。移除未與複晶矽層1〇8反應的金屬層116 ’ 以完成電晶體的製作。 在深次微米積體電路的製程中，以上述方法所形成之 閘極結構的寬度相當小（大約爲〇.〗微米），因此閘極結構 本身的電阻値相當大。而閘極結構與連接於閘極結構的導 體插塞之間的接觸電阻，也因爲之間的接觸面積減小而變 大。不論是閘極結構本身的電阻或是閘極結構與導體插塞 之間的接觸電阻都會對元件的操作速度造成影響。 此外，在進行加熱製程以形成金屬矽化物層時，複晶 矽層的結晶情形將對所形成之金屬矽化物層的品質有相當 大的影響。由於閘極結構的寬度較小，因此所形成之金屬 砂化物層很可能會因爲發生結塊現象（Agglomeration)，導 致鬧極結構的窄線效應(Narrow Line Effect)，甚至於斷線 的現象。 因此’本發明提供一種具有T形閘極之電晶體的製造 方法，可以有效的降低閘極結構本身的電阻値，並且同時 降低閘極結構與導體插塞之間的接觸電阻。此外，本發明 的方法也可以加大進行形成金屬矽化物層之加熱製程的溫 度區間，以避免結塊現象所造成之窄線效應或是斷線的問 題。 本發明提供一種具有T形閘極之電晶體的製造方法， 在已形成有隔離結構的基底上形成閘氧化層與複晶矽層。 κ Μ ------— ί — — ί — — 1請先闓讀之注意事項再填寫本頁) 本紙張尺漫適闬中國國家標準（CKS)A4規輅（2〗〇χ 297公g ) 1 42689 2 4785twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作杜印絜 五、發明說明（> ) 於複晶矽層兩側的基底中形成輕摻雜汲極結構’並且於輕 摻雜汲極結構周圍的基底中形成口袋摻雜區（pkt Implantation)。形成介電層全面覆蓋基底之後，進行回蝕 刻步驟以移除複晶矽層上方的介電層，並使介電層的表面 低於複晶矽層的上表面。於介電層上形成複晶矽間隙壁緊 接於複晶矽層突出於介電層的側壁。以複晶矽層與複晶矽 間隙壁爲罩幕，對介電層進行回蝕刻步驟，以於複晶矽間 隙壁下方形成介電層間隙壁。於基底中形成源極/汲極區， 並且進行回火步驟以調整源極/汲極區的晶格排列。進行 離子植入步驟以使複晶矽間隙壁與部分的複晶矽層變質爲 非晶矽間矽壁與非晶矽層。形成與基底共形的金屬層，並 且進行加熱製程以使部分的金屬層與非晶矽間隙壁與非晶 矽層反應，以形成金屬矽化物層。之後，以濕式蝕刻法去 除未與非晶矽間隙壁與非晶矽層反應的金屬層°由於金屬 矽化物層與複晶矽層共同組成電晶體的閘極，而且金屬矽 化物層的寬度大於複晶矽層的寬度，因此稱爲Τ形閘極。 本發明的特徵爲形成複晶矽間隙壁緊接於複晶矽層， 並使複晶矽間隙壁與部分的複晶矽層變質爲非晶矽間隙壁 與非晶矽層之後，與金屬層反應形成金屬矽化物層。由於 複晶砂層與金屬矽化物層共同組成閘極結構，因此所形成 之閘極爲Τ形。由於Τ形閘極具有較大的截面積，因此Τ 形閘極本身的電阻値較低。此外，由於τ形閘極具有較大 的上表面，因此Τ形閘極與後續製程中所形成之導體插塞 之間的接觸電阻較低。 5 1.11----..---------裝·！-----訂---------線 I ' (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297 公t ) 經濟部智慧財產局員工消費合作社印製 426892 4785twf.doc/008 五、發明說明（（A ) 另一方面，由於形成T形閘極之金屬砂化物層時，金 屬層是與寬度較寬的非晶矽進行反應，因此比較不會發生 結塊現象D在進行加熱製程時的溫度會有比較大的容許範 Μ。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下= 圖式之簡單說明： 第1Α圖至第1C圖繪示習知一種製造具有多晶矽化物 金屬之閘極的剖面流程圖；以及 第2Α圖至第2G圖繪示依照本發明知一較佳實施例， 一種具有Τ形閘極之電晶體的製造方法的流程剖面圖。 圖式標記說明： 100 ' 200 ：基底 102、202 :隔離結構 104、208 :輕摻雜汲極結構 106、204 :閘氧化層 108 ' 206 :複晶矽層 110 :閘極結構 112 :間隙壁 114 ' 218 :源極/汲極區 116、220 :金屬層 118、222 :金屬矽化物層 120、224 :多晶矽化物金屬層 6 ---„---J---------裝 -------訂---------線 (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 426892 4 7 8 5 twf.d〇c/ 0 0 8_逆 五、發明說明（g ) 206a :非晶砂層 210 : 口袋摻雜區 212 :介電層 214 :複晶矽間隙壁 214a :非晶矽間隙壁 216 :介電層間隙壁 226 : T形閘極 實施例 請參照第2A圖’在已經形成有隔離結構202的基底2〇〇 上形成閘氧化層204與複晶矽層206。其中，複晶矽層2〇6 的材質比如爲經過摻雜的複晶矽。接著，於複晶矽層206 兩側的基底200中形成輕摻雜汲極區208，並且於輕摻雜 汲極區2〇8周圍的基底2〇0中形成口袋摻雜區210。其中， 形成輕摻雜汲極區208的方法比如爲將與基底200具有相 反電性的離子植入基底200中，而形成口袋摻雜區210的 方法則比如爲將與基底2〇〇具有相同電性的離子植入基底 200中。口袋摻雜區210的作用在於降低短通道效應（Short Channel Effect)。 請參照第2B圖，形成介電層212全面覆蓋基底200， 並且移除部分的介電層212,以使介電層212的表面低於 複晶矽層206的表面。其中，形成介電層212的方法比如 爲利用常壓化學氣相沉積法(Atmosphere Pressure Chemical Vapor Deposition ; APCVD)沉積大約 6000 埃至 8000 埃的 氧化物。使介電層212之表面低於複晶矽層206之表面的 7 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公爱） 111·--r>----------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 426892 五、發明說明（4) 方法比如爲先以化學機械硏磨法（Chemical-Mechanical P〇丨ishing; CMP)將介電層212的表面硏磨至與複晶矽層 206的表面具有相同高度，再進行回蝕刻步驟，移除部分 的介電層212，以使介電層212的表面低於複晶矽層206 的表面。 請參照第2C圖，於介電層212上形成複晶矽間隙壁214 緊接於複晶矽層突出於介電層212的側壁。其中，形 成複晶矽間隙壁214的方法包括先沉積厚度大約爲300埃 至1000埃，且與基底200共形之經過摻雜的複晶矽層(未 繪示於圖中），再進行回蝕刻步驟，移除部分的複晶矽層， 以形成複晶矽間隙壁214。 請參照第2D圖，移除部分的介電層212(繪示於第2C 圖中）以及部分的閘氧化層204，以於複晶矽間隙壁214下 方形成介電層間隙壁216。形成介電層間隙壁216的方法 比如爲複晶矽層206與複晶矽間隙壁214爲蝕刻罩幕，進 行回蝕刻步驟。接著，於基底200中形成源極/汲極區218。 形成源極/汲極區218的方法比如爲先以複晶矽層206與複 晶矽間隙壁214爲罩幕，對基底200進行離子植入步驟， 再進行回火製程，以調整源極/汲極區218的晶格排列 其中，此進行此回火製程的方法比如爲以大約攝氏900度 至1100度的溫度進行大約5秒至15秒的回火製程。 請參照第2E圖，進行另一次的離子植入步驟，使複 晶矽間隙壁214與部分的複晶矽層206變質爲非晶矽間隙 壁214a與非晶矽層206a。使複晶矽變質爲非晶矽的方法 8 - — l·— — —* — ! — —------I -----^ » ----I--- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中S國家標準（CNS)A4規格（210χ 297公釐） 426892 4785twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明〇 ) 比如爲以大約25KeV至35KeV的能量植入劑量爲ι〇Μ的 砷（As)離子。 請參照第2F圖，形成與基底200共形的金屬層220， 並且進行加熱製程以使部分的金屬層22〇與非晶矽間隙壁 (繪示於第2E圖中）與部分的非晶矽層206a(繪示於第 2E圖中）反應，以形成金屬矽化物層222。形成金屬層220 的方法比如爲沉積厚度大約爲250埃至350埃的鈦(Ti)或 鈷(Co)。形成金屬矽化層22〇的加熱製程比如爲兩階段的 回火製程。其中，第一階段的回火製程比如爲在充滿氨氣 的環境中，以大約攝氏600度至700度的高溫進行大約25 秒至35秒。進行第一階段之回火製程的目的在於使金屬 層22〇與複晶矽反應生成金屬矽化物。第二階段的回火製 程比如爲在充滿氨氣的環境中以大約攝氏750度至850度 的溫度進行大約15秒至25秒。此第二階段之回火製程的 目的在於改變金屬矽化物的結晶型態，以改善金屬矽化物 的導電性。由於金屬矽化物層222與複晶矽層206共同構 成的多晶矽化物金屬層224是作爲電晶體的閘極，且金屬 矽化物層222的寬度大於複晶矽層206,因此所形成之電 晶體具有T形閘極226。 請參照第2G圖，移除未與非晶矽間隙壁214a與非晶 矽層206a反應的金屬層22〇(繪示於第2F圖中）。移除金 屬層220的方法比如爲以氫氧化銨（NH4OH)、過氧化氫 (H202)與去離子水以大約1 : 1 : 4的比例混合而成的溶液 在大約攝氏65度至75度的溫度下進行濕式回蝕刻。 9 ^ (請先閱讀背面之注意事項再填寫本頁) ί Γ 惠· ί 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 426892 A7 4785twf.doc/008 ____B7_____ 五、發明說明（2 ) 本發明的特徵爲形成複晶矽間隙壁緊接於複晶矽層之 側壁’並使複晶矽間隙壁與部分的複晶矽層變質爲非晶砂 間隙壁與非晶矽層之後，與金屬層反應形成金屬矽化物 層。由於複晶矽層與金屬矽化物層共同組成閘極結構，因 此所形成之閘極爲τ形。由於τ形閘極具有較大的截面積， 因此T形閘極本身的電阻値較低。此外，由於T形閘極具 有較大的上表面’因此T形閘極與後續製程中所形成之導 體插塞之間的接觸電阻較低。 另一方面，‘由於形成T形閘極之金屬矽化物層時，金 屬層是與寬度較寬的非晶矽進行反應，因此比較不會發生 結塊現象。在進行加熱製程時的溫度會有比較大的容許範 圍。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾。因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 I ^—r I ί I-------i 111111 訂 ------I-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐）7008 A7 B7 V. Description of the invention (() The present invention relates to a manufacturing method with a T-shaped gate, and in particular to a method of forming a polycrystalline silicon spacer to form a T-shaped gate. In the manufacturing process of the bulk circuit, the quality of the gate has a great influence on the performance of the device. Especially in the process of the deep sub-micron integrated circuit, the resistance of the gate will be affected by the width of the gate. Reduce and increase, so the material used to make the gate must have fairly good electrical properties. Since polycide composed of polycrystalline silicon and metal silicide has better conductivity than polycrystalline silicon, And it has better adhesion to the oxide commonly used as a dielectric layer, so it is often used as the material for forming the gate. Figures 1A to 1C show a conventional method for manufacturing a gate with polycrystalline silicide metal. A cross-sectional flowchart of the electrode. Referring to FIG. 1A, a gate oxide layer 106 and a polycrystalline silicon layer 108 are formed on the substrate 100 on which the isolation structure 102 has been formed. Next, a lightly doped drain structure is formed in the substrate 100. 4 ( Lightly Doped Drain; LDD). Among them, the gate oxide layer 106 and the polycrystalline silicon layer 108 together form a gate structure 110 °. Referring to FIG. 1B, a gap wall 112 is formed next to the side wall of the gate structure 110 and on the substrate 100. A source / drain region 114 is formed in the substrate. A metal layer 116 conforming to the substrate 100 is formed to cover the source / drain region 114, the spacer 112, and the polycrystalline silicon layer 108. Referring to FIG. 1C, a heating process is performed to Part of the metal layer 116 (shown in Figure 1B) and part of the polycrystalline silicon layer 108 and the source / drain 3-^-^ ----- III I --------- Order ------- 1 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) ) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4, Agricultural 4.26892 4785twf.doc / 008 A7 --- --- B7_____-V. Description of the invention (1) The surface of the polar region II1 reacts to form a metal silicide layer 118. Among them, the metal silicide layer 118 and the polycrystalline silicon layer 108 together form a polycrystalline silicide metal layer 120. The uncoated polycrystalline silicon layer 1 is removed. 8 reaction metal layer 116 'to complete the production of the transistor. In the process of deep sub-micron integrated circuit, the width of the gate structure formed by the above method is quite small (about 0. 〖micron), so the gate The resistance of the structure itself is quite large. The contact resistance between the gate structure and the conductor plug connected to the gate structure is also increased because the contact area between them is reduced. Whether it is the resistance of the gate structure itself or It is the contact resistance between the gate structure and the conductor plug that will affect the operating speed of the element. In addition, when the heating process is performed to form the metal silicide layer, the crystallization of the polycrystalline silicon layer will have a considerable influence on the quality of the formed metal silicide layer. Due to the small width of the gate structure, the metal sand layer formed is likely to cause agglomeration, resulting in the narrow line effect of the anode structure, or even the phenomenon of disconnection. Therefore, the present invention provides a method for manufacturing a transistor having a T-gate, which can effectively reduce the resistance of the gate structure itself, and at the same time reduce the contact resistance between the gate structure and the conductor plug. In addition, the method of the present invention can also increase the temperature interval of the heating process for forming the metal silicide layer to avoid the problem of narrow line effects or disconnection caused by the agglomeration phenomenon. The invention provides a method for manufacturing a transistor having a T-shaped gate electrode. A gate oxide layer and a polycrystalline silicon layer are formed on a substrate on which an isolation structure has been formed. κ Μ ------— ί — ί — — 1 Please read the precautions before filling this page) This paper ruler is suitable for China National Standard (CKS) A4 Regulations (2) 〇χ 297 公g) 1 42689 2 4785twf.doc / 008 A7 B7 Consumer cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs, Du Yin 絜 5. Description of the invention (&); forming lightly doped drain structures in the substrate on both sides of the polycrystalline silicon layer 'and A pocket doped region (pkt implantation) is formed in the substrate around the lightly doped drain structure. After the dielectric layer is formed to completely cover the substrate, an etch-back step is performed to remove the dielectric layer above the polycrystalline silicon layer, and the surface of the dielectric layer is lower than the upper surface of the polycrystalline silicon layer. A polycrystalline silicon spacer is formed on the dielectric layer next to the side wall of the polycrystalline silicon layer protruding from the dielectric layer. Using the polycrystalline silicon layer and the polycrystalline silicon spacer as a mask, the dielectric layer is etched back to form a dielectric layer spacer below the polycrystalline silicon spacer. A source / drain region is formed in the substrate, and a tempering step is performed to adjust a lattice arrangement of the source / drain region. An ion implantation step is performed to modify the polycrystalline silicon spacer and part of the polycrystalline silicon layer into an amorphous intercrystalline silicon wall and an amorphous silicon layer. A metal layer conforming to the substrate is formed, and a heating process is performed to cause a part of the metal layer to react with the amorphous silicon spacer and the amorphous silicon layer to form a metal silicide layer. After that, the metal layer that does not react with the amorphous silicon spacer and the amorphous silicon layer is removed by wet etching. The metal silicide layer and the polycrystalline silicon layer together form the gate of the transistor, and the width of the metal silicide layer It is larger than the width of the polycrystalline silicon layer, so it is called a T-shaped gate. The invention is characterized in that a polycrystalline silicon spacer is formed next to the polycrystalline silicon layer, and the polycrystalline silicon spacer and a part of the polycrystalline silicon layer are modified into an amorphous silicon spacer and an amorphous silicon layer, and then the metal layer is formed. The reaction forms a metal silicide layer. Since the complex sand layer and the metal silicide layer together form the gate structure, the gate formed is T-shaped. Because the T-gate has a larger cross-sectional area, the resistance of the T-gate itself is lower. In addition, because the τ-shaped gate has a large upper surface, the contact resistance between the T-shaped gate and the conductor plug formed in the subsequent process is low. 5 1.11 ----..--------- installed! ----- Order --------- Line I '(Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (21〇χ 297 mm t ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 426892 4785twf.doc / 008 V. Description of the invention ((A) On the other hand, when the metal sanding layer of the T-shaped gate is formed, the metal layer has a wider width Amorphous silicon reacts, so the agglomeration phenomenon is less likely to occur. D The temperature during the heating process will have a relatively large allowable range M. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable In the following, the preferred embodiment will be given in detail, and will be described in detail in conjunction with the accompanying drawings. = Brief description of the drawings: Figures 1A to 1C show a conventional cross-sectional process of manufacturing a gate with polysilicon silicide metal. And FIGS. 2A to 2G are cross-sectional views showing the flow of a method for manufacturing a transistor with a T-shaped gate according to a preferred embodiment of the present invention. The illustration of the drawing marks: 100 '200: substrate 102 , 202: Isolation structure 104, 208: Lightly doped Electrode structure 106, 204: gate oxide layer 108 '206: polycrystalline silicon layer 110: gate structure 112: spacer 114' 218: source / drain region 116, 220: metal layer 118, 222: metal silicide layer 120, 224: Polycrystalline silicide metal layer 6 -------------------------------------------- Order (Please read first Note on the back, please fill out this page again) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 426892 4 7 8 5 twf.d〇c / 0 0 8_Inverse five, description of the invention ( g) 206a: amorphous sand layer 210: pocket doped region 212: dielectric layer 214: polycrystalline silicon spacer 214a: amorphous silicon spacer 216: dielectric layer spacer 226: T-shaped gate FIG. 2A 'A gate oxide layer 204 and a polycrystalline silicon layer 206 are formed on a substrate 200 on which an isolation structure 202 has been formed. The material of the polycrystalline silicon layer 206 is, for example, doped polycrystalline silicon. Then A lightly doped drain region 208 is formed in the substrate 200 on both sides of the polycrystalline silicon layer 206, and a pocket doped region 210 is formed in the substrate 2000 around the lightly doped drain region 208. Among them, Method of lightly doped drain region 208 For example, to implant ions having opposite electrical properties from the substrate 200 into the substrate 200, a method of forming the pocket doped region 210 is to implant ions having the same electrical properties as the substrate 200 into the substrate 200. Pocket doping The role of the miscellaneous region 210 is to reduce the Short Channel Effect. Referring to FIG. 2B, a dielectric layer 212 is formed to completely cover the substrate 200, and a portion of the dielectric layer 212 is removed, so that the surface of the dielectric layer 212 is lower than the surface of the polycrystalline silicon layer 206. Among them, the method for forming the dielectric layer 212 is, for example, depositing an oxide of about 6000 angstroms to 8000 angstroms using an atmospheric pressure chemical vapor deposition (APCVD) method. Make the surface of the dielectric layer 212 lower than the surface of the polycrystalline silicon layer 206. This paper size applies the Chinese National Standard (CNS) A4 specification (210x297). 111 · --r > --------- ------- Order --------- (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 426892 V. Description of the invention (4) The method is, for example, honing the surface of the dielectric layer 212 to the same height as the surface of the polycrystalline silicon layer 206 by chemical-mechanical honing (CMP); Then, an etch-back step is performed to remove a portion of the dielectric layer 212 so that the surface of the dielectric layer 212 is lower than the surface of the polycrystalline silicon layer 206. Referring to FIG. 2C, a polycrystalline silicon spacer 214 is formed on the dielectric layer 212, and is next to the sidewall of the polycrystalline silicon layer protruding from the dielectric layer 212. The method for forming the polycrystalline silicon spacer 214 includes firstly depositing a doped polycrystalline silicon layer (not shown in the figure) having a thickness of about 300 angstroms to 1,000 angstroms and conforming to the substrate 200, and then back In the etching step, a part of the polycrystalline silicon layer is removed to form a polycrystalline silicon spacer 214. Referring to FIG. 2D, a portion of the dielectric layer 212 (shown in FIG. 2C) and a portion of the gate oxide layer 204 are removed to form a dielectric layer spacer 216 below the polycrystalline silicon spacer 214. A method of forming the dielectric spacer 216 is, for example, the polycrystalline silicon layer 206 and the polycrystalline silicon spacer 214 as an etching mask, and the etch-back step is performed. Next, a source / drain region 218 is formed in the substrate 200. The method of forming the source / drain region 218 is, for example, using the polycrystalline silicon layer 206 and the polycrystalline silicon spacer 214 as a mask, performing an ion implantation step on the substrate 200, and then performing a tempering process to adjust the source / drain region. The lattice of the drain region 218 is arranged. The method of performing the tempering process is, for example, performing a tempering process at a temperature of about 900 to 1100 degrees Celsius for about 5 seconds to 15 seconds. Referring to FIG. 2E, another ion implantation step is performed to modify the polycrystalline silicon spacer 214 and a part of the polycrystalline silicon layer 206 into an amorphous silicon spacer 214a and an amorphous silicon layer 206a. Method for modifying polycrystalline silicon to amorphous silicon 8-— l · — — — * —! — —------ I ----- ^ »---- I --- (Please read first Note on the back, please fill in this page again.) This paper size is applicable to S National Standard (CNS) A4 specification (210 x 297 mm) 426892 4785twf.doc / 008 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 〇) For example, implant arsenic (As) ions at a dose of ΙΟΜ at an energy of about 25 KeV to 35 KeV. Referring to FIG. 2F, a metal layer 220 conforming to the substrate 200 is formed, and a heating process is performed so that part of the metal layer 22 and the amorphous silicon spacer (shown in FIG. 2E) and part of the amorphous silicon are heated. The layer 206a (shown in FIG. 2E) reacts to form a metal silicide layer 222. The method of forming the metal layer 220 is, for example, depositing titanium (Ti) or cobalt (Co) with a thickness of about 250 to 350 angstroms. The heating process for forming the metal silicide layer 22 is, for example, a two-stage tempering process. Among them, the first-stage tempering process is performed in an ammonia-filled environment at a high temperature of about 600 to 700 degrees Celsius for about 25 seconds to 35 seconds, for example. The purpose of the first stage of the tempering process is to make the metal layer 22 and the polycrystalline silicon react to form a metal silicide. The second-stage tempering process is performed, for example, in an ammonia-filled environment at a temperature of about 750 ° C to 850 ° C for about 15 seconds to 25 seconds. The purpose of this second stage tempering process is to change the crystalline form of the metal silicide to improve the conductivity of the metal silicide. Since the metal silicide layer 222 and the polycrystalline silicon layer 206 together constitute a polycrystalline metal silicide layer 224 as a gate of the transistor, and the width of the metal silicide layer 222 is larger than that of the polycrystalline silicon layer 206, the formed transistor has T-shaped gate 226. Referring to FIG. 2G, the metal layer 22 (not shown in FIG. 2F) that has not reacted with the amorphous silicon spacer 214a and the amorphous silicon layer 206a is removed. The method for removing the metal layer 220 is, for example, a solution prepared by mixing ammonium hydroxide (NH4OH), hydrogen peroxide (H202) and deionized water at a ratio of about 1: 1: 4: about 65 to 75 degrees Celsius. Wet etch-back at temperature. 9 ^ (Please read the notes on the back before filling this page) ί Γ Hui · ί The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 426892 A7 4785twf.doc / 008 ____B7_____ V. Invention Explanation (2) The present invention is characterized in that a polycrystalline silicon spacer is formed next to the side wall of the polycrystalline silicon layer, and the polycrystalline silicon spacer and a part of the polycrystalline silicon layer are modified into an amorphous sand barrier and an amorphous silicon. After the layer, it reacts with the metal layer to form a metal silicide layer. Since the polycrystalline silicon layer and the metal silicide layer together form a gate structure, the gate formed is τ-shaped. Because the τ-shaped gate has a large cross-sectional area, the resistance of the T-shaped gate itself is low. In addition, since the T-gate has a large upper surface ', the contact resistance between the T-gate and the conductor plug formed in the subsequent process is low. On the other hand, 'When forming a metal silicide layer of a T-shaped gate, the metal layer reacts with a wide width of amorphous silicon, so agglomeration is less likely to occur. The temperature during the heating process will have a relatively large allowable range. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. I ^ —r I ί I ------- i 111111 Order ------ I-- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to the national standard (CNS) A4 specification (210 X 297 mm)