TW425634B - Method for preventing the loss of ions in MOS manufacturing process - Google Patents

Abstract

The present invention provides a method for manufacturing PMOS by preventing the loss of born boron. The manufacturing process of the present invention comprises: first, providing a semiconductor substrate having at least STI regions, and forming a gate oxide layer on the substrate; forming a polysilicon layer on the gate oxide layer; implanting ions into the polysilicon layer; depositing a silicon oxynitride layer on the polysilicon layer, wherein the silicon oxynitride layer is used as an anti-reflective layer; forming a photoresist layer on the silicon oxynitride layer; pattern-etching the silicon oxynitride layer and the polysilicon layer to form a gate region; depositing a dielectric layer on the gate region after lightly doping drain region; using anisotropic etching method to etch the silicon oxynitride layer, so as to form a spacer on the side wall of the gate; then, performing a heavy doping process to form a source/drain; and finally, performing an annealing process.

Description

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5 ~ l Field of the invention: The present invention relates to a method for generating PMOS used in the manufacturing of semiconductor devices. In particular, it relates to a method for preventing boron loss to generate pM0s. Background of the invention: When the density of integrated circuits is continuously expanding At the same time, in order to keep the area of the chip (chip) the same, or even shrink, so as to continuously reduce the unit cost of the circuit, the only way is to continuously reduce the design rule of the circuit (design rule). And when the size of the component is reduced, the junction surface in the source / drain must be shallower to avoid short-channel effects. Therefore, we must use low energy, high dose boron ions (boron or boron fluoride) when implanting lightly doped drain electrodes at the PM0s interface. However, during the tempering process to restore the crystal structure on the surface of the Shi Xi wafer, boron easily flows to the surface oxide layer, so that the boron ions implanted in the source / drain electrode are lost in the silicon wafer, which reduces the boron ions. Its concentration near the surface causes an increase in the source / drain resistance and a decrease in the driving current (ID, SAT), thereby reducing the efficiency of the semiconductor device. Purpose and summary of the invention:

Page 4 A2563 4 V. Description of the invention (2) In the background of the above invention, there are many shortcomings of the traditional method of generating PMOS. The present invention provides a process to solve the problem of traditional generation of PMos. It is to provide a method for generating pMOS by forming silicon nitride on the side wall of the gate to form a compensating gap wall, and using silicon nitride to hinder the loss of the inserted ions. Another object of the present invention is to provide a method for generating a PMOS, and reduce the source / drain resistance and increase the driving current. This is because in the subsequent tempering process, the implanted boron ions easily flow to the oxide layer and reduce the concentration near the surface, resulting in an increase in the source / drain resistance and a decline in the driving current (ID, SAT). By this manufacturing method, the concentration of boron ions close to the surface can be maintained, resulting in a low resistance value (ID'SAT) of the source / drain electrode, thereby improving the performance of the semiconductor device. Another object of the present invention is to provide a method for generating pms, and effectively reduce overlapping capacitance (Cgd), so as to reduce RC time delay ′ and thereby improve the efficiency of the semiconductor device. In one embodiment of the present invention, a polycrystalline silicon layer is formed on the semiconductor substrate in the isolation (STI) region in the gate oxide, and then a silicon oxynitride layer is deposited. First, a silicon nitride oxide layer is first provided and includes at least a shallow trench. The gate oxide layer is on the base layer, and the ions are implanted on the polycrystalline silicon layer and the crystal sand layer.

Page 5 4 2 5 6 3 4 Five 'Invention description (3) " Used as an anti-reflection layer, and then forming a photoresist layer on the silicon oxynitride layer' and etched silicon oxynitride layer and polycrystalline silicon layer In order to form the gate region β, a silicon nitride layer is deposited on the gate region, and the vaporization layer is etched by anisotropic etching to form a compensation gap on the gate sidewall. Next, a lightly doped electrode is used to deposit a silicon nitride layer on the substrate, and the silicon nitride layer is etched by using an anisotropic etch method to form a spacer on the side wall of the gate, and then a heavy Doping to form a source / drain, and finally performing a tempering process. Figures 5-4 are simple illustrations: Figures A through 1 show the method of preventing the loss of boron to generate PMOS according to the embodiments of the present invention. Here & Symbols: 10 substrate 14 shallow trench isolation 16 gate oxide layer 18 polycrystalline silicon layer 20 gas oxidation layer 21 photoresistance yf 22 nitride layer 24 compensation gap

V. Description of the invention (4) 26 Source / Drain 2 8 Nitride Mitsubishi 30 Spacer 5-5 Detailed description of the invention: As shown in the first A diagram, 'Semiconductor substrate 1 0' uses n-type silicon Substrate 'here includes at least a shallow trench isolation 14 to oxidize the sand on the surface to a thickness of about 15 angstroms to 60 angstroms. This shredded layer of oxide will serve as a gate oxide layer for semiconductor components. 16 (gate oxide). Next, a low pressure chemical vapor deposition (LPCVD) method is used to deposit a polycrystalline layer 18 having a thickness of about 150 to 2500 angstroms on silicon dioxide. By thermal diffusion or ion implantation, a high concentration of boron, phosphorus, or arsenic is doped into the newly deposited polycrystalline silicon, thereby reducing the gate resistivity to reduce the "RC time delay" of the gate conductive layer (RC t 丨 delay) ". Plasma-assisted chemical vapor deposition (piasma_Enhanced

Chemical Vapor Deoosition (PECVD) deposits a silicon oxynitride layer 20 (SiON) on the polycrystalline silicon layer is, and has a thickness of about 200 angstroms to 50 angstroms. It must be mentioned briefly here that the semiconductor substrate 10 is a structure with elements formed therein, and these are not important to the present invention and will not be incomprehensible because the details are not described in detail. A photoresist layer 21 is covered on the silicon oxynitride layer 20, and a stepper is used for local exposure to make the pattern on the photomask

V. Description of the invention (5) Complete transfer to the photoresist 'and then develop the photoresist to define the size of the gate electrode. The structure shown in Figure 1B is used for the next lithography process. The patterns and doped regions of the thin films are shown. The silicon oxynitride layer 20 and the polycrystalline silicon layer are etched to form a ytterbium structure. Next, a chemical vapor deposition (CVD) method is used to deposit a silicon nitride layer 22 to cover the entire surface of the wafer. The thickness is about 100 angstroms to 600 angstroms, which is used as a gate compensation gap. Use, as shown in the first C diagram. This compensation spacer is used to prevent boron out diffusion. This is because in the subsequent tempering process, "Although the crystal structure of the silicon crystal surface can be restored, it will also cause the implanted boron ions to easily flow to the surface oxide layer in the silicon wafer," which will reduce the boron ions close to the surface Concentration, resulting in an increase in resistance and a decline in driving current (ID, SAT) "The silicon nitride (sa) is used to compensate the formation of the spacer, which can effectively prevent boron ions in the source / drain during the tempering process Churn. When the boron ion maintains its concentration near the surface, it results in the generation of a low resistance value of the source / drain and a high driving current (ID, SAT) ', thereby improving the efficiency of the semiconductor device. The wafer covered with the silicon nitride layer 22 will be partially anisotropic (dry etching), and the furnace stone Γ pattern partially attached to the gate gap 24 will not be completely removed to form a compensation gap. The wall is straightened, separated, and implanted. This implantation is not high. ^ Cm β is mainly used to prevent the occurrence of short-channel effects. "Light doping 425634. V. Description of the invention (6) Lightly Doped Drain, LDD) " will form a lightly doped source / drain 26 'as shown in Figure E. Next, a conventional chemical vapor deposition method is used to form a silicon nitride layer 28 to cover the surface of the wafer. As shown in the first F diagram, β sends the wafer covered with the silicon nitride layer 2 8 into a dry etcher to perform an anisotropic etching (Anis〇tr〇pic Etch) method, which will be on the gate side. The wall forms a gap wall 30 structure as shown in the first G diagram. Next, the wafer is subjected to high concentration and deep ion implantation to perform heaVy doping of the source / and electrode 26, The concentration is about 1 019 / = m2, which will be used as the source / drain body. Then, the heavily doped implant will be completed. After the wafer is sent to the thermal diffusion furnace, the ion activation is performed at a high temperature of about 900 C to 1 G 5 GC. At the same time, "off": implantation, and the silicon on the surface of the damaged wafer is returned. Fire (annealing), as shown in the first figure 1. The above is only the scope of the present invention for the patent application; equivalent changes made by God or within the scope. The preferred embodiment is not ' Restrictions All other fine modifications that do not depart from the present disclosure should be included in the following patent applications

Claims (1)

2 563 4 VI. Application Patent Scope 1. A method for preventing ion loss, the method at least comprises: providing a semiconductor substrate including at least a shallow trench isolation (STI) region; forming a gate oxide layer on the substrate; Forming a conductive layer on the gate oxide layer; forming an anti-reflection layer on the conductive layer; and forming a gate region pattern to etch the anti-reflection layer and the conductive layer to form a dielectric layer covering the gate Area; # 开 ^ etch back the dielectric layer with a 3? Etching method to form a compensation gap on the gate side wall; perform a lightly doped drain; form a gap wall on the side wall of the gate; and The lightly doped Bk /, dopant / and electrode are heavily doped to form a source / drain, and a tempering process is performed on the remaining source / d and electrode. 2. If item 1 of the scope of patent application includes N-type semiconductor substrates. The above-mentioned semiconductor substrate to 3. If the scope of the patent application No. 1 contains polycrystalline silicon. Negative method, in which the above-mentioned conductive layer includes at least 4. As described in item 1 of the patent application scope, gas-oxygen cutting is included. $ 之 方 去, where the above anti-reflection layer is at least 1 page 10 4 2563 4 / method of claiming patent scope% as in item 4 of the patent application range, wherein the above-mentioned anti-reflection layer is formed by at least one of the following methods: Fast-heating chemical vapor deposition method 'low chemical vapor deposition method or plasma chemical vapor deposition method. As little as qualitatively doped with β. Deletion Item 1 Fluorine or Shelter Fan *. Li Yi Special Please list below Apply if there are 6 ’packages and 7 people apply for the method of patent scope item 1, where the above dielectric layer contains at least nitride stone. A method for preventing ion loss, the method includes at least: bottom providing-at least a semiconductor base formation including a shallow trench isolation (STI) region-a gate oxide layer on the substrate; forming a polycrystalline silicon layer on the gate On the polar oxide layer; implanted ions in the polycrystalline silicon layer; use a silicon nitride oxide layer on the polycrystalline silicon layer, and the oxynitride layer is used as an anti-reflection layer; 3—the photoresist layer is in the nitrogen A gate area is defined on the oxidized stone layer and the region of the oxidized nitrogen and the silicon layer; the gate area is described to form a gate area; a silicon nitride layer is deposited to cover the gate Area; by using an anisotropic etching method on the gate side to etch the silicon nitride layer wall to form a compensation gap; 425634 VI. Patent application scope for a lightly doped drain electrode; depositing a silicon nitride layer on the substrate The silicon nitride layer is etched by using an anisotropic etching method to form a spacer on the side wall of the gate electrode; performing heavy doping to form a source / drain electrode; and finally performing a tempering process. 9. The method according to item 8 of the patent application, wherein the gate layer includes at least polycrystalline silicon. 10. The method according to item 8 of the scope of patent application, wherein the etching of the above polycrystalline silicon is made by a self-aligned reactive ion etching method. 11. The method according to item 8 of the patent application, wherein the gate layer includes at least one of the following dopants: boron, phosphorus, or arsenic. 1 2. The method according to item 8 of the patent application, wherein the dopant is doped by an ion implantation method. 1 3. The method according to item 8 of the scope of patent application, wherein the above-mentioned dopant is impregnated by a thermal diffusion method. 14. The method according to item 8 of the application, wherein the lightly doped dopant contains at least one of the following: boron or boron fluoride. Page 12 6. Scope of patent application 1 5. The method according to item 8 of the scope of patent application, wherein the etching of the above polycrystalline silicon is made by self-aligned reactive ion etching. 16. The method according to item 8 of the patent application, wherein the dopant is doped by a thermal diffusion method. 17 · The method according to item 8 of the patent application, wherein the thickness of the silicon nitride layer is about 100 angstroms to 600 angstroms. Page 13