五、發明說明⑴ 4052^ β 、本發明係有關於薄膜電晶體的製造方法，特別有關於 可減^光電流及電洞電流的薄膜電晶體的製造方法。 _ 5奮#照、第1圖（a )至（e )，第1圖（a )至（e )係顯 不用=說明習知薄膜電晶體的製造方法的剖面圖。習知薄 mta曰曰體的製造方法係用於玻璃基板1上製造薄膜電晶體 1 0 (如第1圖（e )所示），而習知薄膜電晶體的製造方法 包括下列步驟。 (1)如第1圖（a)所示，於上述玻璃基板1的既定位 置上形成第一金屬層11 0，以當作上述薄膜電晶體1 0的閘 〇 (2) 如第1圖（b)所示’於上述玻璃基板1及閘極 11 0上形成閘極絕緣層丨2 〇。 (3) 如第1圖（c)所示，於上述閘極11〇上的閘極絕 緣層120上依序形成非晶矽的主動層13〇及n+摻雜層丨32， 且上述主動層130用以當作上述薄膜電晶體1〇的通道區。 (4) 如第1圖（d)所示’於上述閘極絕緣層12〇及n+ 摻雜層132上形成第二金屬層140。 (5) 如第1圖（e)所示’蝕刻上述第二金屬層14〇及 n+摻雜層1 32，以形成上述薄膜電晶體1 〇的源極及汲極 150。 彳 然而，由於上述習知薄膜電晶體受到偏壓時，電洞會 直接由主動區130流至電極150，故造成大的電洞電流。 又請參照第2圖，第2圖係顯示習知薄膜電晶體^另— 例的剖面圖，且於第2圖中與第1圖相同的部份或相當的部V. Description of the Invention ⑴ 4052 ^ β The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor which can reduce photocurrent and hole current. _ 5fen # Photo, Figs. 1 (a) to (e), Figs. 1 (a) to (e) are not shown. = A cross-sectional view illustrating a method for manufacturing a conventional thin film transistor. A conventional method for manufacturing a thin film transistor is used to manufacture a thin film transistor 10 on a glass substrate 1 (as shown in FIG. 1 (e)), and a conventional method for manufacturing a thin film transistor includes the following steps. (1) As shown in FIG. 1 (a), a first metal layer 11 0 is formed on a predetermined position of the glass substrate 1 to serve as a gate of the thin film transistor 10. (2) As shown in FIG. 1 ( As shown in b), a gate insulating layer 丨 2 is formed on the glass substrate 1 and the gate 110. (3) As shown in FIG. 1 (c), an active layer 13 of amorphous silicon and an n + doped layer 32 are sequentially formed on the gate insulating layer 120 on the gate 11 and the active layer is formed. 130 is used as a channel region of the thin film transistor 10 described above. (4) As shown in FIG. 1 (d) ', a second metal layer 140 is formed on the gate insulating layer 120 and the n + doped layer 132. (5) As shown in FIG. 1 (e), the second metal layer 14o and the n + doped layer 132 are etched to form the source and drain electrodes 150 of the thin film transistor 10.彳 However, when the conventional thin film transistor is biased, the holes will flow directly from the active region 130 to the electrode 150, resulting in a large hole current. Please also refer to FIG. 2. FIG. 2 is a cross-sectional view showing a conventional thin film transistor. Another example is shown in FIG. 2. The same or equivalent part of FIG.
五、發明說明（2) 40ν2υ3 _ 份標上相同的符號，以省略其說明。為了減少此種電洞電 流，而如第2圖所示，使主動層13〇跨出閘極11〇，如此雖 然可減少電洞電流，但是受來 射 9 而 產 生 大 的 光 電 流 0 有 鑑 於 此 9 本發 明 之 的 供 一 種 薄 膜 電 晶 體 的 製 造 方 法 膜 電 晶 體 而 上 述 薄 膜 電 晶 體 於 上 述 玻 璃 基 板 的 既 定 位 置 上 述 薄 膜 電 晶 體 的 閘 極 ； 於 上 述 絕 緣 層 ♦ 於 上 述 閘 極 上 的 閘 極 的 主 動 層 播 雜 層 及 遮 蔽 層 電 晶 體 的 通 道 區 ； 以 上 述 遮 蔽 阻 隔 絕 緣層 9 去 除 上 述遮 蔽 層 層 上 形 成 第 -- 金 屬 層 9 以 及 4k 層 以 形 成 上 述 薄 膜 電 晶 體 的 其 中 上 述 遮 蔽層 最 好 為 鉻 、 鉬 及 鋁 中 之 一 者 所 形 成 j 化 矽 0 又 上 述 主 動 層 及 推· 雜 層 第 一 金屬 層 最 好 由 鉻 、 翻 及 鋁 二 金 屬 層 最 好 由 鋁 所 形 成 〇 此 物 及 氧 化 物 中 之 一 者 所 形 成 0 又 提 供 一 種 薄 膜 電 晶 體 的 上 製 造 薄 膜 電 晶 體 J 而 上 述 薄 列 步 驟 * 於 上 述 玻 璃 基板 上 形 自玻璃基板1方向的光照 係為了解決上述問題，而提 ，適用於玻璃基板上製造薄 的製造方法包括下列步驟： 形成第一金屬層，以當作上 玻璃基板及閘極上形成閘極 絕緣層上依序形成具有側壁 且上述主動層當作上述薄膜 層為罩幕，於上述側壁形成 ，於上述閑極絕緣層及摻雜 刻上述第二金屬層及摻雜 源極及》及極。 金屬。且上述遮蔽層最好由 而上述阻隔絕緣層最好為氧 最好為非晶♦。再者，上述 中之一者所形成、而上述第 外，上述閘極絕緣層由氮化 製造方法，適用於玻璃基板 膜電晶體的製造方法包括下 成第一金屬層，以當作上述5. Description of the invention (2) 40ν2υ3 _ copies are marked with the same symbols to omit their descriptions. In order to reduce such hole current, as shown in FIG. 2, the active layer 13 is crossed out of the gate electrode 11. In this way, although the hole current can be reduced, a large photocurrent is generated by the incoming 9. The method for manufacturing a thin film transistor of the present invention is a film transistor and the thin film transistor is at a predetermined position on the glass substrate. The gate of the thin film transistor is on the insulating layer. The channel area of the active layer dopant layer and the masking layer transistor; the masking and blocking edge layer 9 is used to remove the masking layer layer to form a first metal layer 9 and a 4k layer to form the thin film transistor. The masking layer is the best It is formed by one of chromium, molybdenum, and aluminum. The first metal layer of the active layer and the doped layer is preferably formed of chromium, aluminum, and aluminum. The metal layer is preferably formed of aluminum.The formation of one of the compounds 0 provides a thin film transistor, and the thin film transistor J is provided. The above-mentioned thin-line step * is performed on the glass substrate from the direction of the glass substrate 1 in order to solve the above problems. The manufacturing method for manufacturing a thin film on a glass substrate includes the following steps: forming a first metal layer to be used as an upper glass substrate and forming a gate insulating layer on the gate, and sequentially forming side walls with the active layer as a cover of the thin film layer; A curtain is formed on the side wall, and the second metal layer and the doped source electrode and the gate electrode are etched on the idler insulating layer and the doping electrode. metal. In addition, the above-mentioned shielding layer is preferable, and the above-mentioned blocking edge layer is preferably oxygen, and most preferably amorphous. Furthermore, the gate insulating layer is formed by one of the above, and the gate insulating layer is formed by nitriding. The method suitable for manufacturing a glass substrate and a film transistor includes forming a first metal layer as the above.
Ml 第5頁 五、發明說明（3) ' ------ =電晶體的閘極；於上述玻璃基板及閘極上形成閘極絕 緣層，於上述閘極上的閘極絕緣層上依序形成具有側壁的 主動層、摻雜層及金屬遮蔽層，且上述主動層當作上述薄 膜電晶體的通道區；以上述金屬遮蔽層為罩幕，施行氧 化，而於上述側壁及金屬遮蔽層形成氧化物；去除上述金 屬遮蔽層上的氧化物；於上述閘極絕緣層及金屬遮蔽層上 形成第二金屬層；以及蝕刻上述第二金屬層、金屬遮蔽層 及摻雜層，以形成上述薄膜電晶體的源極及汲極。 其中’上述金屬遮蔽層最好由鉻、翻及铭中之一者所 形成。且上述主動層及摻雜層最好為非晶石夕。又上述第一 金屬層最好由鉻、鉬及鋁中之一者所形成、而上述第二金 屬層最好由鋁所形成。此外，上述閘極絕緣層最好由氮化 物及氧化物中之一者所形成。 依據上述本發明的薄膜電晶體的製造方法，由於使主 動層小於閘極，而由上述閘極遮蔽來自玻璃基板的光，故 可減少光電流的產生。且由於在主動層的侧壁形成阻隔絕 緣層’而阻止由主動層直接流至電極的電洞，故可減少電 洞電流。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉較佳實施例’並配合所附圖式’作詳細說明 如下： 〔圖式簡單說明〕 第1圖（a )至（e )係顯示用以說明習知薄膜電晶體 的製造方法的剖面圖；Ml Page 5 V. Description of the invention (3) '------ = gate of transistor; gate insulation layer is formed on the above glass substrate and gate electrode, and the gate insulation layer on the gate electrode is sequentially Forming an active layer, a doped layer, and a metal shielding layer with a sidewall, and the active layer is used as a channel region of the thin film transistor; the metal shielding layer is used as a mask, and oxidation is performed on the sidewall and the metal shielding layer An oxide; removing the oxide on the metal shielding layer; forming a second metal layer on the gate insulating layer and the metal shielding layer; and etching the second metal layer, the metal shielding layer and the doped layer to form the thin film Source and drain of the transistor. Among these, the above-mentioned metal shielding layer is preferably formed of one of chrome, flip, and inscription. In addition, the active layer and the doped layer are preferably amorphous stones. The first metal layer is preferably formed of one of chromium, molybdenum, and aluminum, and the second metal layer is preferably formed of aluminum. The gate insulating layer is preferably formed of one of a nitride and an oxide. According to the method for manufacturing a thin film transistor of the present invention, since the active layer is made smaller than the gate, and the light from the glass substrate is shielded by the gate, the generation of photocurrent can be reduced. Moreover, since a blocking edge layer 'is formed on the side wall of the active layer to prevent holes flowing directly from the active layer to the electrodes, the hole current can be reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, "the preferred embodiments are exemplified below" and the accompanying drawings are described in detail below: [Simplified description of the drawings] Figure 1 (a) (E) to (e) are cross-sectional views illustrating a method for manufacturing a conventional thin film transistor;
405269 五、發明說明（4) 第2圖係顯示習知薄膜電晶體的另一例的剖面圖； 第3圖（a)至（g)係顯示用以說明依據本發明之第 一實施例之薄膜電晶體的製造方法的剖面圖；以及 第4圖（a)至（g)係顯示用以說明依據本發明之第 二實施例之薄膜電晶體的製造方法的剖面圖。 〔符號說明〕 1、3、4〜玻璃基板；10、30、40〜薄膜電晶體· 110、310、410〜閘極；120、32 0、420〜閘極絕緣層； 130、3 42、442 〜主動層；132、334、344、434、444 〜換 雜層；140、360、460〜金屬層；150、370、470〜電極； 336〜金屬層；340、440〜侧壁；346〜遮蔽層；35〇〜阻 隔絕緣層；446〜金屬遮蔽層；450〜氧化物。 〔第一實施例〕 請參照第3圖（a)至（g) ’第3圖（a)至（g)係顯 示用以說明依據本發明之第一實施例之薄膜電晶體的製造 方法的剖面圖。本發明之薄膜電晶體的製造方法係適用於 玻璃基板3上製造薄膜電晶體30 (如第3圖（g )所示）， 而上述薄膜電晶體的製造方法包括下列步驟。 步驟一 如第3圖（a)所示，於上述玻璃基板3的既定位置上 形成第一金屬層3 1 0，以當作上述薄膜電晶體3 〇的閘極。 例如，首先於上述玻璃基板3上濺鍍金屬層（如鉻 (Cr )、鉬（Mo )、鋁（A1 )等），然後以微影技術 (photolithography)及蝕刻技術來形成上述閘極31〇。405269 V. Description of the invention (4) Fig. 2 is a sectional view showing another example of a conventional thin film transistor; Figs. 3 (a) to (g) are views for explaining a thin film according to the first embodiment of the present invention A cross-sectional view of a method of manufacturing a transistor; and FIGS. 4 (a) to (g) are cross-sectional views illustrating a method of manufacturing a thin-film transistor according to a second embodiment of the present invention. [Explanation of symbols] 1, 3, 4 to glass substrates; 10, 30, 40 to thin film transistors · 110, 310, 410 to gates; 120, 32 0, 420 to gate insulation layers; 130, 3 42, 442 ~ Active layer; 132, 334, 344, 434, 444 ~ Miscellaneous layer; 140, 360, 460 ~ metal layer; 150, 370, 470 ~ electrode; 336 ~ metal layer; 340, 440 ~ side wall; 346 ~ shielding Layer; 35 ~~ barrier edge layer; 446 ~ metal shielding layer; 450 ~ oxide. [First Embodiment] Please refer to Figs. 3 (a) to (g) 'Figs. 3 (a) to (g) are diagrams for explaining a method for manufacturing a thin film transistor according to a first embodiment of the present invention Sectional view. The manufacturing method of the thin film transistor of the present invention is suitable for manufacturing the thin film transistor 30 on the glass substrate 3 (as shown in FIG. 3 (g)), and the manufacturing method of the thin film transistor includes the following steps. Step 1 As shown in FIG. 3 (a), a first metal layer 3 1 0 is formed on a predetermined position of the glass substrate 3 to serve as a gate of the thin film transistor 3 0. For example, firstly, a metal layer (such as chromium (Cr), molybdenum (Mo), aluminum (A1), etc.) is sputtered on the glass substrate 3, and then the gate electrode 31 is formed by photolithography and etching technology. .
405269 五、發明說明（5) 步驟二 如第3圖（b)所示，於上述玻璃基板3及閘極310上形 成閘極絕緣層3 2 0。 例如，沈積氮化物或氧化物於上述玻璃基板3及閘極 31 0上，以形成上述閘極絕緣層3 2 〇。 步驟三 如第3圖（c)及（d)所示，於上述閘極310上的閘極 絕緣層320上依序形成具有側壁340的主動層342、摻雜層 344及遮蔽層346，且上述主動層342當作上述薄膜電晶體 30的通道區。 例如，如第3圖（c )所示，依序沈積非晶矽（a - S i )層332及n+型非晶矽334，且於n+型非晶矽334上濺鍍金屬 層（如鉻（Cr)、鉬（Mo)、鋁（A1)等）336。然後， 如第3圖（d)所示，以微影技術及蝕刻技術來形成上述主 動層342、摻雜層344及遮蔽層346， 步驟四 如第3圖（e)所示，以上述遮蔽層346為罩幕，於上 述側壁340形成阻隔絕緣層3 50，然後去除上述遮蔽層 346。 例如，在氧氣的流量為3000seem、溫度為2 30 °C的周 遭環境下，施行10〜20分鐘的熱氧化，而於上述侧壁340 形成氧化物350，然後去除上述遮蔽層346。 步驟五 如第3圖（f)及（g)所示，於上述閘極絕緣層320及405269 V. Description of the invention (5) Step 2 As shown in FIG. 3 (b), a gate insulating layer 3 2 0 is formed on the above-mentioned glass substrate 3 and the gate 310. For example, a nitride or an oxide is deposited on the glass substrate 3 and the gate electrode 310 to form the gate insulation layer 3 2 0. Step 3: As shown in FIG. 3 (c) and (d), an active layer 342, a doping layer 344, and a shielding layer 346 having a sidewall 340 are sequentially formed on the gate insulating layer 320 on the gate 310, and The active layer 342 is used as a channel region of the thin film transistor 30. For example, as shown in FIG. 3 (c), an amorphous silicon (a-Si) layer 332 and an n + -type amorphous silicon 334 are sequentially deposited, and a metal layer such as chromium is sputtered on the n + -type amorphous silicon 334. (Cr), molybdenum (Mo), aluminum (A1), etc.) 336. Then, as shown in FIG. 3 (d), the above-mentioned active layer 342, doped layer 344, and masking layer 346 are formed by lithography technology and etching technology. Step 4 is shown in FIG. 3 (e) with the above masking The layer 346 is a mask. A blocking edge layer 3 50 is formed on the sidewall 340, and then the shielding layer 346 is removed. For example, under a surrounding environment with a flow of oxygen of 3000 seem and a temperature of 2 30 ° C, thermal oxidation is performed for 10 to 20 minutes to form an oxide 350 on the sidewall 340, and then the shielding layer 346 is removed. Step 5 As shown in Figures 3 (f) and (g), the gate insulation layers 320 and
I、發明說明⑹ ---_ 摻雜層344上形成第二金屬層360，然後蝕刻上述第二金 層360及摻雜層344，以形成上述薄膜電晶體3〇的源 極370。 及，及 例如，如第3圖（f )所示，於上述閘極絕緣層32〇及 摻雜層344上濺鍍金屬層（如鋁（A1)等）36〇。然後，如 第3圖（g)所示，以微影技術及蝕刻技術來形成上述薄 電晶體30的源極及汲極370。 4 〔第二實施例〕 請參照第4圖（a )至（g )，第4圖（a )至（g )係顯 示用以說明依據本發明之第二實施例之薄膜電晶體的製造 方法的剖面圖。本發明之薄膜電晶體的製造方法係適用於 玻璃基板4上製造薄膜電晶體4〇 (如第4圖（g)所示）， 而上述薄膜電晶體的製造方法包括下列步驟。 步驟一 如第4圖（a)所示，於上述玻璃基板4的既定位置上 形成第一金屬層4 1 〇，以當作上述薄膜電晶體4〇的閘極。 例如’首先於上述玻璃基板4上濺鍍金屬層（如鉻 (Cr )、鉬（Mo )、鋁（a 1 )等），然後以微影技術及餘 刻技術來形成上述閘極4 1 0。 步驟二 如第4圖（b )所示’於上述玻璃基板4及閘極41〇上形 成閘極絕緣層420。 例如’沈積氮化物或氧化物於上述玻璃基板4及閘極 41 0上，以形成上述閘極絕緣層4 2 0。I. Description of the Invention ⑹ ---_ A second metal layer 360 is formed on the doped layer 344, and then the second gold layer 360 and the doped layer 344 are etched to form the source electrode 370 of the thin film transistor 30. And, and, for example, as shown in FIG. 3 (f), a metal layer (such as aluminum (A1), etc.) is sputtered 36 on the gate insulating layer 32o and the doped layer 344. Then, as shown in FIG. 3 (g), a source and a drain 370 of the thin transistor 30 are formed by a lithography technique and an etching technique. [Second Embodiment] Please refer to Figs. 4 (a) to (g), and Figs. 4 (a) to (g) are shown to explain a method for manufacturing a thin film transistor according to a second embodiment of the present invention Section view. The manufacturing method of the thin film transistor of the present invention is suitable for manufacturing the thin film transistor 40 on the glass substrate 4 (as shown in FIG. 4 (g)), and the manufacturing method of the thin film transistor includes the following steps. Step 1 As shown in FIG. 4 (a), a first metal layer 4 1 0 is formed on a predetermined position of the glass substrate 4 as a gate of the thin film transistor 40. For example, 'a metal layer (such as chromium (Cr), molybdenum (Mo), aluminum (a 1), etc.) is sputtered on the glass substrate 4 first, and then the above-mentioned gate electrode 4 1 0 is formed by a photolithography technique and an etching technique. . Step 2 As shown in FIG. 4 (b), a gate insulating layer 420 is formed on the above-mentioned glass substrate 4 and the gate 41o. For example, 'the nitride or oxide is deposited on the above-mentioned glass substrate 4 and the gate 410 to form the above-mentioned gate insulating layer 420.
第9頁 五、發明說明（7) 405269 步驟三 如第3圖（c)及（d)所示，於上述閘極41〇上的閘極 絕緣層420上依序形成具有側壁440的主動層442、摻雜層 444及金屬遮蔽層446，且上述主動層442當作上述薄膜電 晶體40的通道區。 例如’如第4圖（c )所示，依序沈積非晶矽層4 3 2及 n+型非晶矽434，且於n+型非晶矽434上濺鍍金屬層（如鉻 (Cr )、鉬（Mo )、鋁（A1 )等）436。然後，如第4圖 (d)所示，以微影技術及蝕刻技術來形成上述主動層 442、摻雜層444及金屬遮蔽層446， 步驟四 如第4圖（e)所示’以上述金屬遮蔽層446為罩幕， 施行氧化，而於上述側壁4 4 0形成氧化物4 5 0，然後去除上 述金屬遮蔽層44 6上的氧化物。 例如’在氧氣的流量為3000sccm、溫度為23CPC的周 遭環境下，施行10〜20分鐘的熱氧化，而於上述側壁440 形成氧化物450 ’然後以如CR7等溶液去除上述金屬遮蔽層 446上的氧化物。 步驟五 如第4圖（f)及（g)所示’於上述閘極絕緣層420及 金屬遮蔽層446上形成第二金屬層460，然後蝕刻上述第二 金屬層460、金屬遮蔽層446及摻雜層444，以形成上述薄 膜電晶體40的源極及汲極470。 例如，如第4圖（f )所示，於上述閘極絕緣層4 2 0及5. Description of the invention on page 9 (7) 405269 Step 3 As shown in Figures 3 (c) and (d), an active layer with a sidewall 440 is sequentially formed on the gate insulating layer 420 on the gate 41o. 442, a doped layer 444, and a metal shielding layer 446. The active layer 442 is used as a channel region of the thin film transistor 40. For example, as shown in FIG. 4 (c), an amorphous silicon layer 4 32 and an n + -type amorphous silicon 434 are sequentially deposited, and a metal layer (such as chromium (Cr), Molybdenum (Mo), aluminum (A1), etc.) 436. Then, as shown in FIG. 4 (d), the above-mentioned active layer 442, doped layer 444, and metal shielding layer 446 are formed by lithography technology and etching technology. Step 4 is shown in FIG. 4 (e). The metal shielding layer 446 is a mask, which is oxidized, and an oxide 4 50 is formed on the sidewall 4 4 0, and then the oxide on the metal shielding layer 44 6 is removed. For example, 'in the surrounding environment where the flow of oxygen is 3000 sccm and the temperature is 23CPC, thermal oxidation is performed for 10 to 20 minutes, and an oxide 450 is formed on the side wall 440.' Then, a solution such as CR7 is used to remove the metal shielding layer 446. Oxide. Step 5: forming a second metal layer 460 on the gate insulating layer 420 and the metal shielding layer 446 as shown in FIG. 4 (f) and (g), and then etching the second metal layer 460, the metal shielding layer 446, and The doped layer 444 forms a source and a drain 470 of the thin film transistor 40 described above. For example, as shown in FIG. 4 (f), the gate insulating layers 4 2 0 and
第10頁 五、發明說明（8) 金屬遮蔽層446上濺鍍金屬層（如鋁 後’如第4圖（g)所示，以微影技術 述薄臈電晶體40的源極及汲極470。 如上所述，依據上述本發明的薄 法，由於使主動層小於閘極，而由上 基板方向的光，故可減少光電流的產 的侧壁形成阻隔絕緣層，而阻止由主 電洞，故可減少電洞電流。 —，然本發明已以較佳實施例揭露 限疋本發明，任何熟習此項技藝者， 神和範圍内，當可作更 當視後附之申請專利& @畀/n飾因 寻利範圍所界定者為 (A1 )等）460。然 及姑刻技術來形成上 膜電晶體的製造方 述閘極遮蔽來自玻璃 生。且由於在主動層 動層直接流至電極的 如上，然其並非用以 在不脫離本發明之精 此本發明之保護範圍 準。Page 10 V. Description of the invention (8) The metal shielding layer 446 is sputter-plated with a metal layer (such as aluminum). As shown in FIG. 4 (g), the source and drain of the thin crystalline transistor 40 are described by lithography technology. 470. As mentioned above, according to the thin method of the present invention, since the active layer is made smaller than the gate and light is directed from the upper substrate, the side wall that can reduce the generation of photocurrent forms a blocking edge layer and prevents the main power The hole current can be reduced.-However, the present invention has been disclosed in a preferred embodiment to limit the present invention. Anyone skilled in the art, within the scope of God and scope, can be regarded as the attached patent & @ 畀 / n decoration (A1) etc. as defined by the profit-seeking area) 460. However, the manufacturing method of the film transistor to form the film transistor is described as gate shielding from glass. And because the active layer in the active layer directly flows to the electrode as above, it is not used without departing from the spirit of the present invention and the scope of protection of the present invention.