經濟部中央標準局員工消費合作杜印製 Α7 Β7 五、發明説明（l ) 本發明係有關一製造半導體元件的方法，且尤其，有 關一製造具宥漏電流降低區的一半導體元件的方法。 v 在每一個k造程序中一半導體元件的隔離程序是初始 程序，且其決定主動區的尺寸及往後的程序邊界。 隔離方法之一\，使用一砂區域氧化(LOCOS)法，在一 定的情況下於一¥導體>基質上執行一熱氧化程序而在一非 主動區上形成一場氧化物膜。 爲了增強半導體基質的隔離特性，使用離子注入在半 導體基質中形成一場離子層。 然而，一電場可能在場離子磨與源極間的邊界處的場 氧化物膜的邊緣形成。因而產生一漏電流，因此，降低半 導體元件的更新特性。 * 第1圖係用以解釋製造一半導體界件的一傳統方法的 橫截面圖。 參考號碼1表示一半導體基質，參考號碼3表示一場氧 化物膜，參考號碼5表示一場離子層，參考號碼7表示一閘 極氧化物膜，參考號碼9表示一閘極電極，參考號碼11表 示一絕緣膜圖案，參考號碼12表示一閘極，參考號碼13a 表示一汲極，參考號碼13b表示一源極，參考號碼15a表示 第一層間絕緣層，參考號碼16與20表示接點孔，參考號碼 19表示一第二層間絕緣層，及參考號碼21表示一雜質區》 首先，使用一傳統的方法於半導體基質1上形成Λ氧 化物膜3，然後場離子層5被形成於半導體基質中。 . 場離子層5降低產生於場氧化物膜3的邊緣與於後來之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） IJ—Ί—---Γ —裝-------訂 <------^線 (請先閣讀背面之注意事項再填寫本頁) 經濟部中夬樣隼局員工消費合作杜印製 A7 B7 五、發明説明（2 ) 程序中形成的一源極之間的區域中的接面漏電流，且利用 、離子植入一第f導電型的雜質至具有場氧化物膜3之半導 體基質1的整個_面上而形成。 結果，在除亍直接位於場氧化ί勿膜3以下的區域以外 的區域中場離子是攀深的。' 具有一汲極13a、一源極13b，及一閘極12的電晶體構 成一絕緣膜圖案11，一閘;^電極9與一閘極氧化物膜7被形 成於具有場氧化物膜3形成於其上的半導體基質1的上面。 一絕緣材料被沉積在具有場氧化物膜3形成於其上的 半導體基質1的上面，然後被模製形成曝光汲極13a的接點 孔16 〇 脅 接下來，一導體材料被沉積在具有接點孔形成在其中 的合成結構的整個表面上，然後被f莫辦形成位元線17 〇 一絕緣材料被沉積在半導體基質1之上，後被模製形 成接點孔20。 雜質區21利用植入一具有相對於第一導電型雜質的導 電率之第二導電型雜質於合成結構的整個表面而被形成於-源極13b之下。 形成雜質區21的目的是爲了防止半導體元件的復新特 性因爲漏電流而衰退。 漏電流形成的原因有：1)產生在介於場離子層5與源 極13b間的場氧化物膜3的邊緣部分的電場；及2)在接^占孔 20形成過程中在半導體基質1上發生蝕刻損壞。 · 因此，雜質區21使用離子注入程序形成在源極13B之 % —--一- I r I I Ϊ裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 張尺度適用中國國家標準（⑽）八槻公疫） ' 5 - ^ 經濟部中央標準局員工消費合作杜印裝 A7 B7 五、發明説明（3 ) 下，如此使得在場氧化物膜3的邊緣部分不產生接面漏電 v流。而且，損壞被去除，使得漏電流不產生。 根據之前甲提及之製造一半導體元件的方法，可以防 止在場氧化物膜i邊緣部分中所產‘生的接面漏電流。然 而，產生於在場气螂膜之邊緣部分外的接面漏電流，例 如，在源極之下，可能無法輕易防止。 而且，由於半導體元择的高集成，所以場氧化物膜的 厚度有被減少的趨勢。然而，如果場氧化物膜的厚度被降 低，半導體元件的隔離特性就無法充分滿足。因此，場離 子的雜質濃度須被增加且其離子植入能量必須降低。然而 雜質濃度的增加與離子植入能量的降低可能使復新特性變 差，而補償隔離特性時。 提供一利用抑制介於源極/汲極與一場離子層間之邊 界的漏電流產生而藉以改善半導體基質復新特性的製造半 導體基質的方法是本發明之目的。 爲了實現本發明的目的，一第一導電型的雜質被離子 植入至具有一場氧化物膜形成在其上的半導體基質的整個 表面，以在半導體基質中形成一場離子層。一第二導電型 電晶體與一層間絕緣層被相繼形成在半導體基質上。層間 絕緣層被模製以曝光電晶體的源極。一第二導電型的雜質 被離子植入至源極的較低部分形成一第一漏電流降低區。 而且，一第二導電型的雜質被離子植入至第一漏電流ib低 區的較低部分形成一第二漏電流降低區。 . 本發明的前述目的與優點藉由參考附圖詳細說明一較 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 、-°. 經濟部中央標準局員工消費合作社印製 A7 B7 ---------- "----- 五、發明説明（4 ) 佳實施例將變得更淸楚其中： 第1圖^用以解釋根據—傳統方法製造一半導體元件 v. \ 的橫截面圖；琴 第2八到涩圖读用以解釋根據本囊明之製造一半導體元 件的方法的橫截^#1。> 參考第2A-2D圖’參考號碼31表示一半導體基質，參 考號碼33表示一場氧化物k，參考號碼35表示一場離子 層，參考號碼37表示一閘極氧化物膜，參考號碼39表示一 閘極電極，參考號碼41表示一絕緣膜圖案，參考號碼42表 示一閘極’參考號碼43a表示一汲極，參考號碼43b表示一 源極，參考號碼45與45a表不弟一層間絕緣層圖案’參考 令 號碼46與50表不接點孔’參考號碼47表示一位元線，參考 號碼49表示一第二層間絕緣層圖案，參考號碼51表示一第 一漏電流降低區，及參考號碼53表示一第二漏電流降低 區。 參考第2A圖，場氧化物膜33被形成於一半導體基質31 上，然後場離子層3 5被形成在半導體基質31中。 場離子層35降低產生在介於場氧化物膜33的邊緣與一 源極(在隨後的一程序中被形成)之間的接面漏電流且在藉 由在一90〜150KeV的能量及3*1012〜1013/cm2之劑量下將一 第一導電型雜質，例如，硼，離子植入至其上具有場氧化 物膜33的半導體基質31的整個表面而形成。 ^ 結果，在非直接位於場氧化物膜33以下的區域外的區 域場離子層35是較深的。 % ~~國家標率（CNS ) A4規格（210X 297公釐） -7 - ^~ ---ill·.:---- r 裝------訂----.!線 一请先閱讀背面之注意事項再填寫本萸) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 參考第2B圖，一電晶體被形成在具有場氧化物膜形成 v 於其上的半導體基質31之上。 詳盡地說，一氧化物膜(在一隨後的程序中被模製當 '：V .： 作一閘極氧化物#37)，一導體層(¾一隨後的程序中被模 製當作一閘極電寶〗9)歹一絕緣磨(在一隨後的程序中被模 製當作一絕緣膜41)被相繼地形成於半導體基質31的整個 表面上。由絕緣膜圖案41 =閘極電極39，與閘極氧化物膜 37所組成的閘極42藉由使用一光刻程序模製絕緣膜、導體 層，及氧化物膜而形成。而且，汲極43a與源極43b利用植 入離子到具有形成在其上之閘極42的半導體基質31中而形 成。 離子植入程序使用具有與第一導電型雜質相反之導電 率的第二導電型雜質，例如，磷(p)P子，而達成，因此 完成電晶體。 參考第2C圖，一絕緣材料被沉積在具有電晶體形成在 其上之半導體基質31上形成一第一層間絕緣層(在一隨後 的程序中被模製當作一第一層間絕緣層圖案45)且之後曝 光汲極43a及第一層間絕緣層圖案45的接點孔46也利用模 製第一層間絕緣層而形成。 接下來’一導電性材料被沉積在具有接點孔46形成於 其中之合成結構的整個表面上形成位元線47。 參考第2D圖’ 一絕緣材料被沉積在具有位元線形^在 其上之合成結構上形成一第二層間絕緣層(在一隨後的程 序中被模製當作一第二層間絕緣層圖案49)。第二層間絕 i 本纸張尺度適用中國國家標準(CNS)A4^( 210X297557 -----------? 1 裝---^----訂-----J 線 .(請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 Μ Β7 五、發明説明（6 ) 緣層與第β層間絕緣層圖案45使用一光刻程序被模製形成 曝光源極43ί3、第一層間絕緣層45a ’及第二層間絕緣層圖 V v 案49的接點孔巧。 第一漏電流降低區51藉由植入離子在合成結構的整個 表面而被形成在源^極气b之下。’ 在形成第一“電流降低區51的植入離子程序期間’使 用之離子能量階及劑量較私成源極43b之植入程序時大’ 即是，第二導電型雜質’例如磷(P)離子’使用60〜 150KeV的能量1012〜l〇14/cm2之劑量被植入。 於接點孔50的形成期間在半導體基質31的表面上所產 生的蝕刻損壞可使用形成第一漏電流降低區51之離子植入 * 程序補救。 因此，利用形成第一漏電流降低區51可以抑制產生於 ：· 場離子層35與源極43b之間的場氧化物膜33的邊緣部分的 接面漏電流與因爲蝕刻損壞所造成的漏電流。 參考第2E圖，第二漏電流降低區53被形成於第一漏電 流降低區51之下。 第二漏電流降低區53藉由使用大於形成第一漏電流降 低區51之200〜500KeV之能量1012〜1014/cm2之劑量離子植 入一第二導電型雜質，例如磷(P)，而形成。 結果，第二漏電流降低區53被形成於第一漏電流降低 區51之下且延伸至場離子層35以上之區域。 ^ 形成第二漏電流降低區53的目的：1)抑制源極43b之 下的接面漏電流；2)補償半導體元件因爲爲求減少場氧化 % 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） ——ίίι+----裝------訂------球 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作杜印製 A7， B7 五、發明説明（7 ) 物膜33之厚度增加場離子層35的雜質濃度與降低離子能量 所造成之復新特性衰退。 、 接著，^儲存電極藉由沉積一導電材料在接點孔50中 而形成且之狻一介質薄膜與一平板電極被形成，因此完成 電容器。 、 因此，根據每:發明的半導體元件的製造方法，一第一 漏電流降低區被形成於^源極之下然後一第二漏電流降低 區再被形成於第一漏電流降低區之下，用以減弱發生在位 於源極之下之一耗盡區之電場及抑制發生於源極之下與一 場氧化物膜之邊緣部份中的接面漏電流的產生，因此改善 半導體元件的復新特性。 如前面所述，雖然本發明已詳紬地參考舉例的實施例 裝 I I 訂 i I I 線 ' d - (請先閲讀背面之注意事項再填寫本頁) 說明，但是本發明並不限制於此而且一個孰於此技的人在 本發明的範圍內可以進行不同的修己^。 元件標號 對照 表 1 半導體基質 33 氧化物膜 3 氧化物膜 35 場離子層 ： 5 場離子層 37 閘極氧化物膜 7 閘極氧化物膜 39 閘極電極 9 閘極電極 41 絕緣膜圖案 11 絕緣膜圖案 42 閘極 12 閘極 43a 汲極 13a 汲極 43b 源極 13b 源極 45 第一層間絕緣層圖案 15a 第一層間絕緣層 45a 第一層間絕緣層圖案 16 接點孔 46 接點孔^ 17 位元線 47 位元線 19 第二層間絕緣層圖 案 49 第二層間絕緣層圖案 20 接點孔 50 接點孔 ， 本纸張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） 五、發明説明（ 8 A7 B7 21 雜貧區 31 半導rt基質 經濟部中央標準局員工消費合作社印製 51 第一'漏電流降低區 53 第二漏電流降低區 (請先閱讀背面之注意事項界填寫本頁) -裝· 訂 :線- 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 -Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs for consumer cooperation. A7 B7 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device with a reduced leakage current region. v The isolation process of a semiconductor element in each process is the initial process, and it determines the size of the active area and subsequent process boundaries. One of the isolation methods, using a sand area oxidation (LOCOS) method, under certain conditions, a thermal oxidation process is performed on a ¥ conductor > substrate to form a field oxide film on an inactive region. In order to enhance the isolation characteristics of the semiconductor substrate, an ion layer is formed in the semiconductor substrate using ion implantation. However, an electric field may be formed at the edge of the field oxide film at the boundary between the field ion mill and the source. Therefore, a leakage current is generated, and therefore, the refreshing characteristics of the semiconductor element are reduced. * Figure 1 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor boundary member. Reference number 1 indicates a semiconductor substrate, reference number 3 indicates a field oxide film, reference number 5 indicates a field ion layer, reference number 7 indicates a gate oxide film, reference number 9 indicates a gate electrode, and reference number 11 indicates a Insulating film pattern, reference number 12 indicates a gate electrode, reference number 13a indicates a drain electrode, reference number 13b indicates a source electrode, reference number 15a indicates a first interlayer insulating layer, and reference numbers 16 and 20 indicate contact holes. The number 19 indicates a second interlayer insulating layer, and the reference number 21 indicates an impurity region. First, a Λ oxide film 3 is formed on the semiconductor substrate 1 by a conventional method, and then the field ion layer 5 is formed in the semiconductor substrate. The reduction of the field ion layer 5 is generated at the edge of the field oxide film 3 and later the paper size is applied to the Chinese National Standard (CNS) A4 specification (210X297 mm). IJ—Ί —--- Γ — equipment ---- --- Order < ------ ^ line (please read the precautions on the back before filling out this page) Employee Co-operation of the Bureau of Samples in the Ministry of Economic Affairs Du printed A7 B7 V. Invention Description (2) A junction leakage current in a region between the sources formed in the procedure is formed by ion implantation of an f-th conductivity type impurity onto the entire surface of the semiconductor substrate 1 having the field oxide film 3. As a result, the field ions are deep in regions other than the region directly below the field oxide film 3. '' A transistor having a drain electrode 13a, a source electrode 13b, and a gate electrode 12 constitutes an insulating film pattern 11 and a gate; ^ an electrode 9 and a gate oxide film 7 are formed on a field oxide film 3 An upper surface of the semiconductor substrate 1 formed thereon. An insulating material is deposited on the semiconductor substrate 1 having the field oxide film 3 formed thereon, and is then molded to form the contact hole 16 of the exposed drain electrode 13a. Next, a conductive material is deposited on the substrate Dot holes are formed on the entire surface of the composite structure therein, and then bit lines 17 are formed by an insulating material. An insulating material is deposited on the semiconductor substrate 1 and is then molded to form a contact hole 20. The impurity region 21 is formed under the source 13b by implanting a second conductive type impurity having a conductivity relative to the first conductive type impurity on the entire surface of the composite structure. The purpose of forming the impurity region 21 is to prevent the restoration characteristics of the semiconductor element from deteriorating due to leakage current. The reasons for the formation of the leakage current are: 1) the electric field generated at the edge portion of the field oxide film 3 between the field ion layer 5 and the source electrode 13b; and 2) the semiconductor substrate 1 is formed during the formation of the hole 20 Etching damage occurred. · Therefore, the impurity region 21 is formed at the% of the source 13B using an ion implantation procedure. --- I r II outfitting --- order --- (Please read the precautions on the back before (Fill in this page) Zhang Zhimeng applies the Chinese National Standard (槻) Yabuya epidemic) '5-^ Consumers' cooperation with the Central Bureau of Standards, Ministry of Economic Affairs, Du Duan A7 B7 V. Under the description of the invention (3), this makes the presence of oxides The edge portion of the film 3 does not generate the interface leakage current v. Moreover, the damage is removed so that no leakage current is generated. According to the method for manufacturing a semiconductor element mentioned in the foregoing A, the junction leakage current generated in the edge portion of the field oxide film i can be prevented. However, the leakage current at the junction outside the edge portion of the field gas worm membrane, for example, under the source, may not be easily prevented. Moreover, due to the high integration of semiconductor elements, the thickness of the field oxide film tends to be reduced. However, if the thickness of the field oxide film is reduced, the isolation characteristics of the semiconductor element cannot be sufficiently satisfied. Therefore, the impurity concentration of the field ions must be increased and its ion implantation energy must be reduced. However, an increase in impurity concentration and a decrease in ion implantation energy may degrade the recovery characteristics and compensate for the isolation characteristics. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate by suppressing the generation of a leakage current at the boundary between the source / drain and a field ion layer to improve the recovery characteristics of the semiconductor substrate. To achieve the object of the present invention, an impurity of a first conductivity type is ion-implanted onto the entire surface of a semiconductor substrate having a field oxide film formed thereon to form a field ion layer in the semiconductor substrate. A second conductivity type transistor and an interlayer insulating layer are sequentially formed on the semiconductor substrate. The interlayer insulating layer is molded to expose the source of the transistor. A second conductivity type impurity is ion-implanted into the lower portion of the source to form a first leakage current reduction region. Moreover, a second conductivity type impurity is ion-implanted into a lower portion of the lower region of the first leakage current ib to form a second leakage current reduction region. The foregoing objects and advantages of the present invention are described in detail with reference to the accompanying drawings. A Chinese standard (CNS) A4 specification (210X297 mm) applies to the paper size (please read the precautions on the back before filling this page),-° . Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 ---------- " ----- V. Description of the Invention (4) The best embodiment will become even better: Among them: 1 Figure ^ is used to explain a cross-sectional view of a semiconductor device manufactured according to the traditional method v. \; Qin No. 28 to Figure 2 are used to explain the cross-section ^ # 1 of the method of manufacturing a semiconductor device according to this chapter. > Referring to Figures 2A-2D, reference number 31 indicates a semiconductor substrate, reference number 33 indicates a field oxide k, reference number 35 indicates a field ion layer, reference number 37 indicates a gate oxide film, and reference number 39 indicates a Gate electrode, reference number 41 indicates an insulation film pattern, reference number 42 indicates a gate electrode, reference number 43a indicates a drain electrode, reference number 43b indicates a source electrode, and reference numbers 45 and 45a indicate an interlayer insulation layer pattern 'Reference order numbers 46 and 50 indicate contact holes' Reference number 47 indicates a one-bit line, reference number 49 indicates a second interlayer insulation layer pattern, reference number 51 indicates a first leakage current reduction region, and reference number 53 Indicates a second leakage current reduction region. Referring to FIG. 2A, a field oxide film 33 is formed on a semiconductor substrate 31, and then a field ion layer 35 is formed in the semiconductor substrate 31. The field ion layer 35 reduces the leakage current generated at the junction between the edge of the field oxide film 33 and a source (formed in a subsequent procedure) and reduces the energy between 90 and 150 KeV and 3 * At a dose of 1012 to 1013 / cm2, a first conductive type impurity such as boron is ion-implanted onto the entire surface of the semiconductor substrate 31 having the field oxide film 33 thereon. ^ As a result, the field ion layer 35 is deeper in a region outside the region not directly below the field oxide film 33. % ~~ National standard rate (CNS) A4 specification (210X 297 mm) -7-^ ~ --- ill ·.: ---- r equipment -------- order ----.! Line one Please read the notes on the back before filling in this.) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) Referring to Figure 2B, a transistor is formed with a field oxide film formed v at Above the semiconductor substrate 31. To elaborate, an oxide film (molded in a subsequent process when ': V .: is made as a gate oxide # 37), a conductor layer (¾ is molded in a subsequent process as a Gate Electrode 9) An insulating mill (molded as an insulating film 41 in a subsequent procedure) is successively formed on the entire surface of the semiconductor substrate 31. A gate electrode 42 composed of an insulating film pattern 41 = a gate electrode 39, and a gate oxide film 37 is formed by molding an insulating film, a conductor layer, and an oxide film using a photolithography process. The drain 43a and the source 43b are formed by implanting ions into a semiconductor substrate 31 having a gate 42 formed thereon. The ion implantation procedure is achieved using a second conductivity type impurity having a conductivity opposite to that of the first conductivity type impurity, for example, phosphorus (p) P, thereby completing the transistor. Referring to FIG. 2C, an insulating material is deposited on a semiconductor substrate 31 having transistors formed thereon to form a first interlayer insulating layer (molded as a first interlayer insulating layer in a subsequent procedure) Pattern 45) and then expose the contact holes 46 of the drain electrode 43a and the first interlayer insulating layer pattern 45 are also formed by molding the first interlayer insulating layer. Next, a conductive material is deposited on the entire surface of the composite structure having the contact holes 46 formed therein to form bit lines 47. Referring to FIG. 2D ', an insulating material is deposited on a composite structure having bit lines ^ to form a second interlayer insulating layer (molded as a second interlayer insulating layer pattern in a subsequent procedure 49) ). The second layer must be in accordance with Chinese national standard (CNS) A4 ^ (210X297557 -----------? 1 pack --- ^ ---- order ----- J line (Please read the precautions on the back before filling out this page) Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs of the Ministry of Commerce Du B7. V. Description of the Invention (6) The edge layer and the β interlayer insulation layer pattern 45 are covered by a photolithography process. The contact holes of the exposed source electrode 43, 3, the first interlayer insulating layer 45a ', and the second interlayer insulating layer V v. 49 are formed by molding. The first leakage current reduction region 51 is implanted through the entire structure of the synthesized structure. Surface is formed below the source electrode b. 'During the formation of the first "current reduction region 51, the ion energy step and dose used were larger than those used when the source 43b was implanted.' That is, the second conductivity-type impurity 'for example, phosphorus (P) ions' is implanted using a dose of 60 to 150 KeV at an energy of 1012 to 1014 / cm2. During the formation of the contact hole 50 on the surface of the semiconductor substrate 31 The resulting etch damage can be remedied using the ion implantation * procedure forming the first leakage current reduction region 51. Therefore, the formation of the first leakage The current reduction region 51 can suppress the leakage current generated at the junction of the edge portion of the field oxide film 33 between the field ion layer 35 and the source electrode 43b and the leakage current caused by the etching damage. Referring to FIG. 2E, the Two leakage current reduction regions 53 are formed below the first leakage current reduction region 51. The second leakage current reduction region 53 is formed by using an energy of 1012 to 1014 / cm2 that is greater than 200 to 500 KeV of the first leakage current reduction region 51. A dose of ion is implanted by implanting a second conductivity type impurity, such as phosphorus (P). As a result, the second leakage current reduction region 53 is formed below the first leakage current reduction region 51 and extends above the field ion layer 35. ^ The purpose of forming the second leakage current reduction region 53 is: 1) to suppress the leakage current at the junction below the source 43b; 2) to compensate the semiconductor device because it is to reduce the field oxidation% This paper applies the Chinese national standard (CNS) ) A4 size (210X 297mm) ——ίί + ---- installation ------ order ------ ball (please read the notes on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs Consumption cooperation of employees Du printed A7, B7 V. Description of invention (7) Thickness of material film 33 The regeneration characteristics caused by increasing the impurity concentration of the field ion layer 35 and decreasing the ion energy are degraded. Next, the storage electrode is formed by depositing a conductive material in the contact hole 50, and a dielectric film and a flat electrode Is formed so that the capacitor is completed. Therefore, according to the semiconductor device manufacturing method of the invention, a first leakage current reduction region is formed under the source, and then a second leakage current reduction region is formed again on the first Below the leakage current reduction region, it is used to weaken the electric field occurring in a depletion region located below the source and to suppress the generation of leakage current at the junction between the source and the edge portion of an oxide film. Therefore, the refresh characteristics of the semiconductor element are improved. As mentioned above, although the present invention has been described in detail with reference to the example embodiment of the II-II-II line 'd-(please read the precautions on the back before filling this page) description, the present invention is not limited to this and A person skilled in the art can perform various self-cultivation within the scope of the present invention ^. Component reference table 1 semiconductor substrate 33 oxide film 3 oxide film 35 field ion layer: 5 field ion layer 37 gate oxide film 7 gate oxide film 39 gate electrode 9 gate electrode 41 insulating film pattern 11 insulation Film pattern 42 Gate 12 Gate 43a Drain 13a Drain 43b Source 13b Source 45 First interlayer insulation layer pattern 15a First interlayer insulation layer 45a First interlayer insulation layer pattern 16 Contact hole 46 Contact Hole ^ 17 bit line 47 bit line 19 Second interlayer insulating layer pattern 49 Second interlayer insulating layer pattern 20 Contact hole 50 Contact hole, this paper size applies to China National Standard (CNS) A4 (210X297) (5) Description of the invention (8 A7 B7 21 Miscellaneous poor area 31 Semiconducting rt Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 51 First leakage current reduction area 53 Second leakage current reduction area (please read the back Please note this page to fill in this page)-Binding · Binding: Line-This paper wave size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -11-