經濟部中央標準局员工消费合作社印製 __；___B7 —____ 五、發明説明（） 5-1發明領娀： 本發明係關於一種金屬矽化物閘極之製程，特別是在 自對準接觸窗製程中產生平整金屬矽化物閘極結構的方 法。 5-2發明背景： 在超大型積體電路(VLSI)製程中，源極(s〇urce)與汲極 (drain)區域面積無法一直縮小下去，因為接觸窗（contact hole)必須使用獨立的罩幕(mask)步驟來對準這些區域，而且 必須分配額外的區域，以防未對準之情況發生。目前，自 對準接觸窗和主動區無邊界(active region borderless)製程廣 泛地被使用於SRAM或DRAM的設計之中’因為此製程可 以減少元件之中，在接觸窗間（例如，接觸窗與閘極、接 觸窗與主動區邊緣）的距離。 然而，傳統的閘極製程中，在熱處理製程之後，金屬 矽化物層通常會在外觀輪廓上產生一些突起的結構，這些 突起結構會使後續覆蓋上去的間隙壁（spacer)產生不平整的 表面’並且由於覆蓋於這些突起結構附近的間隙壁較薄， 容易造成金屬石夕化物閘極與在自對準接觸窗（self-aligned contact，SAC)中的金屬材料之間的短路。 以下是典型的傳統矽化鎢閘極製造流程。首先，請參 閱第一圖’在底材12上定義主動區（active region)、井區（well region)和場氧化層，在主動區上形成半導體元件，其中主 2 A7 (請先閲讀背面乏注意事項再填寫本頁) 訂 本紙張尺度適用中國國家揉準（CNS ) Μ規格（2丨0X297公楚）Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs __; ___B7 —____ V. Description of the Invention () 5-1 Invention Field: The present invention relates to a process for manufacturing a metal silicide gate, especially for self-aligned contact windows Method for generating flat metal silicide gate structure in manufacturing process. 5-2 Background of the Invention: In the VLSI process, the area of the source and drain regions cannot be reduced all the time because a separate cover must be used for the contact hole. A mask step is used to align these areas, and additional areas must be allocated to prevent misalignment. At present, self-aligned contact windows and active region borderless processes are widely used in the design of SRAM or DRAM 'because this process can reduce the number of components between contact windows (for example, contact windows and Gate, contact window, and edge of active area). However, in the traditional gate process, after the heat treatment process, the metal silicide layer usually produces some protruding structures on the appearance contour, and these protruding structures will cause uneven surfaces of the subsequently covered spacers to produce an uneven surface. And because the gap wall covering near the protruding structures is thin, it is easy to cause a short circuit between the metal oxide gate and the metal material in a self-aligned contact (SAC). The following is a typical traditional tungsten silicide manufacturing process. First, please refer to the first figure, 'Define the active region, well region, and field oxide layer on the substrate 12, and form a semiconductor element on the active region. The main 2 A7 (please read Note: Please fill in this page again.) The size of the paper is applicable to China National Standard (CNS) Μ (2 丨 0X297).
動區、井區和場氧化層並未顯示在第—圖之中。然後請參 閱第二圖’在底材12上形成閘極氧化層14，通常為沈積一 層厚度在30-200埃之間的二氧化石夕層。接著，沈積一捧雜 多晶石夕層16 ’作為半導體元件的閘極。然'後，在掺雜多晶 石夕層16上，覆蓋一金屬石夕化物層18。然後，沈積一罩幕層 20,覆蓋在摻雜多晶石夕層16與金屬石夕化物層18之上，通 常罩幕層20是利用氮化石夕層所組成，或是利用氮化石夕層與 *一乳化碎層所組成。 請參閱第三圖，經過微影與蝕刻製程，蝕刻罩幕層2〇、 金屬石夕化物層18、換雜多晶㈣16及閘極氧化層14，形 成半導體元件的閘極結構。 請參閱第四圖，進行離子佈植製程，在底材12之中形 成淡摻雜沒極22。然後進行高溫退火處理製程，閘極結構 的金屬石夕化物層18會向外成長，形成令間凸出的閉極結 構’如第六B圖所示。 然後，請參閱第七B圖，在閘極結構的兩側形成，間隙 層24，作為閘極結構的絕緣保護。請參閱第八圖，進行離 子佈植製程’利用閘極結構、間隙層24作為離子佈植罩幂， 在底材12之中形成源汲極26。 接著，請參閱第九B圖，沈積一内介電層28在閘極結 構與底材12的表面，内介電層28的組成材料包括未經摻 雜的二氧化矽和硼磷摻雜四乙基矽酸鹽（BPTE〇s)。然後， 請參閲第十B圖，在内介電層2S之上形成光阻3〇，定義 [ ____ 3 ( CNS ) A4^^7210x297^^ ) (請先閲讀背面•之注意事項再填寫本頁} r 裝 r 線 ------------ ,-1 I —si imw · 經濟部中央標準局負工消费合作社印^ A7 ---------- —_B7 五、發明説明^ ) 一 ---- 半導體元件之接觸窗的自對準區域。請參閱第十_ ， 利用微影與侧製程，間隙層24作為㈣罩幕 二 電層28與罩幕層2G進行侧製程，形成半導體元件的^ ^準區域。最後，進行-般的製程，完成半導體元件的製 然而，根據傳統的製程，石夕化鶴層會在高溫退火處理 的過程中快速成長，甚至突出原來已經定義好的間極結構 表面。如此的石夕化鎢層的成長效應，在覆蓋間隙壁之後， 很容易在閘極結構的表面產生突出且不平滑的外觀輪靡。 而且’由於覆蓋於這些突起結構附近的間隙壁較為薄弱， 很容易在石夕化鎢閘極與自對準接觸窗之間，造成短路 題。 因而，在SRAM或DRAM的製造過程之中，需要一種 避免產生上述之突起結構的製造方法，以及避免在矽化鎢 閘極與自對準接觸窗中的金屬材料之間產生短路的製造方 法。 i-3發明目的及概诚： 本發明提供一種自對準半導體元件的製造方法，可以 形成具有平整表面的閘極結構。 本發明提供一種閘極結構的製造方法，在形成閘極結 構之後，對閘極結構的金屬矽化物層進行濕蝕刻製程，形 成凹入形閘極結構，接著進行高溫退火製程，使得金屬 .--1^-- (請先閲讀背面-之注意事項再填寫本頁) -丁 4The moving area, well area and field oxide layer are not shown in the first figure. Then refer to the second figure 'to form a gate oxide layer 14 on the substrate 12, which is usually a layer of stone dioxide with a thickness of 30-200 angstroms. Next, a handful of heteropolycrystalline stone layer 16 'is deposited as the gate of the semiconductor element. Then, on the doped polycrystalline silicon layer 16, a metallic stone material layer 18 is covered. Then, a cover layer 20 is deposited, covering the doped polycrystalline silicon layer 16 and the metallic stone material layer 18. Generally, the cover layer 20 is composed of a nitride stone layer or a nitride stone layer It is composed of * 1 emulsified crushed layer. Referring to the third figure, after the photolithography and etching processes, the mask layer 20, the metal oxide layer 18, the doped polycrystalline silicon 16 and the gate oxide layer 14 are etched to form the gate structure of the semiconductor device. Referring to the fourth figure, the ion implantation process is performed to form a lightly doped dead electrode 22 in the substrate 12. Then, a high-temperature annealing process is performed, and the metal oxide layer 18 of the gate structure will grow outward to form a closed-pole structure protruding between the gates, as shown in FIG. 6B. Then, referring to Figure 7B, a gap layer 24 is formed on both sides of the gate structure to serve as insulation protection for the gate structure. Referring to FIG. 8, an ion implantation process is performed. The gate structure and the gap layer 24 are used as ion implantation masks to form a source drain 26 in the substrate 12. Next, referring to FIG. 9B, an inner dielectric layer 28 is deposited on the surface of the gate structure and the substrate 12. The constituent materials of the inner dielectric layer 28 include undoped silicon dioxide and boron-phosphorus doped Ethyl silicate (BPTE0s). Then, please refer to the tenth figure B, forming a photoresistor 30 on the inner dielectric layer 2S, and defining [____ 3 (CNS) A4 ^^ 7210x297 ^^) (Please read the precautions on the back side before filling in this Page} r line r line ------------, -1 I —si imw · Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ A7 ---------- —_B7 V. Description of the Invention ^) a ---- Self-aligned area of the contact window of the semiconductor element. Please refer to the tenth step. Using the lithography and side processes, the gap layer 24 is used as the mask. The electrical layer 28 and the mask layer 2G are subjected to the side process to form a ^^ region of the semiconductor device. Finally, a general process is performed to complete the manufacturing of semiconductor devices. However, according to the traditional process, the Shixi Chemical Crane layer will grow rapidly during the high temperature annealing process, even highlighting the surface of the previously defined interpolar structure. Such a growth effect of the lithographic tungsten layer can easily produce a prominent and uneven appearance on the surface of the gate structure after covering the gap wall. And because the gap wall covering the vicinity of these protruding structures is relatively weak, it is easy to cause a short circuit between the Shixihua tungsten gate and the self-aligned contact window. Therefore, in the manufacturing process of SRAM or DRAM, there is a need for a manufacturing method that avoids the above-mentioned protruding structure and a manufacturing method that avoids a short circuit between the tungsten silicide gate and the metal material in the self-aligned contact window. i-3 Invention purpose and sincerity: The present invention provides a method for manufacturing a self-aligned semiconductor device, which can form a gate structure having a flat surface. The invention provides a method for manufacturing a gate structure. After the gate structure is formed, a metal silicide layer of the gate structure is subjected to a wet etching process to form a recessed gate structure, and then a high temperature annealing process is performed to make the metal.- -1 ^-(Please read the precautions on the back-before filling out this page)-Ding 4
A7 B7 經濟部中央標率局負工消費合作社印裝 五、發明説明（） 化物層在高溫之中成長，形成具有平滑表面的閘極結構。 本發明提供一種金屬矽化物閘極的製造方法，在閘極 結構的高溫退火製程之前，對金屬矽化物層進行蝕刻製 程，形成凹入形金屬矽化物閘極，在高溫退火製程之後， 閘極結構會具有一平整表面。 本發明為一種金屬矽化物閘極的製造方法，首先，提 供一底材，在底材上形成閘氧化層、摻雜複晶矽層、金屬 矽化物層與罩幕層，然後進行姓刻製程，蝕刻罩幕層、金 屬矽化物層、摻雜複晶矽層與閘氧化層，定義半導體元件 的閘極結構。進行離子佈植製程，在底材之中形成淡摻雜 汲極。接著，進行一濕蝕刻製程，對金屬矽化物層進行蝕 刻製程，形成一凹入形閘極結構，然後進行閘極結構的高 溫熱退火製程，金屬矽化物層在高溫之中快速成長。在高 溫熱退火製程之後，形成一個具有平滑表面的閘極結構。 圖式簡單說明： 第一圖係顯示一底材之剖面示意圖； 第二圖係顯示底材上沈積罩幕層、矽化金屬層、摻雜多 晶矽層及閘極氧化層之剖面示意圖； 第二圖係顯示在經過微影與钕刻製程之後，所定義出來 之閘極結構的剖面示意圖； 第四圖係顯示在經過離子佈植製程之後，在基板上形成 淡摻雜汲極的剖面示意圖； ------ 5 本紙ft尺度適用中關家標準（CNS ) M規格（叫^公益------ (請先閲讀背面之注意事項再填耗本頁) f 裝·A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 5. V. INTRODUCTION OF THE INVENTION () The compound layer grows at high temperatures to form a gate structure with a smooth surface. The invention provides a method for manufacturing a metal silicide gate. Before the high temperature annealing process of the gate structure, an etching process is performed on the metal silicide layer to form a recessed metal silicide gate. After the high temperature annealing process, the gate The structure will have a flat surface. The invention is a method for manufacturing a metal silicide gate. First, a substrate is provided, a gate oxide layer, a doped polycrystalline silicon layer, a metal silicide layer, and a mask layer are formed on the substrate, and then a surname engraving process is performed. , Etching the mask layer, the metal silicide layer, the doped polycrystalline silicon layer and the gate oxide layer to define the gate structure of the semiconductor element. An ion implantation process is performed to form a lightly doped drain in the substrate. Next, a wet etching process is performed to etch the metal silicide layer to form a recessed gate structure, and then a high temperature thermal annealing process of the gate structure is performed, and the metal silicide layer grows rapidly at high temperatures. After the high temperature thermal annealing process, a gate structure with a smooth surface is formed. Brief description of the drawings: The first diagram is a schematic sectional view of a substrate; the second diagram is a schematic sectional view of a mask layer, a silicided metal layer, a doped polycrystalline silicon layer, and a gate oxide layer deposited on the substrate; Figure 4 shows a schematic cross-section of the gate structure defined after the lithography and neodymium etching process. Figure 4 shows a schematic cross-section of a lightly doped drain electrode on the substrate after the ion implantation process;- ----- 5 The paper ft scale is applicable to the Zhongguanjia Standard (CNS) M specification (called ^ Public Welfare ------ (Please read the precautions on the back before filling out this page) f Loading ·
、1T -J線 經濟部中央標準局W3C工消費合作社印製 A7 B7 五、發明説明（） 第五圖係顯是在蝕刻閘極結構的矽化金屬層之後，形成 凹入形閘極結構的剖面示意圖； 第六A圖為依據本發明的方法，在高溫退火處理製程之 後’形成具有平整輪廓之閘極結構的剖面示意圖； 第六B圖係為在習知技術之中，在高溫退火製程之後， 形成具有突出矽化金屬層之閘極結構的剖面示意 圖； -第七A圖係為依據本發明的方法，於閘極結構的側壁形 成間隙層的剖面示意圖； 第七B圓係為習知技術之中，於閘極結構的側壁沈積間 隙層後，所得之閘極結構剖面示意圖； 第八A圖為依據本發明的方法，進行微影和離子佈植製 程，在底材中形成源極與汲極的剖面示意圖； 第八B圖係在習知技術之中，進行微影和離子植入製 程，在底材中形成源極與汲極的剖面示意圖； 第九A圖係為依據本發明的方法，在閘極結構上覆蓋一 内介電層的剖面示意圖； 第九B圖係在習知技術之中中，在閘極結構上覆蓋^内 介電層的剖面示意圖； 第十A圖係依據本發明的方法，在閘極結構上定義光阻 層的剖面示意圖； 第十B圖係在習知技術之中，在閘極結構上定義光阻的 剖面不意圖， t.— (請先閱讀背面"之注意事項再填寫本頁) 訂 線 61. A7 B7 printed by W3C Industrial and Consumer Cooperative of Central Standards Bureau of Ministry of Economic Affairs of 1T-J line. 5. Description of the invention () The fifth picture shows the cross-section of a recessed gate structure after etching the silicided metal layer of the gate structure. Figure 6A is a cross-sectional schematic diagram of a gate structure having a flat profile after the high temperature annealing process according to the method of the present invention; Figure 6B is a conventional technique after the high temperature annealing process A schematic cross-sectional view of a gate structure with a protruding silicided metal layer is formed.-The seventh A chart is a cross-sectional schematic diagram of forming a gap layer on the side wall of the gate structure according to the method of the present invention; the seventh B-circle system is a conventional technique. Among them, after the gap layer is deposited on the side wall of the gate structure, a schematic cross-sectional view of the gate structure is obtained. FIG. 8A is a method of lithography and ion implantation according to the method of the present invention to form a source electrode and a substrate in the substrate. A schematic cross-sectional view of a drain electrode; FIG. 8B is a cross-sectional schematic view of a source and a drain electrode formed in a substrate through a lithography and ion implantation process in a conventional technique; According to the method of the present invention, a schematic cross-sectional view of an inner dielectric layer covered on a gate structure; FIG. 9B is a cross-sectional view of an inner dielectric layer covered on a gate structure in the conventional technology; Figure A is a schematic cross-sectional view of a photoresist layer defined on the gate structure according to the method of the present invention; Figure 10B is a conventional technology that does not intend to define a photoresist profile on the gate structure, t. — (Please read the precautions on the back & fill in this page first) Thread 6
經濟部中央標準局負工消費合作社印製 第十一 a 圖、 一為依據本發明的方法，使用微影與蝕刻製 程’疋義自行對準接觸窗區域的剖面示意圖；以及 第十〜B圖係在習知技術之中，利用微影與關製程， 定義出自對準接觸窗區域的剖面示意圖。 乏二6發明詳細說日^ . 乂下將以矽化鎢（WSiz)作為本發明之實施例，說明在金 屬石夕化物閑極的製造過程中，在半導體元件中產生凹入形 金屬石夕化物結構的方法，但本發明之方法可延伸於自對準 接觸半導體元件之金屬碎化物閘極的製造過程。 本發明係在底材上製造一閘極結構，此閘極結構係包 含-閘極氧化層、-閘極多晶破層與—金屬梦化物層，在 閘極結構之上覆蓋一罩幕層，作為後續製程的保護罩幕。 接著，進行一濕蝕刻製程，對金屬矽化物層進行蝕刻製程， 產生一凹入形金屬閘極結構。然後，進行高溫退火製程， 金屬矽化物層在高溫中快速成長，形成具有平滑表面的閘 極結構。在完成閘極結構的製造之後，在閘極結構的兩侧 形成間隙壁’作為閘極結構的絕緣層。接著覆蓋一内介電 層在閘極結構與底材的表面，以罩幕層與侧壁作為姓刻罩 幕’在内介電層之中形成自對準接觸窗，作為半導體元件 的接觸窗。 首先，請參閱第一圊，提供一底材12，在底材12上定 義主動區、井區和場氧化層，而半導體元件是形成在主動 本紙張尺度適用中國國家#準（CNS) A4規格（210X297公漤） I r \ - ' I - - I I m Hal— Is— ·-1 士久 I- -I I (請先閱讀背面_之注意事項再填寫本頁)Figure 11a printed by the Central Bureau of Standards and Consumers ’Cooperative of the Ministry of Economic Affairs, one is a schematic cross-sectional view of the method of using the lithography and etching process according to the present invention to self-align the contact window area; and Figures 10 ~ B In the conventional technology, the lithography and closing processes are used to define the cross-sectional schematic diagram of the self-aligned contact window area. The second and sixth inventions are detailed in detail ^. His Majesty will use tungsten silicide (WSiz) as an embodiment of the present invention to explain the production of concave metal silicates in semiconductor elements during the manufacturing process of metal lithium anodes Structure method, but the method of the present invention can be extended to the manufacturing process of self-aligned contact semiconductor chip metal debris gate. The present invention is to manufacture a gate structure on a substrate. The gate structure includes -gate oxide layer, -gate polycrystalline fracture layer and -metal dream layer, and a gate layer is covered on the gate structure. , As a protective cover for subsequent processes. Next, a wet etching process is performed to etch the metal silicide layer to produce a concave metal gate structure. Then, a high temperature annealing process is performed, and the metal silicide layer grows rapidly at high temperature to form a gate structure with a smooth surface. After the fabrication of the gate structure is completed, gap walls' are formed on both sides of the gate structure as an insulating layer of the gate structure. Then cover an inner dielectric layer on the surface of the gate structure and the substrate, and use the mask layer and the side wall as the last name. The mask is formed in the inner dielectric layer to form a self-aligned contact window as a contact window of the semiconductor element. . First, please refer to the first section. Provide a substrate 12 on which the active area, well area, and field oxide layer are defined. The semiconductor element is formed on the active paper. Applicable to China Standard #CNS (A4) specifications. (210X297) 漤 I r \-'I--II m Hal— Is— · -1 Shijiu I- -II (Please read the precautions on the back _ before filling this page)
,1T i-線 A7 B7 五、發明説明（） 區之上，其中主動區、井區和場氧化層並未明白顯示於第 一圖之中。 經濟部中央標準局貝工消費合作社印裝 (讀先閲讀背面之注意事項存填寫本頁) 請參閱第二圖，在底材12上沈積閘極氧化層14、摻雜 多晶矽層16、金屬矽化物層18與罩幕層20 ,而摻雜多晶 矽層16與金屬矽化物層18是作為半導體元件的閘極結 構。在一較佳具體實施例之中，閘極氧化層14的形成方法 是使用熱氧化製程’在800至1100°C之高溫氧蒸氣環境之 中，形成二氧化矽層作為閘氧化層14 ;或者，閘極氧化層 14亦可以合適的氧化物之化學組合及程序來形成，可以使 用化學氣相沈積法來形成二氧化矽材料，而化學氣相沈積 法是以四乙基矽酸鹽（TEOS)形成在溫度6〇〇至800eC間且 壓力約0.1至1 Otorr。在一較佳具體實施例中，閘極氧化層 14的厚度係介於30到200埃之間。在一較佳具體實施例 中，摻雜多晶碎層16是以低壓化學氣相沈積法(LPCVD)的 方式，將石夕甲烧（Silane, SiHU)經加熱後解離，並於沈積反應 進行的同時摻雜N+型導電雜質，來形成所需要的含^^播雜 多晶矽層16，在沈積過程中’反應溫度係介於600至65〇 °0間，而工作壓力約在0.3至0.6t〇rr之間，摻雜多晶矽層 16的厚度係介於500到2500埃之間。 在摻雜多晶矽層16之上的矽化鎢層ι8,是以六氣化轉 (Tungsten Hexafluoride, WF6)為鎮的來源氣體，六氣化鎮與 石夕甲烧在300至40(TC間進行化學反應，再以低壓化學氣相 沈積製程的方式，在多晶梦層上形成厚約3〇〇到15〇〇埃 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 經濟部中央標準局另工消費合作社印^ B7五、發明説明（） 矽化金屬層，工作壓力係介於0.3到l.Otorr之間。 罩幕層20通常是氮化矽（Si3N4)層，或者是二氧化矽層 (Si02)和氮化矽層的組合層。在本發明之一較佳實施例之 中，將SiH2Cl2與NH3在溫度約700至800°C間、壓力約0.1 至l.Otorr間進行化學反應，以低壓化學氣相沈積法的方 式，形成厚約1500到3000埃氮化矽材料。 請參閱第三圖，使用微影與乾蝕刻製程，蝕刻罩幕層 20、矽化金屬層18、摻雜多晶矽層16及閘極氧化層14, 形成半導體元件的閘極結構。本發明的一較佳實施例之 中，蝕刻矽化金屬層18及摻雜多晶矽層16，先以WF2和 WC14進行金屬矽化物層18的蝕刻，再以Cl2、HC1和SiCl4 等氣體作為蝕刻反應氣體，對摻雜多晶矽層16進行非等向 性的钱刻反應。 請參閱第四圖，進行離子佈植製程，在底材12之中摻 入導電雜質，在底材12之中形成淡摻雜汲極22,可防止在 半導體元件之中發生短通道效應（short channel effect)。 請參閱第五圖，進行蝕刻製程，對金屬矽化物層18進 行蝕刻製程，形成凹入的閘極結構。根據本發明的較佳具 體實施例，蝕刻金屬矽化物層18，是使用濕蝕刻製程，所 使用的蝕刻液為nh4oh、h2o2和H20的混合溶液。在蝕刻 製程之後，於閘極兩側的金屬矽化物層18之上產生1到5 微米的凹入深度。然而，上述之凹入深度並非固定，其凹 入深度的大小決定於蝕刻溶液的蝕刻速率，以及後續高溫 9 (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公犮） Μ Β7 經濟部中央標準局貝工消t合作社印製 五、發明説明（） 退火製程之中中金屬矽化物的成長速率，其淨效應是希望 在高溫退火製程之後，金屬矽化物層18不會突出於閘極的 表面。 請參閱第六A圖，進行高溫退火處理製程，使得金屬 矽化物層18在高溫下成長。在本發明之一較佳實施例，是 將晶片送入熱擴散爐内，在900到1000°C左右的高溫進行 退火製程。在進行高溫退火製程時，金屬矽化物層18以較 快的速率成長，然而由於事先已經使用蝕刻溶液對金屬矽 化物層18進行蝕刻，因此高溫退火製程之後，將得到具有 平滑表面的閘極結構。 請參閱第七A圖，在閘極結構的兩側形成間隙層24， 作為閘極結構的絕緣保護層，在一較佳實施例之中，間隙 層24的組成材料為二氧化矽材料。請參閱第八A圖，進行 離子佈植製程，利用罩幕層20與間隙層24作為離子佈植 罩冪，將導電雜質植入於底材12之中，在底材12之中形 成源汲極區域26。 請參閱第九A圖，在閘極結構上沈積内介電層28，並 覆蓋在底材12之上，内介電層28的組成材料包括未摻雜 二氧化矽材料和硼磷摻雜四乙基矽酸鹽（BPTEOS)。 請參閱第十A圖，在内介電層28上覆蓋光阻層30， 定義出半導體元件的自對準區域。請參閱第十一 A圖，利 用微影與蝕刻製程，以罩幕層20與間隙層24作為蝕刻罩 幕，對内介電層28進行蝕刻製程，在内介電層28之中形 10 (請先閣讀背面乏注意事項再填寫本頁) -a Γ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公尨) A7 B7 五、發明説明（ 成自對準接觸窗32,作為半導體元件的源汲極區域％的接 觸窗。最後，進行一般的製程，完成半導體元件的製造過 程》 本發明以較佳實施例說明如上’而熟悉此領域 技藝者，在不脫離本發明之精神範圍内，當可作些 許更動潤飾’其專利保護範圍更當視後附之申請專 利範圍及其等同領域而定。例如钱刻金屬石夕化物層所 使用之NH4〇H、H2〇2與h2o的混合溶液，為目前業界廣泛 使用之蝕刻液，當然也可以其他等效的蝕刻液替換之。 (請先閱讀背面之注意事項再填离本頁) •举· -** Γ 經濟部中央標傘局負工消费合作社印製 «1 —1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公炱）1T i-line A7 B7 V. Description of the invention () area, in which the active area, well area and field oxide layer are not clearly shown in the first picture. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (read the precautions on the back and fill in this page) Please refer to the second picture, deposit the gate oxide layer 14, the doped polycrystalline silicon layer 16, and the metal silicide on the substrate 12. The object layer 18 and the mask layer 20, and the doped polycrystalline silicon layer 16 and the metal silicide layer 18 are gate structures of semiconductor devices. In a preferred embodiment, the gate oxide layer 14 is formed by using a thermal oxidation process to form a silicon dioxide layer as the gate oxide layer 14 in a high-temperature oxygen vapor environment at 800 to 1100 ° C; or The gate oxide layer 14 can also be formed by a suitable chemical combination and procedure of the oxide. A chemical vapor deposition method can be used to form a silicon dioxide material, and the chemical vapor deposition method is based on tetraethyl silicate (TEOS ) Is formed between a temperature of 600 to 800 eC and a pressure of about 0.1 to 1 Otorr. In a preferred embodiment, the thickness of the gate oxide layer 14 is between 30 and 200 angstroms. In a preferred embodiment, the doped polycrystalline debris layer 16 is a low-pressure chemical vapor deposition (LPCVD) method in which Silane (SiHU) is heated and dissociated, and the deposition reaction proceeds. N + -type conductive impurities are simultaneously doped to form the required polysilicon-containing polycrystalline silicon layer 16. During the deposition process, the reaction temperature is between 600 and 65 °, and the working pressure is about 0.3 to 0.6t. The thickness of the doped polycrystalline silicon layer 16 is between 500 and 2500 angstroms. The tungsten silicide layer ι8 over the doped polycrystalline silicon layer 16 is a source gas using Tungsten Hexafluoride (WF6) as the town source. Reaction, and then form a low-pressure chemical vapor deposition process to form a thickness of about 3,000 to 15,000 angstroms on the polycrystalline dream layer. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 Ministry of Economic Affairs Printed by the Central Bureau of Standards and Consumers' Cooperatives ^ B7 V. Description of the invention () Siliconized metal layer, the working pressure is between 0.3 and 1.0 Torr. The mask layer 20 is usually a silicon nitride (Si3N4) layer, or two A combined layer of a silicon oxide layer (Si02) and a silicon nitride layer. In a preferred embodiment of the present invention, SiH2Cl2 and NH3 are performed at a temperature of about 700 to 800 ° C and a pressure of about 0.1 to 1.0 Torr. The chemical reaction uses a low pressure chemical vapor deposition method to form a silicon nitride material with a thickness of about 1500 to 3000 angstroms. Please refer to the third figure, using a lithography and dry etching process to etch the mask layer 20, the silicided metal layer 18, Doped polycrystalline silicon layer 16 and gate oxide layer 14 to form a gate of a semiconductor device Structure. In a preferred embodiment of the present invention, the silicided metal layer 18 and the doped polycrystalline silicon layer 16 are etched. The metal silicide layer 18 is etched with WF2 and WC14, and then the gas such as Cl2, HC1, and SiCl4 is used as the etching. A reactive gas performs an anisotropic coin-cut reaction on the doped polycrystalline silicon layer 16. Referring to the fourth figure, an ion implantation process is performed, conductive impurities are doped in the substrate 12, and a thin layer is formed in the substrate 12. Doping the drain electrode 22 can prevent a short channel effect from occurring in the semiconductor device. Referring to the fifth figure, an etching process is performed, and the metal silicide layer 18 is etched to form a recessed gate structure. According to a preferred embodiment of the present invention, the metal silicide layer 18 is etched using a wet etching process, and the etching solution used is a mixed solution of nh4oh, h2o2, and H20. After the etching process, the A recessed depth of 1 to 5 microns is generated on the metal silicide layer 18. However, the recessed depth described above is not fixed, and the size of the recessed depth is determined by the etching rate of the etching solution and the subsequent high temperature 9 ( Please read the notes on the back before filling this page) • Binding. The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X 297 cm) Μ Β7 Printed by the Central Laboratories of the Ministry of Economic Affairs The net effect of the growth rate of the metal silicide during the annealing process is that the metal silicide layer 18 does not protrude from the surface of the gate after the high temperature annealing process. Please refer to FIG. 6A for high temperature The annealing process makes the metal silicide layer 18 grow at a high temperature. In a preferred embodiment of the present invention, the wafer is sent into a thermal diffusion furnace and an annealing process is performed at a high temperature of about 900 to 1000 ° C. During the high temperature annealing process, the metal silicide layer 18 grows at a faster rate. However, since the metal silicide layer 18 has been etched using an etching solution in advance, a gate structure with a smooth surface will be obtained after the high temperature annealing process. . Referring to FIG. 7A, a gap layer 24 is formed on both sides of the gate structure as an insulating protection layer of the gate structure. In a preferred embodiment, the composition material of the gap layer 24 is a silicon dioxide material. Referring to FIG. 8A, the ion implantation process is performed. The mask layer 20 and the gap layer 24 are used as the ion implantation mask to implant conductive impurities in the substrate 12 to form a source sink in the substrate 12.极 区 26。 The polar region 26. Referring to FIG. 9A, an inner dielectric layer 28 is deposited on the gate structure and covered on the substrate 12. The material of the inner dielectric layer 28 includes undoped silicon dioxide material and boron-phosphorus doped Ethyl Silicate (BPTEOS). Referring to FIG. 10A, the photoresist layer 30 is covered on the inner dielectric layer 28 to define a self-aligned region of the semiconductor device. Referring to FIG. 11A, using the lithography and etching process, using the mask layer 20 and the gap layer 24 as an etching mask, the inner dielectric layer 28 is etched, and the inner dielectric layer 28 is shaped 10 ( Please read the lack of attention on the back before filling in this page) -a Γ This paper size applies Chinese National Standard (CNS) A4 specification (210X297 cm) A7 B7 V. Description of the invention (Self-aligned contact window 32 as semiconductor The contact window of the source-drain region of the device. Finally, a general process is performed to complete the manufacturing process of the semiconductor device. "The present invention is described above with a preferred embodiment, and those skilled in the art will not depart from the spirit of the present invention. In addition, it can be modified a little bit. The scope of its patent protection depends more on the scope of the attached patent application and its equivalent fields. For example, the NH4OH, H2O2 and h2o The mixed solution is an etching solution widely used in the industry at present, and of course, it can also be replaced by other equivalent etching solutions. (Please read the precautions on the back before filling out this page) • Lift ·-** Γ Central Ministry of Economic Affairs Standard Umbrella Office work Fee cooperatives print << 1-1 scale in this paper applies China National Standard (CNS) A4 size (210X297 public soot)